Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3523279	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3947226

1

T1

1975

T2

12

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6798559	1			T1	3770		T2	5		T3	32
values[0x0]	334685	1			T1	103		T2	9		T3	13
values[0x1]	337261	1			T1	104		T2	6		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2800075	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4670430

1

T1

2389

T2

16

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23440	1			T5	8		T10	1		T11	21
valid_sources[0x01]	22711	1			T5	2		T10	2		T11	20
valid_sources[0x02]	23098	1			T5	3		T10	6		T11	12
valid_sources[0x03]	25428	1			T5	4		T10	3		T11	17
valid_sources[0x04]	23708	1			T4	11		T5	2		T10	2
valid_sources[0x05]	26404	1			T5	6		T10	3		T11	14
valid_sources[0x06]	77792	1			T5	12		T11	12		T12	2
valid_sources[0x07]	35301	1			T4	9		T11	18		T13	1
valid_sources[0x08]	22153	1			T1	17		T5	11		T10	1
valid_sources[0x09]	25679	1			T4	6		T10	2		T11	26
valid_sources[0x0a]	21299	1			T4	6		T5	20		T10	3
valid_sources[0x0b]	22171	1			T5	2		T10	1		T11	10
valid_sources[0x0c]	23624	1			T11	16		T15	5		T47	13
valid_sources[0x0d]	41067	1			T5	5		T10	4		T11	18
valid_sources[0x0e]	21927	1			T5	28		T10	3		T11	11
valid_sources[0x0f]	25372	1			T5	1		T10	3		T11	12
valid_sources[0x10]	21853	1			T5	2		T10	2		T11	19
valid_sources[0x11]	21556	1			T10	2		T11	18		T12	2
valid_sources[0x12]	21400	1			T5	13		T10	1		T11	13
valid_sources[0x13]	22797	1			T5	7		T10	1		T11	14
valid_sources[0x14]	21184	1			T10	4		T11	23		T14	1
valid_sources[0x15]	22328	1			T5	2		T10	3		T11	8
valid_sources[0x16]	24523	1			T5	4		T10	1		T11	25
valid_sources[0x17]	68748	1			T4	4		T5	8		T10	3
valid_sources[0x18]	22372	1			T4	5		T10	3		T11	13
valid_sources[0x19]	25866	1			T10	3		T11	19		T12	9
valid_sources[0x1a]	25749	1			T5	13		T10	2		T11	12
valid_sources[0x1b]	22506	1			T10	3		T11	14		T13	1
valid_sources[0x1c]	24060	1			T5	5		T10	6		T11	12
valid_sources[0x1d]	40114	1			T5	25		T10	1		T11	13
valid_sources[0x1e]	24596	1			T10	2		T11	15		T13	1
valid_sources[0x1f]	21159	1			T4	16		T10	2		T11	17
valid_sources[0x20]	21614	1			T5	10		T10	5		T11	20
valid_sources[0x21]	27279	1			T10	1		T11	22		T13	1
valid_sources[0x22]	20985	1			T5	1		T10	2		T11	12
valid_sources[0x23]	24473	1			T5	17		T10	2		T11	17
valid_sources[0x24]	21335	1			T5	5		T10	4		T11	22
valid_sources[0x25]	21404	1			T5	6		T10	2		T11	10
valid_sources[0x26]	22196	1			T5	3		T10	2		T11	13
valid_sources[0x27]	23277	1			T10	3		T11	16		T13	2
valid_sources[0x28]	25222	1			T5	3		T10	3		T11	18
valid_sources[0x29]	20983	1			T5	2		T10	1		T11	16
valid_sources[0x2a]	50902	1			T5	1		T11	14		T12	4
valid_sources[0x2b]	21959	1			T4	2		T5	4		T10	3
valid_sources[0x2c]	22536	1			T3	1		T10	2		T11	9
valid_sources[0x2d]	21761	1			T5	4		T10	7		T11	20
valid_sources[0x2e]	21840	1			T5	3		T10	2		T11	21
valid_sources[0x2f]	23785	1			T5	14		T10	3		T11	13
valid_sources[0x30]	23911	1			T5	13		T10	1		T11	15
valid_sources[0x31]	21472	1			T10	5		T11	18		T12	5
valid_sources[0x32]	21428	1			T10	3		T11	18		T13	3
valid_sources[0x33]	25145	1			T5	2		T10	5		T11	9
valid_sources[0x34]	57424	1			T5	12		T10	2		T11	18
valid_sources[0x35]	106094	1			T3	5		T5	4		T10	1
valid_sources[0x36]	21166	1			T10	1		T11	22		T13	1
valid_sources[0x37]	21466	1			T5	2		T10	4		T11	11
valid_sources[0x38]	22649	1			T10	3		T11	11		T13	2
valid_sources[0x39]	25539	1			T5	1		T10	4		T11	12
valid_sources[0x3a]	139461	1			T5	1		T10	8		T11	16
valid_sources[0x3b]	26693	1			T5	1		T10	6		T11	11
valid_sources[0x3c]	40446	1			T5	1		T10	3		T11	17
valid_sources[0x3d]	23519	1			T3	8		T10	4		T11	11
valid_sources[0x3e]	21188	1			T5	28		T10	4		T11	16
valid_sources[0x3f]	24584	1			T5	9		T10	3		T11	14
valid_sources[0x40]	26748	1			T10	2		T11	21		T15	8
valid_sources[0x41]	21400	1			T5	7		T10	5		T11	18
valid_sources[0x42]	26315	1			T5	3		T10	1		T11	16
valid_sources[0x43]	22052	1			T5	2		T10	5		T11	6
valid_sources[0x44]	22315	1			T4	5		T5	15		T10	4
valid_sources[0x45]	27278	1			T10	3		T11	10		T13	3
valid_sources[0x46]	21251	1			T5	13		T10	4		T11	13
valid_sources[0x47]	21464	1			T5	17		T10	3		T11	18
valid_sources[0x48]	105792	1			T10	4		T11	21		T13	1
valid_sources[0x49]	21379	1			T10	2		T11	11		T13	3
valid_sources[0x4a]	42324	1			T4	1		T5	1		T10	4
valid_sources[0x4b]	23071	1			T5	22		T10	9		T11	14
valid_sources[0x4c]	31567	1			T10	1		T11	13		T12	5
valid_sources[0x4d]	37479	1			T5	8		T10	2		T11	20
valid_sources[0x4e]	56771	1			T10	2		T11	10		T12	1
valid_sources[0x4f]	21219	1			T5	2		T11	13		T13	1
valid_sources[0x50]	22459	1			T4	5		T5	16		T10	4
valid_sources[0x51]	21718	1			T5	8		T10	1		T11	10
valid_sources[0x52]	23350	1			T4	10		T5	3		T10	2
valid_sources[0x53]	23633	1			T5	1		T10	2		T11	10
valid_sources[0x54]	22299	1			T5	6		T10	1		T11	17
valid_sources[0x55]	22119	1			T5	4		T10	3		T11	19
valid_sources[0x56]	23277	1			T5	7		T10	5		T11	14
valid_sources[0x57]	21635	1			T5	9		T10	2		T11	13
valid_sources[0x58]	21555	1			T5	5		T10	1		T11	18
valid_sources[0x59]	23958	1			T5	2		T10	2		T11	18
valid_sources[0x5a]	42293	1			T5	10		T10	1		T11	13
valid_sources[0x5b]	81577	1			T11	12		T14	6		T15	4
valid_sources[0x5c]	22786	1			T5	26		T10	4		T11	9
valid_sources[0x5d]	21832	1			T5	2		T11	15		T13	3
valid_sources[0x5e]	132997	1			T10	2		T11	16		T12	2
valid_sources[0x5f]	77518	1			T10	6		T11	21		T12	2
valid_sources[0x60]	112040	1			T10	7		T11	18		T13	2
valid_sources[0x61]	21436	1			T11	22		T13	4		T14	1
valid_sources[0x62]	22487	1			T10	5		T11	20		T12	7
valid_sources[0x63]	21507	1			T5	1		T11	13		T14	1
valid_sources[0x64]	23276	1			T4	3		T10	1		T11	15
valid_sources[0x65]	32800	1			T10	1		T11	17		T12	19
valid_sources[0x66]	21778	1			T5	11		T10	1		T11	14
valid_sources[0x67]	37513	1			T4	2		T5	13		T10	2
valid_sources[0x68]	21531	1			T5	5		T10	3		T11	12
valid_sources[0x69]	23256	1			T1	17		T10	4		T11	19
valid_sources[0x6a]	21318	1			T5	12		T10	4		T11	20
valid_sources[0x6b]	33730	1			T5	3		T10	2		T11	20
valid_sources[0x6c]	21933	1			T5	53		T10	7		T11	20
valid_sources[0x6d]	21573	1			T5	11		T10	2		T11	10
valid_sources[0x6e]	21066	1			T11	17		T12	7		T13	1
valid_sources[0x6f]	21823	1			T5	7		T10	2		T11	16
valid_sources[0x70]	22755	1			T5	28		T10	3		T11	14
valid_sources[0x71]	22013	1			T5	8		T10	1		T11	10
valid_sources[0x72]	21977	1			T10	4		T11	14		T13	1
valid_sources[0x73]	22407	1			T10	4		T11	21		T13	1
valid_sources[0x74]	21446	1			T5	8		T11	15		T14	1
valid_sources[0x75]	46184	1			T10	1		T11	12		T13	1
valid_sources[0x76]	21406	1			T4	3		T10	5		T11	12
valid_sources[0x77]	23705	1			T5	11		T10	1		T11	20
valid_sources[0x78]	21720	1			T11	13		T12	1		T14	2
valid_sources[0x79]	22530	1			T5	2		T10	1		T11	10
valid_sources[0x7a]	21779	1			T10	1		T11	30		T13	2
valid_sources[0x7b]	25209	1			T5	26		T10	1		T11	11
valid_sources[0x7c]	23214	1			T10	1		T11	7		T13	1
valid_sources[0x7d]	22462	1			T5	11		T11	15		T12	9
valid_sources[0x7e]	24796	1			T10	2		T11	15		T12	15
valid_sources[0x7f]	22072	1			T5	23		T10	4		T11	13
valid_sources[0x80]	32514	1			T5	34		T10	3		T11	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3368779

1

T1

1796

T3

13

T4

55

values[0x0]

all_enables

biggest_size

289724

1

T1

91

T2

8

T3

6

values[0x1]

all_enables

biggest_size

288723

1

T1

88

T2

4

T3

8