Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.88		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	202926636	25690	0	0
claim_transition_if_regwen_rd_A	202926636	2325	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202926636	25690	0	0
T22	146451	7	0	0
T45	298211	7	0	0
T52	157497	0	0	0
T56	57620	0	0	0
T61	0	14	0	0
T62	37847	0	0	0
T63	59175	0	0	0
T83	34323	0	0	0
T100	28848	0	0	0
T106	1814	0	0	0
T132	0	11	0	0
T192	0	2	0	0
T193	0	16	0	0
T194	0	1	0	0
T195	0	6	0	0
T196	0	4	0	0
T197	0	10	0	0
T198	182273	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202926636	2325	0	0
T7	68190	0	0	0
T39	1376	0	0	0
T45	298211	7	0	0
T77	225803	0	0	0
T79	19373	0	0	0
T93	104085	0	0	0
T136	0	13	0	0
T185	0	5	0	0
T192	0	5	0	0
T194	0	1	0	0
T198	182273	0	0	0
T199	0	6	0	0
T200	0	2	0	0
T201	0	2	0	0
T202	0	1	0	0
T203	0	20	0	0
T204	25752	0	0	0
T205	28625	0	0	0
T206	22929	0	0	0