Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.00	60.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex	60.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	4	6	60.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	4	6	60.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	4	6	60.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
false	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	5268	1			T7	40		T8	38		T9	18
others[1]	4	1			T244	1		T245	1		T246	1
others[2]	2	1			T247	1		T248	1		-	-
others[3]	1	1			T249	1		-	-		-	-
others[4]	3	1			T250	1		T251	1		T252	1
true	83891	1			T1	15		T3	74		T4	9