Unified Coverage Report :: Module :: dmi_cdc

Module : dmi_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.36			96.36

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc	96.95			96.95

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.95			96.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26			97.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.56			95.56				u_dmi_jtag

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_cdc_req	99.32			99.32
i_cdc_resp	97.73			97.73
u_combined_rstn_sync	90.91			90.91
u_rst_mux	75.00			75.00

Toggle Coverage for Module : dmi_cdc

	Total	Covered	Percent
Totals	25	21	84.00
Total Bits	330	318	96.36
Total Bits 0->1	165	159	96.36
Total Bits 1->0	165	159	96.36

Ports	25	21	84.00
Port Bits	330	318	96.36
Port Bits 0->1	165	159	96.36
Port Bits 1->0	165	159	96.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tck_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
trst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
jtag_dmi_req_i.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_req_i.op[1:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_req_i.addr[6:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_ready_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
jtag_dmi_valid_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_cdc_clear_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_resp_o.resp[1:0]	No	No		No		OUTPUT
jtag_dmi_resp_o.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
jtag_dmi_valid_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
jtag_dmi_ready_i	Unreachable	Unreachable		Unreachable		INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
core_dmi_rst_no	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.op[1:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.addr[5:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.addr[6]	No	No		No		OUTPUT
core_dmi_valid_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_ready_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
core_dmi_resp_i.resp[1:0]	No	No		No		INPUT
core_dmi_resp_i.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
core_dmi_ready_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_valid_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc

	Total	Covered	Percent
Totals	25	21	84.00
Total Bits	328	318	96.95
Total Bits 0->1	163	159	97.55
Total Bits 1->0	165	159	96.36

Ports	25	21	84.00
Port Bits	328	318	96.95
Port Bits 0->1	163	159	97.55
Port Bits 1->0	165	159	96.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
testmode_i	No	No		No		INPUT
test_rst_ni	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tck_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
trst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
jtag_dmi_req_i.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_req_i.op[1:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_req_i.addr[6:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_ready_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
jtag_dmi_valid_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_cdc_clear_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
jtag_dmi_resp_o.resp[1:0]	No	No		Excluded		OUTPUT	0->1:VC_COV_UNR
jtag_dmi_resp_o.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
jtag_dmi_valid_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
jtag_dmi_ready_i	Unreachable	Unreachable		Unreachable		INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
core_dmi_rst_no	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.op[1:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.addr[5:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_req_o.addr[6]	No	No		No		OUTPUT
core_dmi_valid_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_ready_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
core_dmi_resp_i.resp[1:0]	No	No		No		INPUT
core_dmi_resp_i.data[31:0]	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
core_dmi_ready_o	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	OUTPUT
core_dmi_valid_i	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT