Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	199146729	14078	0	0
claim_transition_if_regwen_rd_A	199146729	1113	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199146729	14078	0	0
T17	384038	18	0	0
T18	136317	0	0	0
T19	128626	0	0	0
T36	0	1	0	0
T42	21524	0	0	0
T49	0	14	0	0
T53	50023	0	0	0
T95	0	1	0	0
T133	0	3	0	0
T135	0	2	0	0
T170	0	2	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	27255	0	0	0
T175	15886	0	0	0
T176	24011	0	0	0
T177	37475	0	0	0
T178	25230	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199146729	1113	0	0
T101	0	11	0	0
T120	12330	0	0	0
T141	0	60	0	0
T143	0	9	0	0
T169	0	67	0	0
T171	239307	6	0	0
T172	0	1	0	0
T179	0	7	0	0
T180	0	5	0	0
T181	0	2	0	0
T182	0	1	0	0
T183	43436	0	0	0
T184	20663	0	0	0
T185	28814	0	0	0
T186	1103	0	0	0
T187	1633	0	0	0
T188	27027	0	0	0
T189	50601	0	0	0
T190	32966	0	0	0