Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3116966	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3519994

1

T1

222

T2

5

T4

111

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5998192	1			T1	272		T4	107		T6	1153
values[0x0]	318678	1			T1	61		T2	14		T4	41
values[0x1]	320090	1			T1	62		T2	17		T4	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2475384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4161576

1

T1

265

T2

8

T4

130

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17707	1			T1	3		T10	3		T12	2
valid_sources[0x01]	19278	1			T10	12		T12	6		T13	14
valid_sources[0x02]	17972	1			T4	1		T10	2		T12	3
valid_sources[0x03]	21984	1			T4	1		T10	3		T12	2
valid_sources[0x04]	18827	1			T1	2		T10	9		T12	7
valid_sources[0x05]	17748	1			T10	6		T12	6		T13	10
valid_sources[0x06]	20538	1			T1	2		T4	1		T10	5
valid_sources[0x07]	17726	1			T1	3		T10	2		T12	3
valid_sources[0x08]	17354	1			T1	1		T4	1		T10	9
valid_sources[0x09]	19305	1			T1	2		T10	5		T12	4
valid_sources[0x0a]	20680	1			T1	2		T10	9		T12	3
valid_sources[0x0b]	19086	1			T1	1		T2	1		T10	4
valid_sources[0x0c]	17908	1			T1	1		T12	2		T13	8
valid_sources[0x0d]	18260	1			T1	1		T4	1		T10	4
valid_sources[0x0e]	29042	1			T4	2		T10	6		T12	4
valid_sources[0x0f]	26119	1			T1	1		T4	1		T10	5
valid_sources[0x10]	19198	1			T1	2		T2	1		T4	2
valid_sources[0x11]	25446	1			T10	2		T12	2		T13	10
valid_sources[0x12]	17511	1			T1	3		T4	1		T10	2
valid_sources[0x13]	19309	1			T10	3		T12	4		T13	11
valid_sources[0x14]	26108	1			T1	3		T4	1		T10	4
valid_sources[0x15]	22161	1			T1	1		T4	3		T10	7
valid_sources[0x16]	21268	1			T10	1		T12	6		T13	11
valid_sources[0x17]	22124	1			T10	7		T12	3		T13	9
valid_sources[0x18]	24153	1			T1	2		T10	8		T12	4
valid_sources[0x19]	17306	1			T1	2		T10	1		T12	5
valid_sources[0x1a]	21203	1			T10	1		T12	6		T13	5
valid_sources[0x1b]	17620	1			T1	1		T4	2		T10	1
valid_sources[0x1c]	17747	1			T4	4		T10	4		T12	9
valid_sources[0x1d]	17946	1			T1	1		T2	1		T10	2
valid_sources[0x1e]	23166	1			T1	3		T10	5		T12	5
valid_sources[0x1f]	18484	1			T1	1		T2	1		T4	1
valid_sources[0x20]	17438	1			T1	3		T10	1		T12	2
valid_sources[0x21]	52682	1			T1	1		T10	8		T12	6
valid_sources[0x22]	18725	1			T10	3		T12	5		T13	7
valid_sources[0x23]	20163	1			T1	4		T10	7		T12	6
valid_sources[0x24]	17370	1			T1	3		T4	1		T10	6
valid_sources[0x25]	38374	1			T10	2		T12	1		T13	11
valid_sources[0x26]	19468	1			T1	2		T4	2		T10	1
valid_sources[0x27]	18446	1			T12	2		T13	8		T68	6
valid_sources[0x28]	17236	1			T1	2		T10	8		T12	6
valid_sources[0x29]	32957	1			T1	2		T4	1		T10	1
valid_sources[0x2a]	18078	1			T1	5		T10	11		T12	4
valid_sources[0x2b]	17873	1			T4	1		T10	5		T12	7
valid_sources[0x2c]	17650	1			T1	1		T2	1		T4	5
valid_sources[0x2d]	53997	1			T1	1		T10	1		T12	5
valid_sources[0x2e]	18026	1			T4	1		T10	5		T12	3
valid_sources[0x2f]	17872	1			T10	2		T12	6		T13	7
valid_sources[0x30]	33884	1			T1	3		T4	2		T10	2
valid_sources[0x31]	18565	1			T10	4		T12	6		T13	16
valid_sources[0x32]	18119	1			T1	3		T10	5		T12	1
valid_sources[0x33]	18813	1			T10	1		T12	6		T13	3
valid_sources[0x34]	18959	1			T10	8		T12	4		T13	5
valid_sources[0x35]	40487	1			T1	1		T4	1		T10	2
valid_sources[0x36]	17666	1			T4	1		T10	3		T12	9
valid_sources[0x37]	19053	1			T1	1		T10	5		T12	6
valid_sources[0x38]	17721	1			T1	2		T10	8		T12	1
valid_sources[0x39]	84983	1			T10	5		T12	1		T13	11
valid_sources[0x3a]	23974	1			T2	1		T10	4		T12	5
valid_sources[0x3b]	18114	1			T1	2		T4	1		T10	4
valid_sources[0x3c]	17635	1			T2	1		T10	3		T12	3
valid_sources[0x3d]	17764	1			T10	2		T12	1		T13	5
valid_sources[0x3e]	17823	1			T1	1		T10	4		T12	1
valid_sources[0x3f]	23372	1			T2	1		T4	2		T10	3
valid_sources[0x40]	65171	1			T1	3		T4	2		T10	2
valid_sources[0x41]	18127	1			T1	10		T4	1		T10	2
valid_sources[0x42]	18911	1			T1	1		T10	5		T12	2
valid_sources[0x43]	18006	1			T1	5		T4	2		T10	6
valid_sources[0x44]	58769	1			T1	1		T4	1		T10	1
valid_sources[0x45]	19436	1			T1	1		T4	1		T12	5
valid_sources[0x46]	83316	1			T10	1		T12	3		T13	4
valid_sources[0x47]	107174	1			T4	1		T10	1		T12	2
valid_sources[0x48]	37283	1			T12	2		T13	8		T68	3
valid_sources[0x49]	18111	1			T1	2		T2	1		T10	4
valid_sources[0x4a]	17723	1			T1	2		T4	2		T10	3
valid_sources[0x4b]	18972	1			T1	2		T4	4		T10	7
valid_sources[0x4c]	17831	1			T1	1		T10	2		T12	4
valid_sources[0x4d]	18116	1			T1	1		T4	1		T10	2
valid_sources[0x4e]	17577	1			T1	3		T10	2		T12	3
valid_sources[0x4f]	20019	1			T1	2		T10	1		T12	4
valid_sources[0x50]	128072	1			T1	3		T4	2		T10	12
valid_sources[0x51]	18841	1			T1	1		T10	1		T12	10
valid_sources[0x52]	80537	1			T4	1		T10	9		T12	2
valid_sources[0x53]	18751	1			T1	1		T10	2		T12	6
valid_sources[0x54]	17786	1			T10	3		T12	6		T13	6
valid_sources[0x55]	18905	1			T1	3		T4	1		T10	11
valid_sources[0x56]	20696	1			T1	1		T10	2		T12	5
valid_sources[0x57]	18969	1			T1	2		T10	9		T12	2
valid_sources[0x58]	17860	1			T10	5		T12	2		T13	6
valid_sources[0x59]	19949	1			T1	3		T10	1		T12	1
valid_sources[0x5a]	17596	1			T1	1		T2	2		T10	1
valid_sources[0x5b]	24691	1			T1	1		T10	5		T12	2
valid_sources[0x5c]	148246	1			T1	1		T10	7		T12	6
valid_sources[0x5d]	22709	1			T1	3		T2	1		T10	5
valid_sources[0x5e]	73826	1			T1	3		T10	4		T12	2
valid_sources[0x5f]	35122	1			T1	1		T10	3		T12	4
valid_sources[0x60]	17919	1			T1	3		T10	3		T12	9
valid_sources[0x61]	41229	1			T4	1		T12	1		T13	17
valid_sources[0x62]	18505	1			T12	2		T13	10		T67	6
valid_sources[0x63]	27912	1			T1	3		T4	2		T10	6
valid_sources[0x64]	17715	1			T10	11		T12	5		T13	7
valid_sources[0x65]	18019	1			T1	2		T10	7		T12	13
valid_sources[0x66]	18335	1			T1	1		T4	1		T10	6
valid_sources[0x67]	19867	1			T1	1		T4	3		T10	4
valid_sources[0x68]	18373	1			T1	2		T4	1		T10	9
valid_sources[0x69]	21294	1			T1	1		T4	1		T10	3
valid_sources[0x6a]	17888	1			T4	2		T10	3		T12	5
valid_sources[0x6b]	19209	1			T1	2		T10	3		T12	2
valid_sources[0x6c]	17965	1			T1	1		T10	1		T12	3
valid_sources[0x6d]	18542	1			T4	4		T10	1		T12	7
valid_sources[0x6e]	20360	1			T1	1		T4	1		T10	1
valid_sources[0x6f]	17697	1			T4	1		T10	1		T12	4
valid_sources[0x70]	19511	1			T10	6		T12	2		T13	7
valid_sources[0x71]	22549	1			T1	1		T12	3		T13	14
valid_sources[0x72]	18484	1			T1	5		T10	2		T12	9
valid_sources[0x73]	19323	1			T4	3		T10	9		T12	8
valid_sources[0x74]	21015	1			T4	1		T10	6		T12	3
valid_sources[0x75]	18177	1			T1	2		T10	5		T12	4
valid_sources[0x76]	18322	1			T1	5		T10	5		T12	2
valid_sources[0x77]	18386	1			T10	7		T13	9		T67	4
valid_sources[0x78]	19226	1			T1	5		T4	2		T10	9
valid_sources[0x79]	18193	1			T1	3		T10	2		T12	1
valid_sources[0x7a]	116021	1			T1	3		T2	1		T10	3
valid_sources[0x7b]	31389	1			T1	2		T4	2		T10	5
valid_sources[0x7c]	18942	1			T1	4		T4	1		T10	8
valid_sources[0x7d]	20165	1			T1	1		T10	5		T12	7
valid_sources[0x7e]	20367	1			T1	2		T10	6		T12	6
valid_sources[0x7f]	19102	1			T1	1		T4	1		T10	2
valid_sources[0x80]	18988	1			T10	2		T12	4		T13	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2971563

1

T1

124

T4

47

T6

485

values[0x0]

all_enables

biggest_size

274877

1

T1

50

T2

3

T4

36

values[0x1]

all_enables

biggest_size

273554

1

T1

48

T2

2

T4

28