Unified Coverage Report :: Design subhierarchy

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
lc_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_dmi_jtag	96.13			96.13
i_dmi_cdc	97.26			97.26
i_cdc_req	99.32			99.32
u_prim_sync_reqack	100.00			100.00
gen_rz_hs_protocol.ack_sync	100.00			100.00
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
u_sync_2	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
gen_rz_hs_protocol.req_sync	100.00			100.00
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
u_sync_2	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
i_cdc_resp	97.73			97.73
u_prim_sync_reqack	100.00			100.00
gen_rz_hs_protocol.ack_sync	100.00			100.00
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
u_sync_2	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
gen_rz_hs_protocol.req_sync	100.00			100.00
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
u_sync_2	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
u_combined_rstn_sync	90.91			90.91
u_prim_cdc_rand_delay	100.00			100.00
u_sync_1	75.00			75.00
gen_generic.u_impl_generic	75.00			75.00
u_sync_2	100.00			100.00
gen_generic.u_impl_generic	100.00			100.00
u_rst_mux	75.00			75.00
gen_generic.u_impl_generic	75.00			75.00
i_dmi_jtag_tap	80.65			80.65
i_tck_inv	71.43			71.43
gen_generic.u_impl_generic	72.73			72.73
gen_scan.i_dft_tck_mux	75.00			75.00
gen_generic.u_impl_generic	75.00			75.00
u_lc_ctrl_fsm	97.07	99.39	90.62		100.00	97.67	97.67
subtree...
u_lc_ctrl_kmac_if	99.37	99.10	100.00		100.00	97.73	100.00
u_prim_flop_2sync	100.00	100.00				100.00
u_sync_1	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_prim_sync_reqack_data_in	98.41	98.18	100.00			95.45	100.00
u_prim_sync_reqack	98.16	97.92	100.00			94.74	100.00
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
u_sync_1	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00
u_sync_1	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_state_regs	100.00	100.00				100.00	100.00
u_state_flop	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_prim_clock_mux2	85.19	100.00	55.56				100.00
gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
u_prim_esc_receiver0	16.07			16.07
u_prim_count	4.08			4.08
u_prim_esc_receiver1	16.07			16.07
u_prim_count	4.08			4.08
u_prim_flop_2sync_init	100.00	100.00				100.00
u_sync_1	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_sync_2	100.00	100.00				100.00
gen_generic.u_impl_generic	100.00	100.00				100.00
u_prim_lc_sync	100.00	100.00					100.00
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
u_secure_anchor_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
u_prim_mubi4_dec	0.00	0.00
gen_bits[0].u_prim_buf	0.00	0.00
gen_generic.u_impl_generic	0.00	0.00
gen_bits[1].u_prim_buf	0.00	0.00
gen_generic.u_impl_generic	0.00	0.00
gen_bits[2].u_prim_buf	0.00	0.00
gen_generic.u_impl_generic	0.00	0.00
gen_bits[3].u_prim_buf	0.00	0.00
gen_generic.u_impl_generic	0.00	0.00
u_prim_rst_n_mux2	85.19	100.00	55.56				100.00
gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
u_reg	99.33	97.79	98.85	100.00		100.00	100.00
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_chk	100.00			100.00
u_tlul_data_integ_dec	100.00	100.00		100.00
u_data_chk	100.00			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	66.67	66.67
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_prim_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
u_prim_onehot_check	100.00			100.00
u_reg_if	98.97	97.14	98.75			100.00	100.00
u_err	100.00	100.00	100.00			100.00	100.00
u_rsp_intg_gen	83.33	66.67					100.00
u_rsp_intg_gen	100.00	100.00					100.00
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
u_data_gen	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00
u_reg_tap	93.82	96.95	98.54	73.61		100.00	100.00
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_prog_error	100.00	100.00
u_alert_test_fatal_state_error	100.00	100.00
u_chk	90.18	100.00		70.54			100.00
u_chk	34.48			34.48
u_tlul_data_integ_dec	100.00	100.00		100.00
u_data_chk	100.00			100.00
u_claim_transition_if	100.00	100.00
u_claim_transition_if_regwen	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00
u_device_id_0	100.00	100.00
u_device_id_1	100.00	100.00
u_device_id_2	100.00	100.00
u_device_id_3	100.00	100.00
u_device_id_4	100.00	100.00
u_device_id_5	100.00	100.00
u_device_id_6	100.00	100.00
u_device_id_7	100.00	100.00
u_hw_revision0_product_id	33.33	33.33
u_hw_revision0_silicon_creator_id	33.33	33.33
u_hw_revision1_reserved	33.33	33.33
u_hw_revision1_revision_id	33.33	33.33
u_lc_id_state	66.67	66.67
u_lc_state	100.00	100.00
u_lc_transition_cnt	100.00	100.00
u_manuf_state_0	100.00	100.00
u_manuf_state_1	100.00	100.00
u_manuf_state_2	100.00	100.00
u_manuf_state_3	100.00	100.00
u_manuf_state_4	100.00	100.00
u_manuf_state_5	100.00	100.00
u_manuf_state_6	100.00	100.00
u_manuf_state_7	100.00	100.00
u_otp_vendor_test_ctrl	100.00	100.00
u_otp_vendor_test_status	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_prim_buf	100.00	100.00
gen_generic.u_impl_generic	100.00	100.00
u_prim_onehot_check	100.00			100.00
u_reg_if	97.14	92.19	96.36			100.00	100.00
u_err	97.50	90.00	100.00			100.00	100.00
u_rsp_intg_gen	83.33	66.67					100.00
u_rsp_intg_gen	100.00	100.00					100.00
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
u_data_gen	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_ext_clock_switched	100.00	100.00
u_status_flash_rma_error	100.00	100.00
u_status_initialized	100.00	100.00
u_status_otp_error	100.00	100.00
u_status_otp_partition_error	100.00	100.00
u_status_ready	100.00	100.00
u_status_state_error	100.00	100.00
u_status_token_error	100.00	100.00
u_status_transition_count_error	100.00	100.00
u_status_transition_error	100.00	100.00
u_status_transition_successful	100.00	100.00
u_transition_cmd	100.00	100.00
u_transition_ctrl_ext_clock_en	100.00	100.00
u_transition_ctrl_volatile_raw_unlock	100.00	100.00
u_transition_regwen	100.00	100.00
u_transition_target	100.00	100.00
u_transition_token_0	100.00	100.00
u_transition_token_1	100.00	100.00
u_transition_token_2	100.00	100.00
u_transition_token_3	100.00	100.00
u_tap_tlul_host	81.19	98.00	92.86	15.09		100.00	100.00
u_cmd_intg_gen	100.00	100.00					100.00
gen_data_intg.u_data_gen	100.00	100.00
u_cmd_gen	100.00	100.00
u_rsp_chk	78.77	100.00	100.00	15.09			100.00
u_chk	15.09			15.09