Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00
tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00


Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 5 5 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
oh_i[0] Yes Yes *T2,*T98,*T99 Yes T2,T98,T99 INPUT
oh_i[1] Unreachable Unreachable Unreachable INPUT
oh_i[3:2] Yes Yes *T32,*T60,*T97 Yes T32,T60,T97 INPUT
oh_i[4] Unreachable Unreachable Unreachable INPUT
oh_i[12:5] Yes Yes T1,T4,T6 Yes T1,T4,T6 INPUT
oh_i[34:13] Unreachable Unreachable Unreachable INPUT
addr_i[5:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o Yes Yes T32,T60,T97 Yes T32,T60,T97 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 5 5 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
oh_i[0] Yes Yes *T2,*T98,*T99 Yes T2,T98,T99 INPUT
oh_i[1] Unreachable Unreachable Unreachable INPUT
oh_i[3:2] Yes Yes *T32,*T60,*T120 Yes T32,T60,T120 INPUT
oh_i[4] Unreachable Unreachable Unreachable INPUT
oh_i[12:5] Yes Yes T1,T4,*T6 Yes T1,T4,T6 INPUT
oh_i[34:13] Unreachable Unreachable Unreachable INPUT
addr_i[5:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
err_o Yes Yes T32,T60,T97 Yes T32,T60,T97 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 30 30 100.00
Total Bits 0->1 15 15 100.00
Total Bits 1->0 15 15 100.00

Ports 5 5 100.00
Port Bits 30 30 100.00
Port Bits 0->1 15 15 100.00
Port Bits 1->0 15 15 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
oh_i[0] Yes Yes *T32,*T60,*T97 Yes T32,T60,T97 INPUT
oh_i[1] Unreachable Unreachable Unreachable INPUT
oh_i[3:2] Yes Yes *T32,*T60,*T97 Yes T32,T60,T97 INPUT
oh_i[4] Unreachable Unreachable Unreachable INPUT
oh_i[12:5] Yes Yes T6,T14,*T15 Yes T6,T14,T15 INPUT
oh_i[34:13] Unreachable Unreachable Unreachable INPUT
addr_i[5:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T3,T5,T6 Yes T3,T5,T6 INPUT
err_o Yes Yes T32,T60,T97 Yes T32,T60,T97 OUTPUT

*Tests covering at least one bit in the range