Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3535480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3983449

1

T1

111

T2

7

T3

485

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6823512	1			T1	113		T3	267		T4	585
values[0x0]	347262	1			T1	50		T2	9		T3	193
values[0x1]	348155	1			T1	47		T2	15		T3	215

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2809634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4709295

1

T1

132

T2

8

T3

532

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22084	1			T4	2		T5	7		T13	7
valid_sources[0x01]	22145	1			T4	3		T5	8		T13	8
valid_sources[0x02]	22166	1			T1	2		T4	2		T5	10
valid_sources[0x03]	30062	1			T4	8		T11	1		T5	1
valid_sources[0x04]	24014	1			T2	1		T4	3		T5	2
valid_sources[0x05]	24474	1			T4	3		T5	7		T15	4
valid_sources[0x06]	23136	1			T4	6		T5	4		T13	3
valid_sources[0x07]	21991	1			T4	3		T5	6		T15	4
valid_sources[0x08]	22228	1			T4	8		T5	3		T13	7
valid_sources[0x09]	23898	1			T4	5		T5	9		T14	5
valid_sources[0x0a]	21523	1			T4	4		T5	5		T13	8
valid_sources[0x0b]	22759	1			T4	5		T5	5		T13	5
valid_sources[0x0c]	22568	1			T1	5		T4	4		T5	7
valid_sources[0x0d]	21751	1			T1	8		T4	3		T5	5
valid_sources[0x0e]	22579	1			T2	1		T4	1		T5	6
valid_sources[0x0f]	25190	1			T4	5		T11	1		T5	8
valid_sources[0x10]	24947	1			T4	3		T5	7		T13	3
valid_sources[0x11]	29528	1			T4	4		T5	2		T15	2
valid_sources[0x12]	45992	1			T1	7		T4	7		T5	2
valid_sources[0x13]	22732	1			T4	1		T11	1		T5	7
valid_sources[0x14]	22693	1			T4	2		T5	2		T13	2
valid_sources[0x15]	21839	1			T1	3		T4	8		T11	1
valid_sources[0x16]	23674	1			T4	2		T5	5		T13	1
valid_sources[0x17]	69086	1			T4	2		T11	1		T5	5
valid_sources[0x18]	27979	1			T4	6		T5	3		T13	2
valid_sources[0x19]	58543	1			T4	4		T5	2		T13	6
valid_sources[0x1a]	22820	1			T4	1		T5	2		T13	1
valid_sources[0x1b]	22214	1			T4	2		T5	2		T13	4
valid_sources[0x1c]	41591	1			T1	1		T4	3		T5	5
valid_sources[0x1d]	22860	1			T4	1		T5	4		T14	1
valid_sources[0x1e]	25557	1			T4	1		T13	3		T20	1
valid_sources[0x1f]	22453	1			T1	3		T4	5		T5	2
valid_sources[0x20]	28959	1			T4	4		T13	5		T7	64
valid_sources[0x21]	23287	1			T1	15		T4	8		T5	5
valid_sources[0x22]	22724	1			T1	5		T4	3		T5	4
valid_sources[0x23]	22227	1			T2	1		T4	2		T5	4
valid_sources[0x24]	22876	1			T4	11		T5	2		T7	98
valid_sources[0x25]	26003	1			T4	3		T5	6		T15	1
valid_sources[0x26]	27500	1			T4	3		T11	1		T5	5
valid_sources[0x27]	23306	1			T4	3		T5	1		T13	1
valid_sources[0x28]	29013	1			T4	5		T5	6		T13	1
valid_sources[0x29]	23997	1			T4	5		T5	5		T20	4
valid_sources[0x2a]	30082	1			T4	5		T5	7		T13	2
valid_sources[0x2b]	23120	1			T1	5		T4	1		T5	2
valid_sources[0x2c]	36162	1			T4	4		T5	6		T15	7
valid_sources[0x2d]	70979	1			T4	4		T5	5		T27	1079
valid_sources[0x2e]	24212	1			T1	2		T4	6		T5	1
valid_sources[0x2f]	23674	1			T4	5		T5	8		T20	1
valid_sources[0x30]	22737	1			T4	9		T5	4		T7	74
valid_sources[0x31]	22440	1			T4	7		T5	7		T13	5
valid_sources[0x32]	22167	1			T5	6		T20	1		T7	87
valid_sources[0x33]	22222	1			T4	1		T5	4		T20	3
valid_sources[0x34]	30064	1			T4	5		T5	4		T14	7
valid_sources[0x35]	22946	1			T4	2		T5	4		T13	3
valid_sources[0x36]	22716	1			T1	2		T4	4		T5	2
valid_sources[0x37]	22428	1			T1	2		T4	6		T5	7
valid_sources[0x38]	25635	1			T4	3		T5	4		T13	3
valid_sources[0x39]	23243	1			T4	2		T5	4		T13	2
valid_sources[0x3a]	22163	1			T4	9		T5	5		T13	3
valid_sources[0x3b]	24190	1			T4	6		T5	5		T15	2
valid_sources[0x3c]	22265	1			T4	4		T5	2		T13	3
valid_sources[0x3d]	25142	1			T2	1		T4	6		T5	4
valid_sources[0x3e]	23909	1			T1	2		T4	4		T5	1
valid_sources[0x3f]	23354	1			T4	2		T5	9		T20	1
valid_sources[0x40]	26002	1			T4	3		T20	1		T7	98
valid_sources[0x41]	24755	1			T4	4		T5	3		T15	4
valid_sources[0x42]	22813	1			T1	3		T4	5		T11	2
valid_sources[0x43]	23066	1			T4	4		T5	4		T15	10
valid_sources[0x44]	26505	1			T4	7		T5	2		T13	1
valid_sources[0x45]	23506	1			T4	5		T5	7		T13	1
valid_sources[0x46]	23044	1			T4	3		T5	6		T13	1
valid_sources[0x47]	22666	1			T4	3		T5	4		T15	7
valid_sources[0x48]	22328	1			T4	5		T5	1		T13	2
valid_sources[0x49]	25080	1			T4	1		T5	6		T13	3
valid_sources[0x4a]	43071	1			T4	3		T5	7		T13	5
valid_sources[0x4b]	22219	1			T4	7		T13	3		T15	2
valid_sources[0x4c]	27228	1			T2	1		T4	6		T5	3
valid_sources[0x4d]	22119	1			T4	4		T11	1		T5	5
valid_sources[0x4e]	28415	1			T4	5		T5	3		T13	7
valid_sources[0x4f]	22293	1			T4	4		T5	3		T15	2
valid_sources[0x50]	55008	1			T4	7		T5	4		T13	1
valid_sources[0x51]	21994	1			T4	2		T5	7		T13	12
valid_sources[0x52]	22356	1			T4	3		T5	4		T13	7
valid_sources[0x53]	23993	1			T1	9		T4	7		T5	6
valid_sources[0x54]	29522	1			T1	8		T4	5		T5	4
valid_sources[0x55]	37502	1			T4	6		T5	3		T13	8
valid_sources[0x56]	25462	1			T4	5		T5	3		T15	6
valid_sources[0x57]	22187	1			T4	6		T5	4		T20	4
valid_sources[0x58]	40486	1			T4	9		T5	7		T15	2
valid_sources[0x59]	22790	1			T4	8		T5	3		T13	5
valid_sources[0x5a]	23807	1			T4	7		T5	5		T15	1
valid_sources[0x5b]	23146	1			T4	6		T5	3		T14	5
valid_sources[0x5c]	73957	1			T4	6		T5	2		T7	99
valid_sources[0x5d]	27934	1			T4	3		T5	5		T13	6
valid_sources[0x5e]	23961	1			T4	6		T5	5		T15	2
valid_sources[0x5f]	24122	1			T4	6		T5	2		T13	3
valid_sources[0x60]	24473	1			T2	1		T4	2		T5	5
valid_sources[0x61]	22119	1			T4	3		T5	6		T15	14
valid_sources[0x62]	24649	1			T4	5		T5	8		T13	7
valid_sources[0x63]	23184	1			T4	4		T5	8		T15	1
valid_sources[0x64]	22122	1			T4	2		T5	6		T13	7
valid_sources[0x65]	22770	1			T4	3		T5	1		T13	5
valid_sources[0x66]	21336	1			T4	5		T5	7		T15	3
valid_sources[0x67]	24751	1			T4	6		T5	8		T14	1
valid_sources[0x68]	25509	1			T2	1		T4	6		T5	6
valid_sources[0x69]	27655	1			T4	4		T5	2		T15	4
valid_sources[0x6a]	22180	1			T4	4		T5	5		T15	4
valid_sources[0x6b]	22656	1			T1	16		T2	1		T4	5
valid_sources[0x6c]	24828	1			T4	3		T5	6		T15	14
valid_sources[0x6d]	22790	1			T4	3		T5	3		T13	1
valid_sources[0x6e]	59790	1			T4	5		T5	11		T15	2
valid_sources[0x6f]	38626	1			T1	34		T4	3		T5	2
valid_sources[0x70]	25179	1			T1	11		T4	3		T5	12
valid_sources[0x71]	25948	1			T4	6		T5	1		T15	2
valid_sources[0x72]	22077	1			T1	2		T4	2		T5	7
valid_sources[0x73]	22701	1			T4	3		T5	5		T15	5
valid_sources[0x74]	22098	1			T4	4		T5	8		T13	2
valid_sources[0x75]	24434	1			T4	3		T5	10		T13	3
valid_sources[0x76]	27476	1			T4	2		T5	1		T13	8
valid_sources[0x77]	22271	1			T4	3		T5	2		T14	1
valid_sources[0x78]	23560	1			T4	2		T5	5		T13	4
valid_sources[0x79]	293548	1			T4	3		T11	1		T5	1
valid_sources[0x7a]	26972	1			T1	2		T4	5		T11	1
valid_sources[0x7b]	22153	1			T4	6		T5	2		T15	6
valid_sources[0x7c]	23168	1			T4	5		T5	5		T13	6
valid_sources[0x7d]	23868	1			T4	8		T5	3		T13	1
valid_sources[0x7e]	24119	1			T4	6		T5	4		T13	2
valid_sources[0x7f]	22721	1			T4	1		T5	4		T14	1
valid_sources[0x80]	22383	1			T4	5		T5	4		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3384061

1

T1

54

T3

125

T4

229

values[0x0]

all_enables

biggest_size

301036

1

T1

33

T2

2

T3

174

values[0x1]

all_enables

biggest_size

298352

1

T1

24

T2

5

T3

186