Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
80.00	80.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex	80.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	2	8	80.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	2	8	80.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	2	8	80.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[6]	0	1	1
false	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	4986	1			T1	16		T8	14		T9	8
others[1]	2	1			T183	1		T248	1		-	-
others[2]	3	1			T249	1		T250	1		T251	1
others[3]	2	1			T252	1		T253	1		-	-
others[4]	3	1			T74	1		T101	1		T254	1
others[5]	3	1			T255	1		T256	1		T257	1
others[7]	1	1			T95	1		-	-		-	-
true	82270	1			T1	44		T3	51		T4	69