Line Coverage for Module :
prim_generic_flop
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Toggle Coverage for Module :
prim_generic_flop
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T2,T3 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Branch Coverage for Module :
prim_generic_flop
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.u_sync_1.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
8 |
6 |
75.00 |
Total Bits 0->1 |
4 |
3 |
75.00 |
Total Bits 1->0 |
4 |
3 |
75.00 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
8 |
6 |
75.00 |
Port Bits 0->1 |
4 |
3 |
75.00 |
Port Bits 1->0 |
4 |
3 |
75.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
d_i |
No |
No |
|
No |
|
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.u_sync_2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T4,T5 |
Yes |
T1,T2,T3 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T4,T5 |
Yes |
T1,T2,T3 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T4,T5 |
Yes |
T1,T2,T3 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Totals |
4 |
4 |
100.00 |
Total Bits |
8 |
8 |
100.00 |
Total Bits 0->1 |
4 |
4 |
100.00 |
Total Bits 1->0 |
4 |
4 |
100.00 |
| | | |
Ports |
4 |
4 |
100.00 |
Port Bits |
8 |
8 |
100.00 |
Port Bits 0->1 |
4 |
4 |
100.00 |
Port Bits 1->0 |
4 |
4 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T3,T4,T5 |
Yes |
T1,T2,T3 |
INPUT |
d_i |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
INPUT |
q_o |
Yes |
Yes |
T1,T6,T7 |
Yes |
T1,T6,T7 |
OUTPUT |
Line Coverage for Instance : tb.dut.u_prim_flop_2sync_init.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_flop_2sync_init.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_prim_flop_2sync_init.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_prim_flop_2sync_init.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_state_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_kmac_if.u_state_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_fsm_state_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_cnt_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_cnt_regs.u_state_flop.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_flop_keymgr_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
18 |
1 |
1 |
19 |
1 |
1 |
21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_flop_keymgr_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |