Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215645562	30299	0	0
claim_transition_if_regwen_rd_A	215645562	2569	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215645562	30299	0	0
T19	132866	0	0	0
T41	340213	13	0	0
T47	44046	0	0	0
T57	0	9	0	0
T62	23403	0	0	0
T100	0	4	0	0
T124	0	2	0	0
T125	0	3	0	0
T127	0	8	0	0
T179	0	5	0	0
T180	0	19	0	0
T181	0	3	0	0
T182	0	1	0	0
T183	1236	0	0	0
T184	121279	0	0	0
T185	16617	0	0	0
T186	11352	0	0	0
T187	141317	0	0	0
T188	81540	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215645562	2569	0	0
T16	226521	5	0	0
T17	26716	0	0	0
T23	111509	0	0	0
T28	19855	0	0	0
T39	39696	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T49	29469	0	0	0
T58	44980	0	0	0
T89	0	8	0	0
T129	0	2	0	0
T135	0	2	0	0
T189	0	7	0	0
T190	0	9	0	0
T191	0	19	0	0
T192	0	11	0	0
T193	1537	0	0	0
T194	1030	0	0	0
T195	64365	0	0	0