Unified Coverage Report :: Module :: tlul_adapter_host

Module : tlul_adapter_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.51	91.30	68.75			90.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host	96.78	95.45	91.67			100.00	100.00

---

Module Instance : tb.dut.u_tap_tlul_host

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.78	95.45	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.19	98.00	92.86	15.09		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	100.00	100.00					100.00
u_rsp_chk	78.77	100.00	100.00	15.09			100.00

Line Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
TOTAL		23	21	91.30
ALWAYS	69	3	3	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	4	3	75.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
72	1	1
77	1	1
79	1	1
80	1	1
81	1	1
83	1	1
			MISSING_ELSE
88	1	1
93	1	1
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134	0	1
			MISSING_ELSE
140	1	1
144	1	1
148	0	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

---

Cond Coverage for Module : tlul_adapter_host

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T6,T7

 LINE       80
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T6,T7

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	93	2	2	100.00
IF	131	3	2	66.67
IF	69	2	2	100.00
IF	79	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	93	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	if ((req_i && gnt_o))
-2-:	80	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_host

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	211857976	804390	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	211857976	804390	0	0
T1	15956	166	0	0
T2	1235	0	0	0
T3	18888	0	0	0
T4	29105	0	0	0
T5	27540	0	0	0
T6	0	138	0	0
T7	0	1669	0	0
T8	0	148	0	0
T11	1132	0	0	0
T12	43800	0	0	0
T13	11018	0	0	0
T14	1359	0	0	0
T15	16797	0	0	0
T16	0	8202	0	0
T23	0	4400	0	0
T28	0	127	0	0
T29	0	579	0	0
T30	0	2485	0	0
T31	0	296	0	0

Line Coverage for Instance : tb.dut.u_tap_tlul_host

	Line No.	Total	Covered	Percent
TOTAL		22	21	95.45
ALWAYS	69	3	3	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	3	3	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
72	1	1
77	1	1
79	1	1
80	1	1
81	1	1
83	1	1
			MISSING_ELSE
88	1	1
93	1	1
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
140	1	1
144	1	1
148	0	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

---

Cond Coverage for Instance : tb.dut.u_tap_tlul_host

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T6,T7

 LINE       80
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T6,T7

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T6,T7

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Not Covered

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

---

Branch Coverage for Instance : tb.dut.u_tap_tlul_host

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	93	2	2	100.00
IF	131	2	2	100.00
IF	69	2	2	100.00
IF	79	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	93	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	if ((req_i && gnt_o))
-2-:	80	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tap_tlul_host

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	211857976	804390	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	211857976	804390	0	0
T1	15956	166	0	0
T2	1235	0	0	0
T3	18888	0	0	0
T4	29105	0	0	0
T5	27540	0	0	0
T6	0	138	0	0
T7	0	1669	0	0
T8	0	148	0	0
T11	1132	0	0	0
T12	43800	0	0	0
T13	11018	0	0	0
T14	1359	0	0	0
T15	16797	0	0	0
T16	0	8202	0	0
T23	0	4400	0	0
T28	0	127	0	0
T29	0	579	0	0
T30	0	2485	0	0
T31	0	296	0	0