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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.99 97.82 96.30 95.74 95.35 98.10 99.00 96.61


Total test records in report: 2003
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T1775 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4091874993 Mar 07 01:06:53 PM PST 24 Mar 07 01:06:56 PM PST 24 116550444 ps
T228 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2842755165 Mar 07 01:16:54 PM PST 24 Mar 07 01:16:55 PM PST 24 42923159 ps
T157 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3964009000 Mar 07 01:17:28 PM PST 24 Mar 07 01:17:33 PM PST 24 119025635 ps
T1776 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1832420551 Mar 07 01:07:41 PM PST 24 Mar 07 01:07:44 PM PST 24 176637205 ps
T1777 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3529470778 Mar 07 01:17:06 PM PST 24 Mar 07 01:17:08 PM PST 24 14580431 ps
T1778 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.540767915 Mar 07 01:08:01 PM PST 24 Mar 07 01:08:05 PM PST 24 665219533 ps
T1779 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2958253721 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:37 PM PST 24 162955521 ps
T1780 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3265210984 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:38 PM PST 24 75948053 ps
T1781 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.922162407 Mar 07 01:17:38 PM PST 24 Mar 07 01:17:41 PM PST 24 100955040 ps
T229 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.348053688 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:16 PM PST 24 138155895 ps
T1782 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1109579136 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:33 PM PST 24 678148267 ps
T1783 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4069944443 Mar 07 01:08:17 PM PST 24 Mar 07 01:08:19 PM PST 24 20093138 ps
T1784 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2079164579 Mar 07 01:16:52 PM PST 24 Mar 07 01:16:55 PM PST 24 88620846 ps
T1785 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.329206124 Mar 07 01:07:13 PM PST 24 Mar 07 01:07:14 PM PST 24 48536443 ps
T1786 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.690054290 Mar 07 01:07:42 PM PST 24 Mar 07 01:07:43 PM PST 24 361790585 ps
T1787 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.787934452 Mar 07 01:16:54 PM PST 24 Mar 07 01:16:55 PM PST 24 16395020 ps
T1788 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1325557216 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:39 PM PST 24 236924692 ps
T1789 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1385659247 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:17 PM PST 24 215094116 ps
T1790 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.992056623 Mar 07 01:07:03 PM PST 24 Mar 07 01:07:09 PM PST 24 1094432117 ps
T1791 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.454622810 Mar 07 01:06:45 PM PST 24 Mar 07 01:06:47 PM PST 24 42673246 ps
T1792 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.764286796 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:38 PM PST 24 27573627 ps
T1793 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1555773790 Mar 07 01:08:29 PM PST 24 Mar 07 01:08:31 PM PST 24 27510060 ps
T1794 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.931608753 Mar 07 01:16:51 PM PST 24 Mar 07 01:16:52 PM PST 24 68267254 ps
T230 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1546148349 Mar 07 01:17:00 PM PST 24 Mar 07 01:17:02 PM PST 24 34627959 ps
T1795 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1761049332 Mar 07 01:17:02 PM PST 24 Mar 07 01:17:04 PM PST 24 47906674 ps
T1796 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.154803007 Mar 07 01:08:17 PM PST 24 Mar 07 01:08:20 PM PST 24 475769083 ps
T1797 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1849108790 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:38 PM PST 24 142079556 ps
T158 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3414198215 Mar 07 01:17:16 PM PST 24 Mar 07 01:17:20 PM PST 24 117915406 ps
T1798 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4002725673 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:27 PM PST 24 108919110 ps
T1799 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2115799450 Mar 07 01:06:53 PM PST 24 Mar 07 01:07:02 PM PST 24 844869685 ps
T1800 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2502877089 Mar 07 01:17:02 PM PST 24 Mar 07 01:17:25 PM PST 24 944282720 ps
T1801 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3697850920 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:19 PM PST 24 324232973 ps
T1802 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1806011667 Mar 07 01:17:16 PM PST 24 Mar 07 01:17:19 PM PST 24 638346313 ps
T1803 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.401883349 Mar 07 01:07:56 PM PST 24 Mar 07 01:07:58 PM PST 24 112791205 ps
T1804 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.928422152 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:18 PM PST 24 81203327 ps
T1805 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2240993614 Mar 07 01:06:51 PM PST 24 Mar 07 01:06:52 PM PST 24 16308363 ps
T1806 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2409025663 Mar 07 01:07:35 PM PST 24 Mar 07 01:07:37 PM PST 24 54354228 ps
T1807 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.503384973 Mar 07 01:08:14 PM PST 24 Mar 07 01:08:16 PM PST 24 93894079 ps
T1808 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4228500129 Mar 07 01:07:59 PM PST 24 Mar 07 01:08:03 PM PST 24 189015628 ps
T1809 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1912997081 Mar 07 01:16:36 PM PST 24 Mar 07 01:16:37 PM PST 24 119144620 ps
T1810 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1817512790 Mar 07 01:07:04 PM PST 24 Mar 07 01:07:07 PM PST 24 83331957 ps
T1811 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.857937682 Mar 07 01:16:51 PM PST 24 Mar 07 01:17:04 PM PST 24 2078411307 ps
T1812 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3725021245 Mar 07 01:08:18 PM PST 24 Mar 07 01:08:19 PM PST 24 31296619 ps
T173 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1187582643 Mar 07 01:08:30 PM PST 24 Mar 07 01:08:33 PM PST 24 42931094 ps
T1813 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3271095267 Mar 07 01:17:06 PM PST 24 Mar 07 01:17:09 PM PST 24 828273652 ps
T1814 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.607655170 Mar 07 01:16:54 PM PST 24 Mar 07 01:16:56 PM PST 24 110286848 ps
T1815 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.615919810 Mar 07 01:08:15 PM PST 24 Mar 07 01:08:16 PM PST 24 21717672 ps
T1816 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.722185847 Mar 07 01:07:42 PM PST 24 Mar 07 01:07:43 PM PST 24 57611421 ps
T1817 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.27235642 Mar 07 01:16:54 PM PST 24 Mar 07 01:17:08 PM PST 24 2167205303 ps
T150 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3915085741 Mar 07 01:17:02 PM PST 24 Mar 07 01:17:05 PM PST 24 563672296 ps
T1818 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2225865407 Mar 07 01:07:41 PM PST 24 Mar 07 01:08:01 PM PST 24 1483150763 ps
T1819 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2821651198 Mar 07 01:17:03 PM PST 24 Mar 07 01:17:05 PM PST 24 116179555 ps
T1820 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1353020158 Mar 07 01:07:03 PM PST 24 Mar 07 01:07:05 PM PST 24 77921447 ps
T1821 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2459655596 Mar 07 01:06:52 PM PST 24 Mar 07 01:06:56 PM PST 24 860968710 ps
T1822 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2392327354 Mar 07 01:17:42 PM PST 24 Mar 07 01:17:43 PM PST 24 59618425 ps
T1823 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2169229811 Mar 07 01:07:41 PM PST 24 Mar 07 01:07:43 PM PST 24 259754970 ps
T237 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3641995504 Mar 07 01:08:01 PM PST 24 Mar 07 01:08:03 PM PST 24 13431179 ps
T235 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1872138013 Mar 07 01:07:54 PM PST 24 Mar 07 01:07:55 PM PST 24 43929027 ps
T1824 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3770678483 Mar 07 01:17:46 PM PST 24 Mar 07 01:17:50 PM PST 24 494196771 ps
T1825 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1204742230 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:28 PM PST 24 628008235 ps
T1826 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4218401631 Mar 07 01:17:50 PM PST 24 Mar 07 01:17:52 PM PST 24 31622042 ps
T1827 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2443305452 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:37 PM PST 24 97257553 ps
T231 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3552747913 Mar 07 01:07:05 PM PST 24 Mar 07 01:07:06 PM PST 24 51011931 ps
T1828 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3173978058 Mar 07 01:07:30 PM PST 24 Mar 07 01:07:35 PM PST 24 329223395 ps
T1829 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.712947224 Mar 07 01:16:51 PM PST 24 Mar 07 01:16:54 PM PST 24 73876920 ps
T1830 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1237445910 Mar 07 01:07:56 PM PST 24 Mar 07 01:07:59 PM PST 24 207647551 ps
T1831 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2090056976 Mar 07 01:17:40 PM PST 24 Mar 07 01:17:41 PM PST 24 82264703 ps
T1832 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2128176741 Mar 07 01:17:03 PM PST 24 Mar 07 01:17:08 PM PST 24 346487136 ps
T1833 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.24896518 Mar 07 01:08:16 PM PST 24 Mar 07 01:08:19 PM PST 24 64402715 ps
T1834 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.4170421928 Mar 07 01:06:53 PM PST 24 Mar 07 01:06:55 PM PST 24 55149128 ps
T1835 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.557222967 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:17 PM PST 24 257525195 ps
T1836 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.232700407 Mar 07 01:07:28 PM PST 24 Mar 07 01:07:31 PM PST 24 42964654 ps
T1837 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2458574135 Mar 07 01:06:39 PM PST 24 Mar 07 01:06:40 PM PST 24 86678461 ps
T1838 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3397631898 Mar 07 01:17:08 PM PST 24 Mar 07 01:17:14 PM PST 24 1733595895 ps
T1839 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2078741761 Mar 07 01:07:59 PM PST 24 Mar 07 01:08:00 PM PST 24 83083074 ps
T236 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3120279517 Mar 07 01:17:56 PM PST 24 Mar 07 01:17:57 PM PST 24 52785986 ps
T1840 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2875379480 Mar 07 01:08:00 PM PST 24 Mar 07 01:08:01 PM PST 24 29464912 ps
T1841 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3981286832 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:36 PM PST 24 27043454 ps
T1842 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3767000872 Mar 07 01:06:51 PM PST 24 Mar 07 01:07:03 PM PST 24 1901365250 ps
T1843 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.290833009 Mar 07 01:08:16 PM PST 24 Mar 07 01:08:18 PM PST 24 104059886 ps
T1844 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3549821545 Mar 07 01:16:55 PM PST 24 Mar 07 01:17:06 PM PST 24 944046100 ps
T1845 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1511192593 Mar 07 01:07:41 PM PST 24 Mar 07 01:07:45 PM PST 24 258604521 ps
T1846 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1061506279 Mar 07 01:07:16 PM PST 24 Mar 07 01:07:23 PM PST 24 1827955233 ps
T1847 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.60480922 Mar 07 01:07:19 PM PST 24 Mar 07 01:07:21 PM PST 24 349585763 ps
T1848 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1447548426 Mar 07 01:07:27 PM PST 24 Mar 07 01:07:30 PM PST 24 37858078 ps
T1849 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.427652503 Mar 07 01:08:16 PM PST 24 Mar 07 01:08:20 PM PST 24 95804859 ps
T1850 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2875105589 Mar 07 01:16:52 PM PST 24 Mar 07 01:16:54 PM PST 24 183594543 ps
T1851 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.658222136 Mar 07 01:16:50 PM PST 24 Mar 07 01:16:52 PM PST 24 25357736 ps
T1852 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4008326131 Mar 07 01:07:13 PM PST 24 Mar 07 01:07:15 PM PST 24 18577877 ps
T1853 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3550525050 Mar 07 01:16:57 PM PST 24 Mar 07 01:17:00 PM PST 24 290509593 ps
T1854 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2007879311 Mar 07 01:07:30 PM PST 24 Mar 07 01:07:32 PM PST 24 53895861 ps
T1855 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3883959298 Mar 07 01:17:17 PM PST 24 Mar 07 01:17:19 PM PST 24 59046513 ps
T1856 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1331466327 Mar 07 01:16:57 PM PST 24 Mar 07 01:16:59 PM PST 24 18969304 ps
T1857 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2325524862 Mar 07 01:08:16 PM PST 24 Mar 07 01:08:17 PM PST 24 38253977 ps
T1858 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2862237456 Mar 07 01:16:52 PM PST 24 Mar 07 01:16:53 PM PST 24 17656373 ps
T1859 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3526281892 Mar 07 01:16:39 PM PST 24 Mar 07 01:16:40 PM PST 24 54758269 ps
T1860 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2353076708 Mar 07 01:17:49 PM PST 24 Mar 07 01:17:51 PM PST 24 28990091 ps
T1861 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1312071888 Mar 07 01:07:03 PM PST 24 Mar 07 01:07:04 PM PST 24 74411733 ps
T1862 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3346720892 Mar 07 01:08:17 PM PST 24 Mar 07 01:08:19 PM PST 24 18407613 ps
T148 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3312478733 Mar 07 01:17:39 PM PST 24 Mar 07 01:17:42 PM PST 24 107026572 ps
T1863 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4092494058 Mar 07 01:17:03 PM PST 24 Mar 07 01:17:04 PM PST 24 28305919 ps
T1864 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2950377694 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:40 PM PST 24 224706062 ps
T232 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2006209098 Mar 07 01:17:24 PM PST 24 Mar 07 01:17:26 PM PST 24 91706101 ps
T1865 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1842735229 Mar 07 01:07:58 PM PST 24 Mar 07 01:07:59 PM PST 24 58224037 ps
T170 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1777279900 Mar 07 01:17:14 PM PST 24 Mar 07 01:17:18 PM PST 24 412312109 ps
T1866 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1972041006 Mar 07 01:08:18 PM PST 24 Mar 07 01:08:21 PM PST 24 97363151 ps
T1867 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2915475285 Mar 07 01:17:17 PM PST 24 Mar 07 01:17:19 PM PST 24 47463357 ps
T1868 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2340307082 Mar 07 01:07:27 PM PST 24 Mar 07 01:07:30 PM PST 24 251755702 ps
T1869 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3394792 Mar 07 01:16:35 PM PST 24 Mar 07 01:16:54 PM PST 24 4731107192 ps
T1870 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2252455501 Mar 07 01:07:05 PM PST 24 Mar 07 01:07:06 PM PST 24 250219808 ps
T1871 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3916674667 Mar 07 01:07:15 PM PST 24 Mar 07 01:07:18 PM PST 24 37911573 ps
T1872 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2560721316 Mar 07 01:17:37 PM PST 24 Mar 07 01:17:40 PM PST 24 290935180 ps
T1873 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3741806878 Mar 07 01:16:53 PM PST 24 Mar 07 01:16:55 PM PST 24 396678326 ps
T1874 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.439126696 Mar 07 01:06:42 PM PST 24 Mar 07 01:06:43 PM PST 24 15239055 ps
T1875 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.566615813 Mar 07 01:07:27 PM PST 24 Mar 07 01:07:30 PM PST 24 225714109 ps
T1876 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2728049879 Mar 07 01:07:44 PM PST 24 Mar 07 01:07:45 PM PST 24 51415199 ps
T1877 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2596848995 Mar 07 01:08:34 PM PST 24 Mar 07 01:08:36 PM PST 24 27714851 ps
T1878 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.164774439 Mar 07 01:16:35 PM PST 24 Mar 07 01:16:37 PM PST 24 44289055 ps
T1879 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2145237288 Mar 07 01:07:40 PM PST 24 Mar 07 01:07:42 PM PST 24 130084114 ps
T171 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3683302632 Mar 07 01:17:40 PM PST 24 Mar 07 01:17:42 PM PST 24 107729356 ps
T1880 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.964176081 Mar 07 01:16:54 PM PST 24 Mar 07 01:16:57 PM PST 24 67958008 ps
T1881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2519197776 Mar 07 01:07:14 PM PST 24 Mar 07 01:07:20 PM PST 24 299858095 ps
T1882 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2124202428 Mar 07 01:07:45 PM PST 24 Mar 07 01:07:46 PM PST 24 20322365 ps
T1883 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1913057279 Mar 07 01:07:46 PM PST 24 Mar 07 01:07:47 PM PST 24 51713090 ps
T163 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2679662494 Mar 07 01:17:09 PM PST 24 Mar 07 01:17:12 PM PST 24 647596712 ps
T1884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.189620462 Mar 07 01:07:42 PM PST 24 Mar 07 01:07:45 PM PST 24 212676560 ps
T1885 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1760418437 Mar 07 01:07:28 PM PST 24 Mar 07 01:07:30 PM PST 24 212684390 ps
T1886 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3816152374 Mar 07 01:07:42 PM PST 24 Mar 07 01:07:52 PM PST 24 4561196004 ps
T1887 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.195963899 Mar 07 01:07:55 PM PST 24 Mar 07 01:07:57 PM PST 24 67379260 ps
T1888 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4008512165 Mar 07 01:17:00 PM PST 24 Mar 07 01:17:01 PM PST 24 15672804 ps
T1889 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3793803769 Mar 07 01:17:48 PM PST 24 Mar 07 01:17:50 PM PST 24 160937917 ps
T1890 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1843109364 Mar 07 01:16:57 PM PST 24 Mar 07 01:16:59 PM PST 24 37205971 ps
T1891 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3168653544 Mar 07 01:07:05 PM PST 24 Mar 07 01:07:06 PM PST 24 16909044 ps
T1892 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2844047750 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:30 PM PST 24 102687115 ps
T1893 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1583525261 Mar 07 01:07:56 PM PST 24 Mar 07 01:08:00 PM PST 24 51806972 ps
T1894 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.613354957 Mar 07 01:06:39 PM PST 24 Mar 07 01:06:41 PM PST 24 118862757 ps
T233 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3323167134 Mar 07 01:16:38 PM PST 24 Mar 07 01:16:39 PM PST 24 59757873 ps
T1895 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3746113275 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:17 PM PST 24 54491420 ps
T1896 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1258342774 Mar 07 01:07:21 PM PST 24 Mar 07 01:07:22 PM PST 24 37719098 ps
T1897 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3131016437 Mar 07 01:08:14 PM PST 24 Mar 07 01:08:16 PM PST 24 68876254 ps
T1898 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1209789952 Mar 07 01:17:16 PM PST 24 Mar 07 01:17:19 PM PST 24 68958426 ps
T1899 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3119965347 Mar 07 01:06:44 PM PST 24 Mar 07 01:06:45 PM PST 24 41383808 ps
T1900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4113671689 Mar 07 01:07:05 PM PST 24 Mar 07 01:07:07 PM PST 24 40045175 ps
T1901 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2177159207 Mar 07 01:17:00 PM PST 24 Mar 07 01:17:01 PM PST 24 14570765 ps
T1902 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2763179248 Mar 07 01:17:06 PM PST 24 Mar 07 01:17:10 PM PST 24 80980211 ps
T1903 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3387134818 Mar 07 01:17:38 PM PST 24 Mar 07 01:17:39 PM PST 24 46941772 ps
T1904 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1685710476 Mar 07 01:16:38 PM PST 24 Mar 07 01:16:43 PM PST 24 430103481 ps
T1905 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3122554781 Mar 07 01:07:19 PM PST 24 Mar 07 01:07:21 PM PST 24 66604791 ps
T1906 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1849992846 Mar 07 01:07:57 PM PST 24 Mar 07 01:07:58 PM PST 24 322733997 ps
T1907 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.655449782 Mar 07 01:17:13 PM PST 24 Mar 07 01:17:17 PM PST 24 131341532 ps
T1908 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2318853438 Mar 07 01:07:04 PM PST 24 Mar 07 01:07:07 PM PST 24 105332277 ps
T1909 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2181742811 Mar 07 01:07:59 PM PST 24 Mar 07 01:08:02 PM PST 24 43148244 ps
T159 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3289018090 Mar 07 01:07:56 PM PST 24 Mar 07 01:07:59 PM PST 24 237303270 ps
T1910 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.112521114 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:31 PM PST 24 5227659162 ps
T1911 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.856478626 Mar 07 01:17:49 PM PST 24 Mar 07 01:17:51 PM PST 24 40515857 ps
T1912 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.511740131 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:18 PM PST 24 48792484 ps
T1913 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2949354306 Mar 07 01:06:42 PM PST 24 Mar 07 01:06:45 PM PST 24 332890380 ps
T1914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2493746703 Mar 07 01:07:42 PM PST 24 Mar 07 01:07:43 PM PST 24 152164621 ps
T1915 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3746823347 Mar 07 01:17:27 PM PST 24 Mar 07 01:17:28 PM PST 24 155959938 ps
T1916 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2929272960 Mar 07 01:17:34 PM PST 24 Mar 07 01:17:36 PM PST 24 216090468 ps
T1917 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.778407208 Mar 07 01:17:34 PM PST 24 Mar 07 01:17:36 PM PST 24 79773716 ps
T1918 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1882166630 Mar 07 01:07:57 PM PST 24 Mar 07 01:08:02 PM PST 24 1497476973 ps
T1919 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2475317865 Mar 07 01:07:28 PM PST 24 Mar 07 01:07:39 PM PST 24 676703454 ps
T1920 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.516264116 Mar 07 01:16:54 PM PST 24 Mar 07 01:16:55 PM PST 24 80999633 ps
T1921 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.4191226176 Mar 07 01:16:52 PM PST 24 Mar 07 01:16:55 PM PST 24 140529151 ps
T1922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3203903306 Mar 07 01:07:55 PM PST 24 Mar 07 01:08:00 PM PST 24 1601195328 ps
T1923 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2730429562 Mar 07 01:17:27 PM PST 24 Mar 07 01:17:56 PM PST 24 5478132727 ps
T1924 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3087395089 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:38 PM PST 24 21943223 ps
T1925 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4093346426 Mar 07 01:08:15 PM PST 24 Mar 07 01:08:16 PM PST 24 61238877 ps
T1926 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3718882676 Mar 07 01:07:44 PM PST 24 Mar 07 01:08:02 PM PST 24 1084682134 ps
T1927 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3742754514 Mar 07 01:06:52 PM PST 24 Mar 07 01:06:53 PM PST 24 20362000 ps
T1928 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1349217629 Mar 07 01:07:44 PM PST 24 Mar 07 01:07:45 PM PST 24 255694926 ps
T1929 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4229559854 Mar 07 01:17:51 PM PST 24 Mar 07 01:17:52 PM PST 24 12471927 ps
T1930 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4289587627 Mar 07 01:07:28 PM PST 24 Mar 07 01:07:31 PM PST 24 66292512 ps
T1931 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2109833968 Mar 07 01:08:14 PM PST 24 Mar 07 01:08:15 PM PST 24 18286157 ps
T1932 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3286461474 Mar 07 01:08:17 PM PST 24 Mar 07 01:08:19 PM PST 24 26304873 ps
T1933 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.223619849 Mar 07 01:17:24 PM PST 24 Mar 07 01:17:26 PM PST 24 244972974 ps
T1934 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.865251739 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:19 PM PST 24 113060342 ps
T149 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2068046209 Mar 07 01:08:16 PM PST 24 Mar 07 01:08:19 PM PST 24 275725754 ps
T1935 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2235356734 Mar 07 01:07:45 PM PST 24 Mar 07 01:07:48 PM PST 24 284447300 ps
T234 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3805507063 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:16 PM PST 24 15108985 ps
T161 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2340096524 Mar 07 01:07:05 PM PST 24 Mar 07 01:07:10 PM PST 24 119751797 ps
T1936 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3298603297 Mar 07 01:16:39 PM PST 24 Mar 07 01:16:41 PM PST 24 105329154 ps
T1937 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3615299743 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:17 PM PST 24 189477828 ps
T1938 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3996901343 Mar 07 01:07:16 PM PST 24 Mar 07 01:07:20 PM PST 24 141870029 ps
T1939 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2725643453 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:38 PM PST 24 64489648 ps
T1940 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.997267345 Mar 07 01:07:57 PM PST 24 Mar 07 01:07:59 PM PST 24 39746119 ps
T1941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2460225261 Mar 07 01:16:39 PM PST 24 Mar 07 01:16:40 PM PST 24 23868674 ps
T1942 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3372623977 Mar 07 01:08:22 PM PST 24 Mar 07 01:08:23 PM PST 24 15911091 ps
T1943 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.180509344 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:37 PM PST 24 15566389 ps
T1944 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2586537558 Mar 07 01:07:04 PM PST 24 Mar 07 01:07:07 PM PST 24 194256512 ps
T1945 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2955544998 Mar 07 01:08:16 PM PST 24 Mar 07 01:08:21 PM PST 24 418483370 ps
T162 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3729024411 Mar 07 01:07:43 PM PST 24 Mar 07 01:07:47 PM PST 24 492236617 ps
T1946 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2976519509 Mar 07 01:07:05 PM PST 24 Mar 07 01:07:07 PM PST 24 57916267 ps
T1947 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1321103024 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:17 PM PST 24 288649579 ps
T1948 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3256079400 Mar 07 01:17:42 PM PST 24 Mar 07 01:17:43 PM PST 24 18490109 ps
T1949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.266574753 Mar 07 01:07:42 PM PST 24 Mar 07 01:07:43 PM PST 24 747811587 ps
T1950 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3124633184 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:17 PM PST 24 168660222 ps
T1951 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2014237151 Mar 07 01:17:51 PM PST 24 Mar 07 01:17:54 PM PST 24 61325981 ps
T1952 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3250986625 Mar 07 01:17:51 PM PST 24 Mar 07 01:17:54 PM PST 24 83431592 ps
T1953 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2342936783 Mar 07 01:08:18 PM PST 24 Mar 07 01:08:19 PM PST 24 50146644 ps
T1954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.52937437 Mar 07 01:07:30 PM PST 24 Mar 07 01:07:32 PM PST 24 123779434 ps
T1955 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2344990561 Mar 07 01:07:45 PM PST 24 Mar 07 01:07:46 PM PST 24 48130945 ps
T1956 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4164022802 Mar 07 01:07:28 PM PST 24 Mar 07 01:07:32 PM PST 24 36878395 ps
T1957 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2341253685 Mar 07 01:08:31 PM PST 24 Mar 07 01:08:33 PM PST 24 21142472 ps
T1958 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4121856551 Mar 07 01:16:36 PM PST 24 Mar 07 01:16:50 PM PST 24 2213297667 ps
T1959 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2026077333 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:28 PM PST 24 338563696 ps
T1960 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.659807306 Mar 07 01:17:48 PM PST 24 Mar 07 01:17:50 PM PST 24 53491293 ps
T1961 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1885486137 Mar 07 01:17:23 PM PST 24 Mar 07 01:17:27 PM PST 24 414894121 ps
T1962 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1732440572 Mar 07 01:17:16 PM PST 24 Mar 07 01:17:17 PM PST 24 43928522 ps
T1963 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.944930184 Mar 07 01:08:00 PM PST 24 Mar 07 01:08:03 PM PST 24 59320608 ps
T1964 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3308091094 Mar 07 01:07:59 PM PST 24 Mar 07 01:08:00 PM PST 24 28989671 ps
T1965 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3278752579 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:38 PM PST 24 68072288 ps
T1966 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3415570576 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:38 PM PST 24 16518781 ps
T1967 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2881480844 Mar 07 01:17:02 PM PST 24 Mar 07 01:17:03 PM PST 24 87571853 ps
T1968 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.290806176 Mar 07 01:16:39 PM PST 24 Mar 07 01:16:41 PM PST 24 42667911 ps
T1969 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3613705111 Mar 07 01:06:42 PM PST 24 Mar 07 01:06:44 PM PST 24 29006987 ps
T1970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2592313910 Mar 07 01:17:14 PM PST 24 Mar 07 01:17:18 PM PST 24 222685217 ps
T1971 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3374664493 Mar 07 01:07:57 PM PST 24 Mar 07 01:07:59 PM PST 24 65766071 ps
T1972 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.829920573 Mar 07 01:17:15 PM PST 24 Mar 07 01:17:21 PM PST 24 1202202471 ps
T1973 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4116486341 Mar 07 01:06:42 PM PST 24 Mar 07 01:06:45 PM PST 24 323214320 ps
T1974 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2336342002 Mar 07 01:17:14 PM PST 24 Mar 07 01:17:16 PM PST 24 84179480 ps
T1975 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2271628446 Mar 07 01:07:44 PM PST 24 Mar 07 01:07:47 PM PST 24 614136434 ps
T1976 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1006156250 Mar 07 01:17:26 PM PST 24 Mar 07 01:17:27 PM PST 24 15166532 ps
T1977 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1169901901 Mar 07 01:16:45 PM PST 24 Mar 07 01:16:47 PM PST 24 75621522 ps
T1978 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2687644478 Mar 07 01:06:41 PM PST 24 Mar 07 01:06:44 PM PST 24 90172399 ps
T1979 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.811388578 Mar 07 01:07:57 PM PST 24 Mar 07 01:07:58 PM PST 24 29100702 ps
T1980 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2955610038 Mar 07 01:08:18 PM PST 24 Mar 07 01:08:20 PM PST 24 44070977 ps
T1981 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1643978046 Mar 07 01:08:28 PM PST 24 Mar 07 01:08:29 PM PST 24 34394362 ps
T1982 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4004047173 Mar 07 01:17:09 PM PST 24 Mar 07 01:17:12 PM PST 24 107023816 ps
T1983 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1445773391 Mar 07 01:07:15 PM PST 24 Mar 07 01:07:34 PM PST 24 1426980659 ps
T1984 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1325788503 Mar 07 01:08:01 PM PST 24 Mar 07 01:08:06 PM PST 24 174028588 ps
T1985 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2911591414 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:52 PM PST 24 644476223 ps
T156 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1027053388 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:28 PM PST 24 329031955 ps
T1986 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2681225027 Mar 07 01:17:25 PM PST 24 Mar 07 01:17:27 PM PST 24 27895229 ps
T1987 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1083406050 Mar 07 01:17:35 PM PST 24 Mar 07 01:17:36 PM PST 24 15609587 ps
T1988 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4180472294 Mar 07 01:17:38 PM PST 24 Mar 07 01:17:42 PM PST 24 199581557 ps
T166 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2512174758 Mar 07 01:07:15 PM PST 24 Mar 07 01:07:20 PM PST 24 756802579 ps
T1989 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3155590515 Mar 07 01:17:37 PM PST 24 Mar 07 01:17:38 PM PST 24 153399361 ps
T1990 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3717893301 Mar 07 01:17:36 PM PST 24 Mar 07 01:17:38 PM PST 24 30337183 ps
T1991 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3659990513 Mar 07 01:17:34 PM PST 24 Mar 07 01:17:36 PM PST 24 318179493 ps
T1992 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3100171215 Mar 07 01:16:53 PM PST 24 Mar 07 01:17:00 PM PST 24 574708307 ps
T1993 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1387497182 Mar 07 01:07:27 PM PST 24 Mar 07 01:07:30 PM PST 24 335816671 ps
T1994 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3150908592 Mar 07 01:17:01 PM PST 24 Mar 07 01:17:02 PM PST 24 42880173 ps
T1995 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2773369586 Mar 07 01:07:55 PM PST 24 Mar 07 01:07:57 PM PST 24 17970248 ps
T1996 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.251815802 Mar 07 01:16:52 PM PST 24 Mar 07 01:16:54 PM PST 24 136398290 ps
T1997 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3291996737 Mar 07 01:08:29 PM PST 24 Mar 07 01:08:31 PM PST 24 17015084 ps
T1998 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.776489515 Mar 07 01:07:20 PM PST 24 Mar 07 01:07:24 PM PST 24 117740084 ps
T1999 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.850786993 Mar 07 01:17:26 PM PST 24 Mar 07 01:17:28 PM PST 24 326376852 ps
T2000 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4134971804 Mar 07 01:07:44 PM PST 24 Mar 07 01:07:45 PM PST 24 361336113 ps
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