Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3274765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3672642

1

T1

212

T2

739

T3

30327

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6312451	1			T1	140		T2	710		T3	55510
values[0x0]	316605	1			T1	84		T2	213		T3	1669
values[0x1]	318351	1			T1	84		T2	227		T3	1715

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2600411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4346996

1

T1

242

T2

827

T3

36304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20297	1			T1	2		T3	218		T9	4
valid_sources[0x01]	113808	1			T3	221		T9	6		T10	7
valid_sources[0x02]	19384	1			T2	6		T3	182		T10	4
valid_sources[0x03]	20236	1			T3	179		T10	11		T13	7
valid_sources[0x04]	19075	1			T3	178		T10	4		T13	10
valid_sources[0x05]	20069	1			T3	198		T10	4		T14	9
valid_sources[0x06]	18855	1			T2	2		T3	277		T10	7
valid_sources[0x07]	22223	1			T2	8		T3	278		T10	1
valid_sources[0x08]	18785	1			T2	4		T3	195		T10	2
valid_sources[0x09]	21110	1			T1	15		T2	6		T3	194
valid_sources[0x0a]	20502	1			T1	10		T3	294		T10	8
valid_sources[0x0b]	18921	1			T2	3		T3	271		T10	5
valid_sources[0x0c]	18887	1			T2	4		T3	208		T10	5
valid_sources[0x0d]	19639	1			T3	309		T10	4		T13	9
valid_sources[0x0e]	20473	1			T1	16		T2	15		T3	240
valid_sources[0x0f]	28507	1			T3	230		T10	3		T13	4
valid_sources[0x10]	20484	1			T2	4		T3	260		T10	2
valid_sources[0x11]	19193	1			T3	254		T10	13		T13	5
valid_sources[0x12]	19690	1			T3	236		T10	4		T13	10
valid_sources[0x13]	20361	1			T2	19		T3	284		T10	8
valid_sources[0x14]	22028	1			T1	1		T2	2		T3	227
valid_sources[0x15]	66702	1			T3	217		T10	10		T13	2
valid_sources[0x16]	19455	1			T2	13		T3	230		T10	4
valid_sources[0x17]	40115	1			T2	3		T3	180		T10	3
valid_sources[0x18]	18968	1			T2	4		T3	287		T10	4
valid_sources[0x19]	31154	1			T2	11		T3	209		T10	4
valid_sources[0x1a]	22622	1			T3	197		T10	3		T14	9
valid_sources[0x1b]	82959	1			T3	218		T10	1		T13	2
valid_sources[0x1c]	30463	1			T2	8		T3	209		T10	6
valid_sources[0x1d]	21934	1			T2	3		T3	260		T10	7
valid_sources[0x1e]	18845	1			T3	222		T10	4		T4	2
valid_sources[0x1f]	20674	1			T2	14		T3	224		T10	3
valid_sources[0x20]	22550	1			T2	1		T3	250		T10	6
valid_sources[0x21]	20194	1			T2	11		T3	244		T10	3
valid_sources[0x22]	20505	1			T2	1		T3	239		T10	4
valid_sources[0x23]	19978	1			T2	6		T3	180		T9	2
valid_sources[0x24]	19422	1			T3	211		T10	2		T13	14
valid_sources[0x25]	21484	1			T3	193		T10	7		T13	6
valid_sources[0x26]	20984	1			T2	15		T3	240		T10	11
valid_sources[0x27]	18605	1			T1	3		T2	12		T3	247
valid_sources[0x28]	20327	1			T3	291		T10	5		T13	1
valid_sources[0x29]	53424	1			T2	14		T3	212		T10	9
valid_sources[0x2a]	19307	1			T3	241		T9	2		T10	3
valid_sources[0x2b]	19302	1			T2	7		T3	160		T10	5
valid_sources[0x2c]	18925	1			T2	14		T3	144		T10	3
valid_sources[0x2d]	19859	1			T1	6		T3	304		T10	6
valid_sources[0x2e]	19458	1			T1	4		T2	4		T3	209
valid_sources[0x2f]	19477	1			T2	3		T3	269		T9	3
valid_sources[0x30]	19826	1			T2	3		T3	199		T9	2
valid_sources[0x31]	19870	1			T3	224		T10	4		T14	6
valid_sources[0x32]	25085	1			T2	23		T3	194		T9	3
valid_sources[0x33]	52543	1			T2	9		T3	323		T10	4
valid_sources[0x34]	73959	1			T3	236		T10	9		T11	20
valid_sources[0x35]	19691	1			T3	275		T10	4		T13	2
valid_sources[0x36]	19070	1			T2	1		T3	204		T10	4
valid_sources[0x37]	25667	1			T3	279		T10	7		T13	2
valid_sources[0x38]	28094	1			T2	10		T3	218		T10	1
valid_sources[0x39]	23861	1			T3	195		T10	5		T13	5
valid_sources[0x3a]	18718	1			T3	313		T10	3		T13	1
valid_sources[0x3b]	286616	1			T2	8		T3	226		T10	5
valid_sources[0x3c]	19300	1			T2	6		T3	202		T10	4
valid_sources[0x3d]	19229	1			T1	1		T2	5		T3	198
valid_sources[0x3e]	19606	1			T3	232		T10	4		T13	9
valid_sources[0x3f]	60470	1			T2	1		T3	284		T10	5
valid_sources[0x40]	19079	1			T2	16		T3	247		T10	4
valid_sources[0x41]	18456	1			T2	1		T3	222		T10	6
valid_sources[0x42]	18565	1			T2	20		T3	211		T10	7
valid_sources[0x43]	73683	1			T2	21		T3	228		T10	9
valid_sources[0x44]	25305	1			T1	4		T3	295		T10	8
valid_sources[0x45]	22945	1			T1	4		T2	10		T3	247
valid_sources[0x46]	18739	1			T3	240		T10	3		T14	5
valid_sources[0x47]	19887	1			T3	244		T10	5		T13	6
valid_sources[0x48]	39676	1			T3	202		T10	2		T13	2
valid_sources[0x49]	18312	1			T3	209		T10	3		T13	17
valid_sources[0x4a]	18997	1			T2	3		T3	295		T9	3
valid_sources[0x4b]	18550	1			T1	7		T3	200		T10	4
valid_sources[0x4c]	18521	1			T3	265		T10	5		T13	7
valid_sources[0x4d]	19191	1			T3	276		T10	5		T13	1
valid_sources[0x4e]	21273	1			T2	13		T3	251		T10	5
valid_sources[0x4f]	45820	1			T2	3		T3	210		T10	9
valid_sources[0x50]	19752	1			T2	1		T3	183		T10	5
valid_sources[0x51]	20349	1			T3	257		T10	6		T13	9
valid_sources[0x52]	23576	1			T3	184		T9	2		T10	2
valid_sources[0x53]	20306	1			T3	235		T10	2		T13	5
valid_sources[0x54]	22915	1			T2	6		T3	206		T10	2
valid_sources[0x55]	19474	1			T2	12		T3	170		T10	8
valid_sources[0x56]	18252	1			T3	145		T10	2		T13	1
valid_sources[0x57]	22576	1			T2	4		T3	300		T10	3
valid_sources[0x58]	19419	1			T2	2		T3	242		T10	7
valid_sources[0x59]	25417	1			T1	6		T2	10		T3	210
valid_sources[0x5a]	37677	1			T2	20		T3	277		T10	2
valid_sources[0x5b]	19290	1			T2	7		T3	254		T10	4
valid_sources[0x5c]	18323	1			T2	8		T3	172		T10	5
valid_sources[0x5d]	21555	1			T2	2		T3	188		T10	8
valid_sources[0x5e]	19279	1			T2	1		T3	194		T10	10
valid_sources[0x5f]	18689	1			T3	236		T10	3		T13	2
valid_sources[0x60]	20446	1			T2	18		T3	263		T10	10
valid_sources[0x61]	22030	1			T2	2		T3	279		T10	3
valid_sources[0x62]	46911	1			T1	14		T2	13		T3	191
valid_sources[0x63]	23017	1			T2	3		T3	205		T10	8
valid_sources[0x64]	20686	1			T2	7		T3	176		T10	4
valid_sources[0x65]	19267	1			T3	180		T10	8		T13	4
valid_sources[0x66]	18689	1			T3	288		T10	7		T13	7
valid_sources[0x67]	19920	1			T2	10		T3	277		T10	8
valid_sources[0x68]	18575	1			T2	3		T3	219		T10	8
valid_sources[0x69]	21244	1			T3	177		T10	3		T13	6
valid_sources[0x6a]	18907	1			T2	5		T3	240		T10	3
valid_sources[0x6b]	19486	1			T2	3		T3	292		T10	3
valid_sources[0x6c]	25773	1			T1	1		T3	236		T10	7
valid_sources[0x6d]	22464	1			T3	233		T10	7		T13	26
valid_sources[0x6e]	38939	1			T2	25		T3	163		T10	6
valid_sources[0x6f]	20216	1			T2	1		T3	238		T10	5
valid_sources[0x70]	18863	1			T2	7		T3	222		T10	7
valid_sources[0x71]	22358	1			T3	220		T10	4		T14	8
valid_sources[0x72]	82948	1			T2	1		T3	149		T10	3
valid_sources[0x73]	19148	1			T2	6		T3	254		T10	10
valid_sources[0x74]	19999	1			T2	3		T3	178		T10	9
valid_sources[0x75]	19056	1			T2	6		T3	220		T10	1
valid_sources[0x76]	19912	1			T2	5		T3	245		T10	4
valid_sources[0x77]	18461	1			T3	224		T10	2		T13	8
valid_sources[0x78]	24402	1			T3	218		T10	3		T14	9
valid_sources[0x79]	19512	1			T3	319		T10	7		T13	1
valid_sources[0x7a]	19317	1			T3	201		T10	2		T13	1
valid_sources[0x7b]	20879	1			T2	3		T3	164		T10	7
valid_sources[0x7c]	19861	1			T2	3		T3	273		T10	2
valid_sources[0x7d]	19656	1			T2	2		T3	214		T10	4
valid_sources[0x7e]	18399	1			T2	6		T3	199		T10	5
valid_sources[0x7f]	19001	1			T2	5		T3	189		T10	4
valid_sources[0x80]	22616	1			T3	257		T10	9		T13	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3127002

1

T1

68

T2

350

T3

27398

values[0x0]

all_enables

biggest_size

273450

1

T1

74

T2

192

T3

1441

values[0x1]

all_enables

biggest_size

272190

1

T1

70

T2

197

T3

1488