Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.88		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	198431593	13134	0	0
claim_transition_if_regwen_rd_A	198431593	1131	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198431593	13134	0	0
T3	336112	2	0	0
T4	3600	0	0	0
T5	100721	0	0	0
T9	1980	0	0	0
T10	34833	0	0	0
T11	933	0	0	0
T12	1704	0	0	0
T13	30839	0	0	0
T14	733446	0	0	0
T17	0	1	0	0
T21	981	0	0	0
T45	0	2	0	0
T82	0	1	0	0
T94	0	9	0	0
T116	0	12	0	0
T156	0	14	0	0
T157	0	1	0	0
T158	0	4	0	0
T159	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198431593	1131	0	0
T17	182378	8	0	0
T18	385023	0	0	0
T19	102713	0	0	0
T20	47271	0	0	0
T29	1291	0	0	0
T30	17277	0	0	0
T31	6522	0	0	0
T32	906	0	0	0
T33	79926	0	0	0
T92	5398	0	0	0
T118	0	7	0	0
T158	0	7	0	0
T159	0	7	0	0
T160	0	14	0	0
T161	0	1	0	0
T162	0	9	0	0
T163	0	17	0	0
T164	0	32	0	0
T165	0	11	0	0