Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1813980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2052631

1

T2

1729

T3

12

T4

9067

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3498161	1			T2	2271		T3	130		T4	15984
values[0x0]	184257	1			T2	352		T3	9		T4	652
values[0x1]	184193	1			T2	344		T3	7		T4	656

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1441480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2425131

1

T2

2004

T3

52

T4

10693

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12523	1			T2	12		T4	129		T11	16
valid_sources[0x01]	12171	1			T2	7		T4	136		T11	19
valid_sources[0x02]	12071	1			T2	13		T4	25		T11	11
valid_sources[0x03]	15321	1			T2	14		T4	107		T11	13
valid_sources[0x04]	11864	1			T2	11		T4	149		T11	16
valid_sources[0x05]	11900	1			T2	18		T4	33		T11	20
valid_sources[0x06]	59480	1			T2	9		T4	82		T11	11
valid_sources[0x07]	13529	1			T2	11		T4	58		T11	13
valid_sources[0x08]	14237	1			T2	10		T4	71		T11	11
valid_sources[0x09]	11944	1			T2	19		T4	48		T11	20
valid_sources[0x0a]	12551	1			T2	10		T4	55		T11	13
valid_sources[0x0b]	13010	1			T2	11		T4	58		T10	3
valid_sources[0x0c]	12032	1			T2	14		T4	71		T11	14
valid_sources[0x0d]	29873	1			T2	15		T4	22		T11	11
valid_sources[0x0e]	17134	1			T2	8		T4	69		T11	14
valid_sources[0x0f]	11727	1			T2	14		T4	35		T11	19
valid_sources[0x10]	16221	1			T2	16		T4	46		T11	18
valid_sources[0x11]	11417	1			T2	5		T4	74		T11	15
valid_sources[0x12]	11769	1			T2	7		T4	62		T11	7
valid_sources[0x13]	109314	1			T2	17		T4	56		T10	1
valid_sources[0x14]	11732	1			T2	14		T4	59		T11	13
valid_sources[0x15]	13163	1			T2	6		T4	53		T11	13
valid_sources[0x16]	17508	1			T2	8		T4	51		T11	10
valid_sources[0x17]	12083	1			T2	10		T4	123		T11	14
valid_sources[0x18]	11732	1			T2	8		T4	35		T11	19
valid_sources[0x19]	12141	1			T2	18		T4	69		T11	14
valid_sources[0x1a]	23832	1			T2	12		T4	60		T11	25
valid_sources[0x1b]	11842	1			T2	18		T4	40		T11	19
valid_sources[0x1c]	11871	1			T2	18		T4	107		T11	14
valid_sources[0x1d]	11954	1			T2	12		T4	54		T11	15
valid_sources[0x1e]	12081	1			T2	16		T4	40		T10	1
valid_sources[0x1f]	12093	1			T2	12		T3	146		T4	125
valid_sources[0x20]	11616	1			T2	9		T4	31		T11	13
valid_sources[0x21]	11756	1			T2	12		T4	87		T11	16
valid_sources[0x22]	11825	1			T2	13		T4	54		T11	14
valid_sources[0x23]	13885	1			T2	17		T4	35		T10	2
valid_sources[0x24]	11653	1			T2	7		T4	28		T11	13
valid_sources[0x25]	12918	1			T2	12		T4	87		T11	11
valid_sources[0x26]	12303	1			T2	8		T4	28		T11	8
valid_sources[0x27]	13336	1			T2	14		T4	27		T11	20
valid_sources[0x28]	12221	1			T2	11		T4	78		T11	11
valid_sources[0x29]	14255	1			T2	7		T4	55		T11	22
valid_sources[0x2a]	12165	1			T2	9		T4	107		T11	16
valid_sources[0x2b]	12541	1			T2	8		T4	64		T11	21
valid_sources[0x2c]	13060	1			T2	19		T4	143		T11	16
valid_sources[0x2d]	11895	1			T2	6		T4	50		T11	10
valid_sources[0x2e]	12217	1			T2	14		T4	89		T11	17
valid_sources[0x2f]	11772	1			T2	20		T4	34		T11	5
valid_sources[0x30]	11670	1			T2	11		T4	75		T11	20
valid_sources[0x31]	12288	1			T2	19		T4	58		T11	23
valid_sources[0x32]	12467	1			T2	10		T4	41		T11	13
valid_sources[0x33]	11948	1			T2	15		T4	111		T11	15
valid_sources[0x34]	11949	1			T2	14		T4	22		T11	18
valid_sources[0x35]	11866	1			T2	10		T4	36		T11	15
valid_sources[0x36]	11574	1			T2	6		T4	72		T11	14
valid_sources[0x37]	46597	1			T2	12		T4	76		T11	13
valid_sources[0x38]	11918	1			T2	13		T4	72		T11	10
valid_sources[0x39]	11924	1			T2	9		T4	46		T11	8
valid_sources[0x3a]	12011	1			T2	13		T4	94		T11	13
valid_sources[0x3b]	12098	1			T2	7		T4	23		T11	16
valid_sources[0x3c]	11923	1			T2	14		T4	52		T11	16
valid_sources[0x3d]	11723	1			T2	13		T4	55		T11	25
valid_sources[0x3e]	12715	1			T2	15		T4	78		T11	11
valid_sources[0x3f]	12424	1			T2	10		T4	73		T11	13
valid_sources[0x40]	13573	1			T2	17		T4	39		T11	15
valid_sources[0x41]	12784	1			T2	13		T4	72		T11	15
valid_sources[0x42]	12074	1			T2	17		T4	40		T11	25
valid_sources[0x43]	11677	1			T2	13		T4	65		T11	21
valid_sources[0x44]	13259	1			T2	8		T4	111		T11	20
valid_sources[0x45]	12048	1			T2	9		T4	59		T11	21
valid_sources[0x46]	11825	1			T2	16		T4	37		T11	13
valid_sources[0x47]	11863	1			T2	12		T4	70		T11	12
valid_sources[0x48]	12250	1			T2	15		T4	49		T11	9
valid_sources[0x49]	11936	1			T2	17		T4	67		T11	6
valid_sources[0x4a]	11546	1			T2	8		T4	92		T11	17
valid_sources[0x4b]	11715	1			T2	7		T4	40		T11	17
valid_sources[0x4c]	12268	1			T2	10		T4	81		T11	12
valid_sources[0x4d]	11556	1			T2	17		T4	48		T11	12
valid_sources[0x4e]	14147	1			T2	12		T4	40		T11	14
valid_sources[0x4f]	14391	1			T2	9		T4	89		T11	21
valid_sources[0x50]	12526	1			T2	12		T4	28		T11	12
valid_sources[0x51]	13409	1			T2	12		T4	51		T11	14
valid_sources[0x52]	12104	1			T2	15		T4	25		T10	1
valid_sources[0x53]	12026	1			T2	16		T4	45		T11	14
valid_sources[0x54]	11708	1			T2	13		T4	74		T11	17
valid_sources[0x55]	16454	1			T2	16		T4	41		T11	12
valid_sources[0x56]	12184	1			T2	11		T4	97		T11	16
valid_sources[0x57]	11918	1			T2	12		T4	38		T11	15
valid_sources[0x58]	12072	1			T2	13		T4	73		T11	20
valid_sources[0x59]	17323	1			T2	6		T4	52		T11	10
valid_sources[0x5a]	11839	1			T2	5		T4	47		T11	12
valid_sources[0x5b]	11991	1			T2	13		T4	46		T11	13
valid_sources[0x5c]	11706	1			T2	5		T4	61		T11	12
valid_sources[0x5d]	12189	1			T2	11		T4	101		T11	23
valid_sources[0x5e]	12519	1			T2	14		T4	42		T11	15
valid_sources[0x5f]	12251	1			T2	16		T4	57		T11	21
valid_sources[0x60]	12216	1			T2	8		T4	43		T11	7
valid_sources[0x61]	12203	1			T2	14		T4	57		T11	19
valid_sources[0x62]	16680	1			T2	13		T4	69		T11	12
valid_sources[0x63]	12892	1			T2	13		T4	116		T11	16
valid_sources[0x64]	12361	1			T2	15		T4	75		T11	11
valid_sources[0x65]	13280	1			T2	10		T4	84		T11	29
valid_sources[0x66]	11763	1			T2	9		T4	118		T11	17
valid_sources[0x67]	12276	1			T2	13		T4	32		T11	18
valid_sources[0x68]	12467	1			T2	7		T4	49		T11	8
valid_sources[0x69]	11705	1			T2	9		T4	46		T11	18
valid_sources[0x6a]	11659	1			T2	14		T4	72		T10	2
valid_sources[0x6b]	68602	1			T2	16		T4	108		T10	1
valid_sources[0x6c]	12718	1			T2	6		T4	95		T10	1
valid_sources[0x6d]	12818	1			T2	7		T4	74		T11	18
valid_sources[0x6e]	11655	1			T2	8		T4	55		T11	19
valid_sources[0x6f]	12377	1			T2	9		T4	94		T11	26
valid_sources[0x70]	11749	1			T2	8		T4	70		T11	13
valid_sources[0x71]	12044	1			T2	9		T4	45		T11	11
valid_sources[0x72]	12097	1			T2	7		T4	86		T11	20
valid_sources[0x73]	11713	1			T2	8		T4	44		T11	8
valid_sources[0x74]	11860	1			T2	11		T4	63		T11	16
valid_sources[0x75]	12426	1			T2	12		T4	130		T11	11
valid_sources[0x76]	12093	1			T2	8		T4	82		T11	22
valid_sources[0x77]	12286	1			T2	14		T4	115		T11	11
valid_sources[0x78]	11933	1			T2	11		T4	58		T11	20
valid_sources[0x79]	12505	1			T2	4		T4	10		T11	21
valid_sources[0x7a]	12370	1			T2	10		T4	44		T11	6
valid_sources[0x7b]	34351	1			T2	17		T4	61		T11	7
valid_sources[0x7c]	12136	1			T2	12		T4	93		T11	18
valid_sources[0x7d]	11944	1			T2	13		T4	73		T11	25
valid_sources[0x7e]	11977	1			T2	14		T4	46		T11	12
valid_sources[0x7f]	12798	1			T2	15		T4	39		T11	18
valid_sources[0x80]	11824	1			T2	17		T4	75		T11	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1734365

1

T2

1114

T3

1

T4

7920

values[0x0]

all_enables

biggest_size

160021

1

T2

321

T3

7

T4

575

values[0x1]

all_enables

biggest_size

158245

1

T2

294

T3

4

T4

572