Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105699348	14951	0	0
claim_transition_if_regwen_rd_A	105699348	2157	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105699348	14951	0	0
T18	214589	1	0	0
T19	375015	0	0	0
T31	14947	0	0	0
T32	9040	0	0	0
T33	4250	0	0	0
T34	22739	0	0	0
T39	34522	0	0	0
T47	0	4	0	0
T61	6124	0	0	0
T83	24030	0	0	0
T89	1730	0	0	0
T91	0	2	0	0
T118	0	1	0	0
T120	0	8	0	0
T121	0	15	0	0
T153	0	7	0	0
T154	0	1	0	0
T155	0	9	0	0
T156	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105699348	2157	0	0
T4	104660	3	0	0
T5	32846	0	0	0
T10	2114	0	0	0
T11	44253	0	0	0
T12	31436	0	0	0
T13	44948	0	0	0
T14	27922	0	0	0
T15	30196	0	0	0
T16	119848	0	0	0
T35	916	0	0	0
T118	0	5	0	0
T141	0	48	0	0
T142	0	10	0	0
T156	0	6	0	0
T157	0	5	0	0
T158	0	12	0	0
T159	0	42	0	0
T160	0	222	0	0
T161	0	6	0	0