Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1837843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2083630

1

T1

1

T2

723

T5

293

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3549050	1			T1	2		T2	657		T5	256
values[0x0]	185417	1			T1	1		T2	277		T5	114
values[0x1]	187006	1			T2	299		T5	106		T9	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2462157

1

T1

2

T2

862

T5

330

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14874	1			T2	5		T4	13		T14	17
valid_sources[0x01]	14476	1			T2	5		T4	15		T13	1
valid_sources[0x02]	13814	1			T2	1		T4	6		T13	2
valid_sources[0x03]	15578	1			T2	5		T4	4		T13	1
valid_sources[0x04]	13759	1			T2	4		T5	1		T4	13
valid_sources[0x05]	14800	1			T2	7		T5	4		T4	2
valid_sources[0x06]	29984	1			T2	9		T4	7		T11	1
valid_sources[0x07]	15090	1			T2	9		T4	6		T11	1
valid_sources[0x08]	14349	1			T2	8		T4	10		T13	1
valid_sources[0x09]	14344	1			T2	2		T4	10		T14	13
valid_sources[0x0a]	14106	1			T2	10		T4	2		T13	1
valid_sources[0x0b]	14038	1			T2	6		T5	6		T4	10
valid_sources[0x0c]	14590	1			T2	7		T5	5		T4	13
valid_sources[0x0d]	14213	1			T2	5		T5	1		T4	1
valid_sources[0x0e]	13880	1			T2	7		T5	1		T4	1
valid_sources[0x0f]	18865	1			T2	7		T5	4		T4	3
valid_sources[0x10]	14221	1			T2	4		T5	10		T4	9
valid_sources[0x11]	14065	1			T2	5		T4	7		T13	1
valid_sources[0x12]	14078	1			T2	4		T5	6		T4	9
valid_sources[0x13]	14119	1			T2	3		T5	2		T4	10
valid_sources[0x14]	13906	1			T2	5		T5	3		T4	2
valid_sources[0x15]	14615	1			T2	7		T4	13		T13	3
valid_sources[0x16]	16922	1			T2	2		T4	8		T81	1
valid_sources[0x17]	13770	1			T2	5		T5	2		T4	6
valid_sources[0x18]	14203	1			T2	3		T4	6		T11	2
valid_sources[0x19]	14034	1			T2	9		T5	2		T4	4
valid_sources[0x1a]	14168	1			T2	4		T5	1		T4	15
valid_sources[0x1b]	16165	1			T2	1		T5	4		T4	16
valid_sources[0x1c]	14215	1			T2	3		T5	2		T4	7
valid_sources[0x1d]	15570	1			T2	6		T5	3		T4	10
valid_sources[0x1e]	14344	1			T2	4		T5	2		T4	2
valid_sources[0x1f]	13838	1			T2	9		T4	4		T11	2
valid_sources[0x20]	15483	1			T2	10		T4	11		T22	8
valid_sources[0x21]	14029	1			T2	5		T5	3		T4	15
valid_sources[0x22]	13834	1			T5	3		T4	12		T22	12
valid_sources[0x23]	14177	1			T2	3		T5	2		T4	4
valid_sources[0x24]	14055	1			T2	4		T5	1		T4	12
valid_sources[0x25]	14471	1			T2	10		T5	6		T4	3
valid_sources[0x26]	13974	1			T2	9		T5	3		T4	7
valid_sources[0x27]	15007	1			T2	4		T4	6		T13	2
valid_sources[0x28]	128217	1			T2	4		T4	11		T13	1
valid_sources[0x29]	15997	1			T2	2		T4	5		T11	1
valid_sources[0x2a]	14010	1			T2	4		T5	4		T4	9
valid_sources[0x2b]	14301	1			T2	2		T5	9		T4	1
valid_sources[0x2c]	13810	1			T2	1		T13	1		T22	23
valid_sources[0x2d]	14172	1			T2	4		T4	9		T11	1
valid_sources[0x2e]	14011	1			T2	5		T5	5		T4	22
valid_sources[0x2f]	13982	1			T2	4		T5	6		T4	16
valid_sources[0x30]	13725	1			T2	5		T5	4		T4	1
valid_sources[0x31]	13972	1			T2	7		T5	5		T9	1
valid_sources[0x32]	15421	1			T2	6		T4	6		T13	1
valid_sources[0x33]	14343	1			T2	1		T4	10		T13	1
valid_sources[0x34]	15371	1			T2	4		T5	10		T4	6
valid_sources[0x35]	14580	1			T2	7		T4	21		T11	2
valid_sources[0x36]	13945	1			T2	11		T4	6		T11	2
valid_sources[0x37]	14441	1			T2	8		T4	6		T13	1
valid_sources[0x38]	14229	1			T2	3		T4	2		T13	1
valid_sources[0x39]	14226	1			T2	1		T5	1		T4	6
valid_sources[0x3a]	16178	1			T2	3		T5	3		T4	8
valid_sources[0x3b]	14436	1			T2	8		T4	17		T11	2
valid_sources[0x3c]	13765	1			T2	2		T5	8		T11	1
valid_sources[0x3d]	13943	1			T2	5		T5	4		T4	9
valid_sources[0x3e]	15496	1			T2	3		T4	7		T11	1
valid_sources[0x3f]	13944	1			T2	2		T4	6		T11	1
valid_sources[0x40]	15182	1			T2	2		T5	3		T4	13
valid_sources[0x41]	15509	1			T2	1		T5	2		T4	8
valid_sources[0x42]	13866	1			T2	11		T4	17		T11	1
valid_sources[0x43]	14372	1			T2	5		T4	9		T13	2
valid_sources[0x44]	15710	1			T2	7		T4	5		T13	2
valid_sources[0x45]	13931	1			T2	7		T4	12		T13	2
valid_sources[0x46]	14016	1			T2	4		T4	8		T22	2
valid_sources[0x47]	13880	1			T2	9		T4	14		T11	1
valid_sources[0x48]	14166	1			T2	4		T5	1		T4	5
valid_sources[0x49]	15058	1			T2	9		T5	5		T4	5
valid_sources[0x4a]	18592	1			T2	9		T4	7		T13	3
valid_sources[0x4b]	15348	1			T2	4		T4	4		T11	2
valid_sources[0x4c]	14325	1			T2	6		T4	5		T13	4
valid_sources[0x4d]	14210	1			T2	3		T5	4		T4	4
valid_sources[0x4e]	16199	1			T2	9		T5	1		T4	5
valid_sources[0x4f]	16712	1			T2	4		T5	1		T11	1
valid_sources[0x50]	13850	1			T2	2		T5	5		T4	5
valid_sources[0x51]	16326	1			T2	5		T5	5		T4	15
valid_sources[0x52]	15861	1			T2	7		T4	6		T14	31
valid_sources[0x53]	35537	1			T2	7		T4	8		T22	3
valid_sources[0x54]	15279	1			T2	1		T5	1		T4	2
valid_sources[0x55]	14293	1			T2	5		T4	9		T11	1
valid_sources[0x56]	14196	1			T1	2		T2	9		T4	1
valid_sources[0x57]	18001	1			T2	14		T4	10		T11	1
valid_sources[0x58]	14235	1			T2	9		T4	11		T13	2
valid_sources[0x59]	15703	1			T2	5		T5	1		T11	2
valid_sources[0x5a]	14199	1			T2	5		T5	3		T4	7
valid_sources[0x5b]	13759	1			T2	9		T5	9		T4	9
valid_sources[0x5c]	13931	1			T2	5		T4	12		T13	3
valid_sources[0x5d]	17755	1			T2	3		T4	8		T13	3
valid_sources[0x5e]	14100	1			T2	4		T5	4		T4	5
valid_sources[0x5f]	17372	1			T2	7		T5	3		T4	7
valid_sources[0x60]	13701	1			T2	5		T5	3		T4	10
valid_sources[0x61]	13709	1			T2	11		T4	13		T11	1
valid_sources[0x62]	14372	1			T2	3		T5	1		T4	13
valid_sources[0x63]	14051	1			T2	11		T4	9		T13	3
valid_sources[0x64]	13913	1			T2	3		T4	5		T13	1
valid_sources[0x65]	15863	1			T2	2		T5	1		T4	7
valid_sources[0x66]	14101	1			T2	3		T5	7		T4	18
valid_sources[0x67]	14189	1			T2	2		T5	2		T4	4
valid_sources[0x68]	13814	1			T2	7		T5	2		T4	15
valid_sources[0x69]	14425	1			T2	1		T5	2		T4	10
valid_sources[0x6a]	14155	1			T2	2		T4	4		T13	2
valid_sources[0x6b]	16309	1			T2	4		T4	3		T14	5
valid_sources[0x6c]	14054	1			T5	3		T4	8		T14	2
valid_sources[0x6d]	14911	1			T2	5		T5	7		T4	11
valid_sources[0x6e]	17196	1			T2	2		T5	4		T4	5
valid_sources[0x6f]	14558	1			T5	1		T4	4		T11	1
valid_sources[0x70]	14090	1			T2	3		T4	3		T13	1
valid_sources[0x71]	18042	1			T2	7		T5	3		T4	3
valid_sources[0x72]	14012	1			T2	4		T4	4		T11	2
valid_sources[0x73]	14237	1			T2	2		T5	3		T4	7
valid_sources[0x74]	14120	1			T2	5		T5	1		T4	8
valid_sources[0x75]	15775	1			T2	1		T4	11		T13	3
valid_sources[0x76]	14140	1			T2	4		T5	1		T4	4
valid_sources[0x77]	13960	1			T2	11		T5	2		T4	12
valid_sources[0x78]	15402	1			T2	2		T5	9		T4	10
valid_sources[0x79]	14033	1			T2	8		T5	6		T4	4
valid_sources[0x7a]	14124	1			T2	4		T5	4		T4	5
valid_sources[0x7b]	14137	1			T2	4		T5	2		T34	1
valid_sources[0x7c]	14327	1			T2	7		T5	1		T4	8
valid_sources[0x7d]	14734	1			T2	7		T4	10		T13	2
valid_sources[0x7e]	14132	1			T2	1		T5	1		T4	2
valid_sources[0x7f]	15331	1			T2	3		T4	1		T11	5
valid_sources[0x80]	13713	1			T2	7		T5	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1761279

1

T1

1

T2

234

T5

133

values[0x0]

all_enables

biggest_size

161643

1

T2

236

T5

86

T9

3

values[0x1]

all_enables

biggest_size

160708

1

T2

253

T5

74

T4

322