Line Coverage for Module :
tlul_cmd_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 20 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 46 | 4 | 4 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
20 |
1 |
1 |
33 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
54 |
1 |
1 |
Assert Coverage for Module :
tlul_cmd_intg_gen
Assertion Details
PayMaxWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
819 |
819 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |