Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	107106227	27819	0	0
claim_transition_if_regwen_rd_A	107106227	2315	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107106227	27819	0	0
T37	0	11	0	0
T47	10570	0	0	0
T51	0	8	0	0
T58	35215	0	0	0
T83	324253	1	0	0
T84	24710	0	0	0
T86	936	0	0	0
T87	0	1	0	0
T88	0	2	0	0
T95	0	6	0	0
T165	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T168	0	3	0	0
T169	25711	0	0	0
T170	1041	0	0	0
T171	5382	0	0	0
T172	6733	0	0	0
T173	7137	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107106227	2315	0	0
T36	23491	0	0	0
T38	0	16	0	0
T72	13365	0	0	0
T87	185139	10	0	0
T98	0	20	0	0
T117	0	56	0	0
T124	0	1	0	0
T174	0	2	0	0
T175	0	16	0	0
T176	0	19	0	0
T177	0	4	0	0
T178	0	6	0	0
T179	1973	0	0	0
T180	6215	0	0	0
T181	4640	0	0	0
T182	3574	0	0	0
T183	55461	0	0	0
T184	56907	0	0	0
T185	30289	0	0	0