Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3043369	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3459747

1

T1

173

T2

281

T3

110

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5848483	1			T1	151		T2	208		T3	99
values[0x0]	326077	1			T1	62		T2	103		T3	47
values[0x1]	328556	1			T1	50		T2	105		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2416339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4086777

1

T1

196

T2

310

T3

121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20439	1			T11	7		T19	5		T18	2
valid_sources[0x01]	20713	1			T11	15		T19	16		T7	1
valid_sources[0x02]	23252	1			T1	2		T2	3		T11	1
valid_sources[0x03]	20973	1			T1	1		T11	8		T19	2
valid_sources[0x04]	23279	1			T1	1		T11	5		T6	1
valid_sources[0x05]	20665	1			T1	2		T11	8		T19	8
valid_sources[0x06]	21349	1			T1	2		T11	3		T6	2
valid_sources[0x07]	22661	1			T1	3		T2	1		T3	19
valid_sources[0x08]	21384	1			T1	1		T11	3		T6	1
valid_sources[0x09]	27378	1			T1	1		T11	3		T18	1
valid_sources[0x0a]	20550	1			T1	1		T11	13		T6	1
valid_sources[0x0b]	26093	1			T2	3		T6	3		T19	11
valid_sources[0x0c]	20151	1			T11	8		T7	1		T23	1
valid_sources[0x0d]	20834	1			T2	5		T11	3		T7	3
valid_sources[0x0e]	20896	1			T11	1		T19	10		T7	1
valid_sources[0x0f]	64400	1			T1	2		T2	2		T11	2
valid_sources[0x10]	21561	1			T2	1		T11	10		T6	1
valid_sources[0x11]	31770	1			T1	3		T2	1		T11	2
valid_sources[0x12]	20543	1			T2	3		T9	2		T11	2
valid_sources[0x13]	87801	1			T1	1		T2	1		T3	1
valid_sources[0x14]	20713	1			T9	1		T11	9		T19	1
valid_sources[0x15]	25737	1			T2	1		T6	3		T19	1
valid_sources[0x16]	21628	1			T2	1		T11	2		T19	2
valid_sources[0x17]	20836	1			T2	2		T9	2		T11	3
valid_sources[0x18]	21128	1			T11	2		T6	1		T19	1
valid_sources[0x19]	23174	1			T1	1		T2	2		T6	1
valid_sources[0x1a]	23941	1			T2	2		T11	4		T19	10
valid_sources[0x1b]	21138	1			T11	4		T6	1		T19	10
valid_sources[0x1c]	21621	1			T11	5		T6	3		T19	8
valid_sources[0x1d]	22507	1			T1	2		T18	2		T7	1
valid_sources[0x1e]	22708	1			T1	1		T9	2		T11	5
valid_sources[0x1f]	20320	1			T1	3		T18	1		T23	3
valid_sources[0x20]	20283	1			T1	3		T2	5		T6	2
valid_sources[0x21]	20646	1			T1	1		T9	7		T10	4
valid_sources[0x22]	21728	1			T2	2		T11	4		T6	1
valid_sources[0x23]	25934	1			T11	2		T19	13		T18	2
valid_sources[0x24]	22761	1			T6	1		T19	7		T18	1
valid_sources[0x25]	20409	1			T11	1		T19	5		T18	1
valid_sources[0x26]	21057	1			T2	8		T3	20		T11	1
valid_sources[0x27]	20019	1			T1	2		T2	2		T11	14
valid_sources[0x28]	20512	1			T1	2		T2	11		T11	6
valid_sources[0x29]	25354	1			T3	15		T9	1		T11	1
valid_sources[0x2a]	20876	1			T1	3		T11	3		T19	4
valid_sources[0x2b]	20740	1			T1	1		T2	7		T18	1
valid_sources[0x2c]	23008	1			T2	1		T10	1		T19	4
valid_sources[0x2d]	21424	1			T1	1		T2	2		T11	7
valid_sources[0x2e]	20824	1			T11	9		T6	1		T19	5
valid_sources[0x2f]	20426	1			T6	1		T19	4		T13	2
valid_sources[0x30]	22600	1			T1	1		T9	1		T11	13
valid_sources[0x31]	24233	1			T2	1		T9	2		T11	5
valid_sources[0x32]	20451	1			T2	10		T11	10		T6	1
valid_sources[0x33]	22837	1			T1	2		T11	6		T19	2
valid_sources[0x34]	21865	1			T9	15		T11	1		T6	1
valid_sources[0x35]	77805	1			T1	2		T11	4		T6	3
valid_sources[0x36]	25008	1			T1	2		T2	2		T11	5
valid_sources[0x37]	22629	1			T1	1		T3	10		T9	3
valid_sources[0x38]	21157	1			T1	1		T2	3		T11	2
valid_sources[0x39]	20643	1			T1	3		T2	2		T13	6
valid_sources[0x3a]	90531	1			T1	2		T2	3		T11	3
valid_sources[0x3b]	22734	1			T11	1		T6	1		T19	5
valid_sources[0x3c]	21113	1			T1	1		T11	5		T6	2
valid_sources[0x3d]	21706	1			T1	1		T11	1		T6	1
valid_sources[0x3e]	29008	1			T11	1		T6	1		T19	2
valid_sources[0x3f]	23721	1			T2	1		T11	4		T6	1
valid_sources[0x40]	20375	1			T3	12		T11	7		T6	2
valid_sources[0x41]	35223	1			T1	3		T9	2		T11	15
valid_sources[0x42]	20535	1			T1	1		T11	3		T19	6
valid_sources[0x43]	20839	1			T1	2		T11	9		T19	14
valid_sources[0x44]	25731	1			T1	2		T2	6		T11	13
valid_sources[0x45]	25996	1			T2	1		T3	4		T11	4
valid_sources[0x46]	23498	1			T1	1		T11	5		T6	2
valid_sources[0x47]	21348	1			T1	2		T11	4		T6	1
valid_sources[0x48]	22683	1			T9	1		T11	9		T19	5
valid_sources[0x49]	22011	1			T1	1		T11	3		T6	2
valid_sources[0x4a]	38513	1			T6	2		T23	1		T13	17
valid_sources[0x4b]	22613	1			T1	1		T11	1		T6	1
valid_sources[0x4c]	21925	1			T1	3		T2	5		T11	15
valid_sources[0x4d]	20494	1			T1	2		T2	3		T11	8
valid_sources[0x4e]	22108	1			T2	10		T6	2		T19	4
valid_sources[0x4f]	22611	1			T1	1		T11	14		T19	5
valid_sources[0x50]	19641	1			T1	1		T11	8		T6	1
valid_sources[0x51]	64806	1			T1	2		T11	6		T6	1
valid_sources[0x52]	26784	1			T1	2		T2	14		T9	2
valid_sources[0x53]	21702	1			T1	1		T2	4		T11	1
valid_sources[0x54]	23169	1			T1	3		T2	5		T9	1
valid_sources[0x55]	20698	1			T1	1		T3	10		T18	1
valid_sources[0x56]	23528	1			T1	1		T2	3		T11	2
valid_sources[0x57]	21251	1			T9	1		T11	5		T19	6
valid_sources[0x58]	20625	1			T11	3		T6	2		T19	4
valid_sources[0x59]	21228	1			T1	3		T2	5		T11	4
valid_sources[0x5a]	21057	1			T2	1		T6	1		T19	4
valid_sources[0x5b]	20773	1			T11	1		T6	1		T22	4
valid_sources[0x5c]	24899	1			T2	4		T11	7		T6	2
valid_sources[0x5d]	23625	1			T1	3		T9	1		T11	19
valid_sources[0x5e]	23553	1			T9	1		T11	3		T18	1
valid_sources[0x5f]	21977	1			T11	5		T6	1		T19	10
valid_sources[0x60]	20843	1			T1	1		T2	3		T9	2
valid_sources[0x61]	22164	1			T2	7		T11	4		T19	5
valid_sources[0x62]	21059	1			T11	10		T6	2		T19	7
valid_sources[0x63]	44602	1			T1	1		T10	1		T11	1
valid_sources[0x64]	21116	1			T1	2		T2	2		T9	3
valid_sources[0x65]	21340	1			T1	1		T2	1		T11	4
valid_sources[0x66]	24439	1			T2	1		T11	2		T6	1
valid_sources[0x67]	20777	1			T1	1		T11	4		T6	1
valid_sources[0x68]	25308	1			T1	2		T2	1		T9	1
valid_sources[0x69]	47848	1			T1	1		T11	6		T6	1
valid_sources[0x6a]	25211	1			T11	11		T12	5		T19	8
valid_sources[0x6b]	21935	1			T11	3		T6	1		T19	6
valid_sources[0x6c]	20627	1			T11	6		T6	1		T18	1
valid_sources[0x6d]	68528	1			T11	1		T19	2		T18	2
valid_sources[0x6e]	26230	1			T2	2		T11	4		T7	2
valid_sources[0x6f]	24331	1			T1	3		T2	8		T11	4
valid_sources[0x70]	26080	1			T2	19		T9	1		T6	1
valid_sources[0x71]	23284	1			T1	1		T11	2		T19	18
valid_sources[0x72]	20768	1			T1	2		T2	3		T11	6
valid_sources[0x73]	21936	1			T1	1		T11	6		T6	1
valid_sources[0x74]	21892	1			T1	1		T9	2		T11	4
valid_sources[0x75]	20599	1			T1	4		T2	1		T11	1
valid_sources[0x76]	23306	1			T2	4		T11	1		T19	8
valid_sources[0x77]	24476	1			T11	1		T6	1		T13	6
valid_sources[0x78]	23728	1			T2	3		T11	4		T6	1
valid_sources[0x79]	45665	1			T1	1		T11	5		T6	1
valid_sources[0x7a]	22522	1			T1	2		T19	5		T18	2
valid_sources[0x7b]	19790	1			T1	2		T2	2		T11	3
valid_sources[0x7c]	20616	1			T1	2		T11	11		T6	2
valid_sources[0x7d]	30916	1			T1	1		T9	2		T11	5
valid_sources[0x7e]	23902	1			T1	2		T2	4		T3	21
valid_sources[0x7f]	21655	1			T1	3		T3	3		T11	2
valid_sources[0x80]	20959	1			T2	10		T11	6		T19	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2895260

1

T1

72

T2

98

T3

47

values[0x0]

all_enables

biggest_size

283307

1

T1

59

T2

94

T3

35

values[0x1]

all_enables

biggest_size

281180

1

T1

42

T2

89

T3

28