Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	195308573	29348	0	0
claim_transition_if_regwen_rd_A	195308573	2599	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195308573	29348	0	0
T15	244676	1	0	0
T24	26673	0	0	0
T25	315763	0	0	0
T26	943618	0	0	0
T34	0	10	0	0
T44	21665	0	0	0
T52	36399	0	0	0
T54	0	1	0	0
T55	0	11	0	0
T59	3296	0	0	0
T81	4273	0	0	0
T86	1496	0	0	0
T87	0	16	0	0
T167	0	1	0	0
T168	0	8	0	0
T169	0	6	0	0
T170	0	12	0	0
T171	0	13	0	0
T172	5975	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195308573	2599	0	0
T15	244676	15	0	0
T24	26673	0	0	0
T25	315763	0	0	0
T26	943618	0	0	0
T44	21665	0	0	0
T52	36399	0	0	0
T59	3296	0	0	0
T81	4273	0	0	0
T86	1496	0	0	0
T122	0	14	0	0
T125	0	25	0	0
T140	0	13	0	0
T172	5975	0	0	0
T173	0	3	0	0
T174	0	15	0	0
T175	0	9	0	0
T176	0	8	0	0
T177	0	16	0	0
T178	0	127	0	0