Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2712555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3108417

1

T1

1517

T2

392

T3

799

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5188926	1			T1	2228		T2	376		T3	721
values[0x0]	315657	1			T1	220		T2	156		T3	270
values[0x1]	316389	1			T1	252		T2	184		T3	258

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2153390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3667582

1

T1

1766

T2

458

T3

890

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16729	1			T3	9		T4	2		T11	27
valid_sources[0x01]	24866	1			T3	16		T4	7		T10	1
valid_sources[0x02]	17123	1			T3	1		T4	3		T11	15
valid_sources[0x03]	18263	1			T3	8		T4	3		T12	6
valid_sources[0x04]	19232	1			T3	1		T4	10		T11	1
valid_sources[0x05]	21453	1			T3	3		T4	6		T12	2
valid_sources[0x06]	21518	1			T3	3		T4	7		T12	1
valid_sources[0x07]	16674	1			T3	8		T4	4		T12	1
valid_sources[0x08]	17712	1			T2	2		T3	1		T4	5
valid_sources[0x09]	19712	1			T3	13		T4	7		T12	3
valid_sources[0x0a]	16685	1			T3	4		T4	11		T11	16
valid_sources[0x0b]	16268	1			T3	3		T4	7		T12	6
valid_sources[0x0c]	16516	1			T3	4		T4	1		T12	3
valid_sources[0x0d]	16849	1			T4	8		T12	4		T15	2
valid_sources[0x0e]	16718	1			T3	9		T4	4		T11	1
valid_sources[0x0f]	23132	1			T3	2		T4	7		T12	4
valid_sources[0x10]	16361	1			T2	5		T3	5		T4	7
valid_sources[0x11]	17373	1			T3	1		T4	3		T12	4
valid_sources[0x12]	16670	1			T3	5		T4	7		T11	4
valid_sources[0x13]	18401	1			T3	1		T4	11		T12	3
valid_sources[0x14]	18168	1			T3	5		T4	9		T10	6
valid_sources[0x15]	21258	1			T2	22		T3	3		T4	4
valid_sources[0x16]	19122	1			T3	7		T4	9		T12	1
valid_sources[0x17]	17583	1			T3	7		T4	4		T10	1
valid_sources[0x18]	22360	1			T3	6		T4	7		T10	4
valid_sources[0x19]	18096	1			T3	8		T4	1		T11	30
valid_sources[0x1a]	18637	1			T3	6		T4	10		T12	7
valid_sources[0x1b]	17649	1			T3	3		T4	7		T11	5
valid_sources[0x1c]	83779	1			T2	54		T3	3		T4	5
valid_sources[0x1d]	17118	1			T2	54		T3	3		T4	3
valid_sources[0x1e]	36529	1			T3	4		T4	2		T11	13
valid_sources[0x1f]	17990	1			T3	3		T4	2		T12	4
valid_sources[0x20]	18504	1			T3	2		T4	9		T12	4
valid_sources[0x21]	27145	1			T3	7		T4	2		T11	33
valid_sources[0x22]	18082	1			T3	9		T4	2		T11	6
valid_sources[0x23]	16805	1			T3	7		T4	6		T12	4
valid_sources[0x24]	24781	1			T2	36		T4	9		T11	14
valid_sources[0x25]	21639	1			T3	4		T4	7		T11	3
valid_sources[0x26]	17467	1			T3	4		T4	8		T12	2
valid_sources[0x27]	16722	1			T3	1		T4	4		T11	5
valid_sources[0x28]	27410	1			T3	5		T4	10		T12	5
valid_sources[0x29]	16668	1			T3	8		T4	3		T10	3
valid_sources[0x2a]	23745	1			T3	3		T4	3		T12	2
valid_sources[0x2b]	17947	1			T3	4		T4	9		T15	3
valid_sources[0x2c]	18200	1			T4	6		T11	13		T12	3
valid_sources[0x2d]	21618	1			T3	7		T4	9		T11	6
valid_sources[0x2e]	16475	1			T3	6		T4	1		T12	6
valid_sources[0x2f]	18875	1			T2	53		T3	10		T4	19
valid_sources[0x30]	16552	1			T3	5		T4	6		T10	5
valid_sources[0x31]	23620	1			T3	4		T4	12		T12	5
valid_sources[0x32]	27915	1			T2	1		T3	6		T4	4
valid_sources[0x33]	17460	1			T4	8		T11	18		T12	8
valid_sources[0x34]	16601	1			T3	7		T4	5		T12	2
valid_sources[0x35]	17576	1			T3	1		T4	3		T11	4
valid_sources[0x36]	16462	1			T3	2		T4	7		T11	3
valid_sources[0x37]	28884	1			T3	8		T4	10		T10	1
valid_sources[0x38]	17865	1			T2	9		T3	6		T4	1
valid_sources[0x39]	18259	1			T3	2		T4	7		T12	4
valid_sources[0x3a]	17991	1			T3	6		T4	6		T12	4
valid_sources[0x3b]	24079	1			T3	3		T4	5		T12	3
valid_sources[0x3c]	17714	1			T3	1		T4	15		T12	4
valid_sources[0x3d]	97759	1			T3	11		T4	4		T10	1
valid_sources[0x3e]	16515	1			T3	2		T4	2		T10	2
valid_sources[0x3f]	19495	1			T3	4		T4	7		T12	3
valid_sources[0x40]	16834	1			T3	3		T4	3		T12	5
valid_sources[0x41]	16739	1			T3	4		T4	5		T12	3
valid_sources[0x42]	40968	1			T2	38		T3	5		T4	7
valid_sources[0x43]	16835	1			T3	6		T4	2		T12	3
valid_sources[0x44]	18122	1			T3	3		T4	1		T12	4
valid_sources[0x45]	16715	1			T3	2		T4	2		T12	4
valid_sources[0x46]	16814	1			T3	8		T4	6		T12	4
valid_sources[0x47]	16670	1			T4	4		T11	12		T12	3
valid_sources[0x48]	19215	1			T3	11		T4	6		T10	3
valid_sources[0x49]	37344	1			T3	3		T4	8		T12	3
valid_sources[0x4a]	33279	1			T4	10		T11	2		T12	1
valid_sources[0x4b]	17679	1			T3	6		T4	5		T11	1
valid_sources[0x4c]	16853	1			T3	14		T4	4		T15	5
valid_sources[0x4d]	20626	1			T3	7		T4	11		T12	4
valid_sources[0x4e]	23976	1			T2	46		T3	6		T4	15
valid_sources[0x4f]	17099	1			T4	3		T11	12		T12	1
valid_sources[0x50]	16202	1			T3	3		T4	10		T12	2
valid_sources[0x51]	19266	1			T3	5		T4	2		T12	6
valid_sources[0x52]	16567	1			T3	5		T4	3		T12	5
valid_sources[0x53]	27113	1			T3	10		T4	10		T12	3
valid_sources[0x54]	19007	1			T2	3		T3	9		T4	3
valid_sources[0x55]	16850	1			T3	7		T4	12		T12	1
valid_sources[0x56]	25170	1			T3	2		T4	11		T10	3
valid_sources[0x57]	18925	1			T2	11		T3	4		T4	2
valid_sources[0x58]	18842	1			T3	6		T4	4		T12	5
valid_sources[0x59]	16273	1			T3	11		T4	3		T10	5
valid_sources[0x5a]	29330	1			T3	4		T4	6		T12	5
valid_sources[0x5b]	16725	1			T3	6		T4	5		T12	2
valid_sources[0x5c]	16865	1			T3	2		T4	11		T11	2
valid_sources[0x5d]	16746	1			T3	3		T4	8		T10	4
valid_sources[0x5e]	17952	1			T3	8		T4	8		T12	4
valid_sources[0x5f]	17644	1			T4	4		T12	6		T14	1
valid_sources[0x60]	17873	1			T2	1		T3	7		T4	2
valid_sources[0x61]	20961	1			T2	41		T3	6		T4	7
valid_sources[0x62]	62068	1			T3	5		T4	20		T12	4
valid_sources[0x63]	16917	1			T3	9		T4	4		T12	3
valid_sources[0x64]	18361	1			T3	12		T4	7		T10	1
valid_sources[0x65]	16613	1			T3	9		T4	3		T12	5
valid_sources[0x66]	17589	1			T3	3		T4	5		T12	4
valid_sources[0x67]	19371	1			T3	9		T4	11		T12	9
valid_sources[0x68]	19073	1			T3	2		T4	9		T10	4
valid_sources[0x69]	21298	1			T3	2		T4	4		T11	34
valid_sources[0x6a]	18753	1			T3	4		T4	3		T11	2
valid_sources[0x6b]	17600	1			T2	20		T3	8		T4	9
valid_sources[0x6c]	16960	1			T3	5		T4	16		T11	1
valid_sources[0x6d]	19007	1			T2	2		T3	9		T4	7
valid_sources[0x6e]	17878	1			T3	9		T4	6		T11	2
valid_sources[0x6f]	18375	1			T3	4		T4	9		T12	7
valid_sources[0x70]	18010	1			T3	1		T4	1		T10	4
valid_sources[0x71]	22211	1			T3	4		T4	2		T12	3
valid_sources[0x72]	48807	1			T3	4		T4	5		T12	5
valid_sources[0x73]	16823	1			T3	8		T4	6		T12	3
valid_sources[0x74]	16305	1			T3	2		T4	10		T10	7
valid_sources[0x75]	26232	1			T3	7		T4	4		T12	3
valid_sources[0x76]	17961	1			T3	9		T4	8		T12	2
valid_sources[0x77]	22505	1			T3	6		T4	10		T12	5
valid_sources[0x78]	20145	1			T3	9		T4	7		T12	4
valid_sources[0x79]	78033	1			T3	13		T4	1		T12	1
valid_sources[0x7a]	16879	1			T3	4		T4	6		T12	5
valid_sources[0x7b]	18235	1			T3	5		T4	3		T12	4
valid_sources[0x7c]	18072	1			T3	4		T4	19		T12	1
valid_sources[0x7d]	53753	1			T3	4		T4	2		T12	3
valid_sources[0x7e]	18081	1			T3	3		T4	3		T12	1
valid_sources[0x7f]	16298	1			T2	5		T3	3		T4	5
valid_sources[0x80]	16793	1			T2	69		T3	8		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2565356

1

T1

1109

T2

186

T3

330

values[0x0]

all_enables

biggest_size

272658

1

T1

186

T2

97

T3

233

values[0x1]

all_enables

biggest_size

270403

1

T1

222

T2

109

T3

236