Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	183714271	14722	0	0
claim_transition_if_regwen_rd_A	183714271	650	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183714271	14722	0	0
T19	299496	12	0	0
T20	222598	0	0	0
T37	24018	0	0	0
T47	42917	0	0	0
T64	0	6	0	0
T89	0	5	0	0
T96	2501	0	0	0
T97	2154	0	0	0
T98	0	3	0	0
T108	0	4	0	0
T132	0	4	0	0
T172	0	1	0	0
T173	0	16	0	0
T174	0	4	0	0
T175	0	1	0	0
T176	30890	0	0	0
T177	8512	0	0	0
T178	36873	0	0	0
T179	5647	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183714271	650	0	0
T21	20601	0	0	0
T89	332460	2	0	0
T90	2601	0	0	0
T98	0	9	0	0
T99	0	2	0	0
T115	0	3	0	0
T180	0	8	0	0
T181	0	1	0	0
T182	0	13	0	0
T183	0	4	0	0
T184	0	13	0	0
T185	0	8	0	0
T186	30611	0	0	0
T187	22717	0	0	0
T188	6841	0	0	0
T189	55612	0	0	0
T190	3902	0	0	0
T191	467017	0	0	0
T192	7637	0	0	0