Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2925431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3346927

1

T1

707

T2

226

T3

669

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5608327	1			T1	455		T2	161		T3	582
values[0x0]	330095	1			T1	291		T2	71		T3	219
values[0x1]	333936	1			T1	309		T2	81		T3	237

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2322110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3950248

1

T1

796

T2

251

T3

748

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19483	1			T1	4		T2	1		T3	5
valid_sources[0x01]	35165	1			T1	1		T3	5		T9	7
valid_sources[0x02]	16900	1			T1	6		T3	1		T9	8
valid_sources[0x03]	16711	1			T1	4		T3	9		T9	2
valid_sources[0x04]	19065	1			T1	6		T3	15		T9	10
valid_sources[0x05]	17552	1			T1	4		T9	3		T10	7
valid_sources[0x06]	18301	1			T1	2		T2	1		T3	4
valid_sources[0x07]	17260	1			T1	8		T3	1		T9	3
valid_sources[0x08]	19226	1			T1	2		T3	4		T9	4
valid_sources[0x09]	18560	1			T1	3		T2	2		T3	3
valid_sources[0x0a]	75225	1			T1	1		T3	7		T10	7
valid_sources[0x0b]	17613	1			T1	6		T3	1		T9	4
valid_sources[0x0c]	22032	1			T1	1		T3	4		T9	2
valid_sources[0x0d]	30413	1			T1	2		T3	4		T9	7
valid_sources[0x0e]	16959	1			T1	5		T3	1		T9	6
valid_sources[0x0f]	17040	1			T1	9		T3	3		T9	3
valid_sources[0x10]	17310	1			T1	2		T2	1		T3	3
valid_sources[0x11]	16875	1			T1	2		T9	9		T10	3
valid_sources[0x12]	17991	1			T1	8		T3	4		T9	3
valid_sources[0x13]	22974	1			T1	4		T3	12		T9	1
valid_sources[0x14]	19336	1			T1	6		T9	2		T10	10
valid_sources[0x15]	18533	1			T1	5		T3	4		T10	5
valid_sources[0x16]	16907	1			T1	3		T3	4		T9	5
valid_sources[0x17]	102600	1			T1	5		T9	7		T10	8
valid_sources[0x18]	17239	1			T1	2		T3	5		T9	12
valid_sources[0x19]	17661	1			T1	5		T2	10		T3	6
valid_sources[0x1a]	31475	1			T1	2		T3	2		T9	9
valid_sources[0x1b]	17261	1			T1	3		T3	3		T9	6
valid_sources[0x1c]	55290	1			T1	1		T3	2		T9	15
valid_sources[0x1d]	16809	1			T1	7		T3	9		T9	11
valid_sources[0x1e]	17568	1			T1	4		T3	5		T9	6
valid_sources[0x1f]	17419	1			T1	6		T3	2		T9	1
valid_sources[0x20]	20496	1			T1	4		T3	4		T9	5
valid_sources[0x21]	30531	1			T1	5		T3	7		T9	5
valid_sources[0x22]	38931	1			T1	4		T3	3		T9	2
valid_sources[0x23]	17047	1			T1	5		T3	3		T9	2
valid_sources[0x24]	17673	1			T1	4		T3	1		T9	1
valid_sources[0x25]	18432	1			T1	2		T3	5		T9	1
valid_sources[0x26]	18994	1			T1	4		T3	7		T9	1
valid_sources[0x27]	29158	1			T1	5		T3	8		T9	9
valid_sources[0x28]	35469	1			T1	5		T3	7		T9	2
valid_sources[0x29]	33325	1			T1	1		T2	4		T3	6
valid_sources[0x2a]	19053	1			T1	1		T3	5		T10	5
valid_sources[0x2b]	19658	1			T1	3		T9	6		T10	4
valid_sources[0x2c]	18887	1			T1	6		T3	7		T9	14
valid_sources[0x2d]	73184	1			T1	4		T3	3		T9	3
valid_sources[0x2e]	17731	1			T1	8		T2	1		T3	6
valid_sources[0x2f]	18309	1			T1	3		T3	5		T10	4
valid_sources[0x30]	17132	1			T1	5		T3	5		T9	9
valid_sources[0x31]	17464	1			T1	3		T3	2		T9	9
valid_sources[0x32]	16923	1			T1	5		T2	3		T3	5
valid_sources[0x33]	18298	1			T1	2		T3	1		T9	8
valid_sources[0x34]	23386	1			T1	6		T3	1		T9	7
valid_sources[0x35]	17471	1			T1	3		T3	8		T9	1
valid_sources[0x36]	21664	1			T1	3		T2	6		T3	1
valid_sources[0x37]	19336	1			T1	7		T3	2		T9	10
valid_sources[0x38]	20397	1			T1	6		T3	6		T9	9
valid_sources[0x39]	17112	1			T1	3		T3	8		T9	8
valid_sources[0x3a]	77077	1			T1	5		T2	11		T3	5
valid_sources[0x3b]	24592	1			T1	4		T2	10		T3	3
valid_sources[0x3c]	18364	1			T1	3		T3	6		T9	7
valid_sources[0x3d]	17905	1			T1	7		T3	1		T9	8
valid_sources[0x3e]	19671	1			T1	3		T2	2		T3	2
valid_sources[0x3f]	17626	1			T1	2		T2	3		T3	3
valid_sources[0x40]	17689	1			T1	3		T2	10		T3	2
valid_sources[0x41]	18614	1			T1	3		T2	3		T3	5
valid_sources[0x42]	16864	1			T1	6		T3	4		T9	6
valid_sources[0x43]	43855	1			T1	3		T3	2		T9	7
valid_sources[0x44]	17217	1			T1	4		T9	4		T10	6
valid_sources[0x45]	44595	1			T1	7		T3	7		T9	5
valid_sources[0x46]	18228	1			T1	7		T3	1		T9	3
valid_sources[0x47]	19950	1			T1	5		T2	5		T3	4
valid_sources[0x48]	60392	1			T1	1		T3	9		T9	2
valid_sources[0x49]	16943	1			T1	6		T3	6		T9	4
valid_sources[0x4a]	20386	1			T1	4		T9	3		T10	7
valid_sources[0x4b]	17740	1			T1	6		T3	5		T9	9
valid_sources[0x4c]	21456	1			T1	6		T2	1		T3	2
valid_sources[0x4d]	18583	1			T1	4		T3	4		T9	5
valid_sources[0x4e]	77421	1			T1	9		T3	8		T9	8
valid_sources[0x4f]	19136	1			T1	6		T2	7		T3	8
valid_sources[0x50]	17484	1			T1	3		T2	12		T3	8
valid_sources[0x51]	38366	1			T1	4		T3	3		T9	7
valid_sources[0x52]	18018	1			T1	4		T3	2		T9	3
valid_sources[0x53]	17475	1			T1	2		T3	1		T9	2
valid_sources[0x54]	86076	1			T1	2		T3	1		T8	506
valid_sources[0x55]	17455	1			T1	8		T3	7		T9	6
valid_sources[0x56]	17443	1			T1	4		T3	4		T9	8
valid_sources[0x57]	18205	1			T1	3		T3	3		T9	10
valid_sources[0x58]	18131	1			T1	6		T3	1		T9	14
valid_sources[0x59]	21536	1			T1	1		T3	2		T10	4
valid_sources[0x5a]	27103	1			T1	7		T3	3		T9	4
valid_sources[0x5b]	20279	1			T1	4		T3	5		T9	2
valid_sources[0x5c]	18895	1			T1	4		T3	9		T9	1
valid_sources[0x5d]	18955	1			T1	6		T3	3		T9	5
valid_sources[0x5e]	18791	1			T1	4		T3	10		T9	3
valid_sources[0x5f]	16829	1			T1	6		T3	1		T9	5
valid_sources[0x60]	17615	1			T1	1		T9	3		T10	4
valid_sources[0x61]	18167	1			T1	2		T3	7		T9	1
valid_sources[0x62]	17470	1			T1	1		T3	6		T9	5
valid_sources[0x63]	18498	1			T1	1		T2	1		T3	6
valid_sources[0x64]	17318	1			T1	5		T3	8		T9	2
valid_sources[0x65]	17451	1			T1	7		T3	8		T9	1
valid_sources[0x66]	20000	1			T1	1		T9	9		T10	5
valid_sources[0x67]	18711	1			T1	4		T2	1		T3	3
valid_sources[0x68]	48802	1			T1	8		T3	9		T9	3
valid_sources[0x69]	17531	1			T1	4		T2	2		T3	3
valid_sources[0x6a]	93874	1			T1	1		T3	2		T9	11
valid_sources[0x6b]	18943	1			T1	6		T3	6		T9	12
valid_sources[0x6c]	17620	1			T1	6		T3	4		T9	1
valid_sources[0x6d]	115250	1			T1	6		T3	2		T9	1
valid_sources[0x6e]	20850	1			T1	8		T3	5		T9	6
valid_sources[0x6f]	19152	1			T1	1		T3	1		T9	1
valid_sources[0x70]	20153	1			T1	5		T3	5		T9	5
valid_sources[0x71]	20275	1			T1	3		T3	4		T9	4
valid_sources[0x72]	17216	1			T1	3		T3	7		T9	3
valid_sources[0x73]	18063	1			T1	4		T2	11		T9	1
valid_sources[0x74]	17566	1			T1	3		T3	5		T9	2
valid_sources[0x75]	17338	1			T1	5		T3	8		T9	2
valid_sources[0x76]	16966	1			T1	2		T3	3		T9	2
valid_sources[0x77]	42862	1			T1	3		T3	9		T9	4
valid_sources[0x78]	18820	1			T1	1		T9	5		T10	6
valid_sources[0x79]	17581	1			T1	3		T3	8		T9	1
valid_sources[0x7a]	18377	1			T1	4		T3	15		T9	1
valid_sources[0x7b]	17073	1			T1	5		T2	4		T3	7
valid_sources[0x7c]	17662	1			T1	4		T3	4		T9	3
valid_sources[0x7d]	19264	1			T1	5		T3	8		T9	2
valid_sources[0x7e]	17700	1			T1	1		T9	6		T10	3
valid_sources[0x7f]	17047	1			T1	3		T3	4		T9	2
valid_sources[0x80]	18818	1			T1	2		T3	7		T10	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2774635

1

T1

186

T2

91

T3

276

values[0x0]

all_enables

biggest_size

286252

1

T1

253

T2

62

T3

194

values[0x1]

all_enables

biggest_size

286040

1

T1

268

T2

73

T3

199