Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	206278454	31375	0	0
claim_transition_if_regwen_rd_A	206278454	2289	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206278454	31375	0	0
T49	291344	9	0	0
T50	0	13	0	0
T61	0	12	0	0
T64	0	8	0	0
T68	12019	0	0	0
T89	529575	0	0	0
T94	0	4	0	0
T105	0	5	0	0
T111	0	3	0	0
T182	0	1	0	0
T183	0	7	0	0
T184	0	1	0	0
T185	16533	0	0	0
T186	17558	0	0	0
T187	49012	0	0	0
T188	692705	0	0	0
T189	27239	0	0	0
T190	20235	0	0	0
T191	3857	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206278454	2289	0	0
T80	2949	0	0	0
T111	0	4	0	0
T141	0	1	0	0
T142	0	7	0	0
T182	618357	3	0	0
T184	0	17	0	0
T192	0	11	0	0
T193	0	2	0	0
T194	0	6	0	0
T195	0	17	0	0
T196	0	6	0	0
T197	23387	0	0	0
T198	1901	0	0	0
T199	22723	0	0	0
T200	975	0	0	0
T201	2511	0	0	0
T202	30856	0	0	0
T203	1279	0	0	0
T204	2116	0	0	0