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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.21 97.79 95.80 93.30 100.00 98.13 99.00 96.43


Total test records in report: 1998
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T1784 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2684093636 Mar 24 01:04:48 PM PDT 24 Mar 24 01:04:50 PM PDT 24 76328678 ps
T1785 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2576342054 Mar 24 01:04:53 PM PDT 24 Mar 24 01:04:54 PM PDT 24 60836359 ps
T145 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.859718564 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:52 PM PDT 24 168960829 ps
T1786 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3128205950 Mar 24 01:04:41 PM PDT 24 Mar 24 01:04:48 PM PDT 24 2315569008 ps
T1787 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.606611376 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:10 PM PDT 24 18372755 ps
T1788 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.830651816 Mar 24 12:42:43 PM PDT 24 Mar 24 12:42:44 PM PDT 24 36841287 ps
T1789 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.13537568 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:09 PM PDT 24 15588064 ps
T1790 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2108139200 Mar 24 01:04:58 PM PDT 24 Mar 24 01:05:13 PM PDT 24 3206764149 ps
T1791 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3825318716 Mar 24 12:42:06 PM PDT 24 Mar 24 12:42:09 PM PDT 24 115212839 ps
T1792 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3262601140 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:36 PM PDT 24 42657182 ps
T1793 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3012045909 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:41 PM PDT 24 621705535 ps
T175 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.473076271 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:17 PM PDT 24 133219353 ps
T1794 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1637028167 Mar 24 01:04:48 PM PDT 24 Mar 24 01:04:50 PM PDT 24 31767765 ps
T1795 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.716062352 Mar 24 01:04:31 PM PDT 24 Mar 24 01:04:37 PM PDT 24 400558212 ps
T1796 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.966652025 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:50 PM PDT 24 14485008524 ps
T1797 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.875631039 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:18 PM PDT 24 182607404 ps
T1798 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1388956902 Mar 24 01:04:57 PM PDT 24 Mar 24 01:05:00 PM PDT 24 165116756 ps
T1799 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1582637386 Mar 24 12:42:19 PM PDT 24 Mar 24 12:42:21 PM PDT 24 27076691 ps
T1800 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2893299141 Mar 24 01:05:10 PM PDT 24 Mar 24 01:05:12 PM PDT 24 364909706 ps
T1801 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.797713738 Mar 24 12:42:17 PM PDT 24 Mar 24 12:42:19 PM PDT 24 26835963 ps
T158 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1385384632 Mar 24 01:05:19 PM PDT 24 Mar 24 01:05:22 PM PDT 24 156932428 ps
T146 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3689306066 Mar 24 12:42:25 PM PDT 24 Mar 24 12:42:28 PM PDT 24 103800118 ps
T1802 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.108683667 Mar 24 01:04:42 PM PDT 24 Mar 24 01:04:43 PM PDT 24 47984206 ps
T1803 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1149823091 Mar 24 01:05:09 PM PDT 24 Mar 24 01:05:13 PM PDT 24 312703063 ps
T1804 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2545207637 Mar 24 12:42:18 PM PDT 24 Mar 24 12:42:34 PM PDT 24 2468653386 ps
T1805 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3566302047 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:14 PM PDT 24 1152966416 ps
T1806 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.509845279 Mar 24 01:04:46 PM PDT 24 Mar 24 01:04:47 PM PDT 24 24592429 ps
T1807 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3322167188 Mar 24 12:42:11 PM PDT 24 Mar 24 12:42:16 PM PDT 24 535706521 ps
T1808 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.881835854 Mar 24 01:05:03 PM PDT 24 Mar 24 01:05:08 PM PDT 24 120928162 ps
T1809 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3270375030 Mar 24 12:42:06 PM PDT 24 Mar 24 12:42:42 PM PDT 24 5910105869 ps
T1810 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.967435794 Mar 24 01:05:18 PM PDT 24 Mar 24 01:05:19 PM PDT 24 515947667 ps
T168 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1511792357 Mar 24 01:05:14 PM PDT 24 Mar 24 01:05:16 PM PDT 24 44799196 ps
T1811 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1889320668 Mar 24 12:42:23 PM PDT 24 Mar 24 12:42:27 PM PDT 24 501430954 ps
T1812 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2196118529 Mar 24 01:04:31 PM PDT 24 Mar 24 01:04:50 PM PDT 24 3206657181 ps
T1813 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2500967849 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 75151760 ps
T167 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.501879102 Mar 24 12:42:36 PM PDT 24 Mar 24 12:42:44 PM PDT 24 223144646 ps
T147 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1053232881 Mar 24 12:42:17 PM PDT 24 Mar 24 12:42:20 PM PDT 24 101593382 ps
T1814 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.223869652 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:36 PM PDT 24 119801197 ps
T1815 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1878184672 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:47 PM PDT 24 224171170 ps
T1816 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1038535730 Mar 24 12:42:23 PM PDT 24 Mar 24 12:42:24 PM PDT 24 26477672 ps
T1817 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1091395688 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 13548676 ps
T1818 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3144116629 Mar 24 12:42:44 PM PDT 24 Mar 24 12:42:46 PM PDT 24 185184591 ps
T243 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.756243456 Mar 24 01:04:44 PM PDT 24 Mar 24 01:04:46 PM PDT 24 16412246 ps
T1819 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1929951491 Mar 24 01:04:23 PM PDT 24 Mar 24 01:04:28 PM PDT 24 81844451 ps
T140 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2124145293 Mar 24 12:42:39 PM PDT 24 Mar 24 12:42:42 PM PDT 24 428556896 ps
T1820 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.68650851 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:34 PM PDT 24 79508667 ps
T1821 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4259912314 Mar 24 01:05:17 PM PDT 24 Mar 24 01:05:19 PM PDT 24 59592303 ps
T1822 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.131583537 Mar 24 01:04:42 PM PDT 24 Mar 24 01:04:43 PM PDT 24 27698543 ps
T1823 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2588860479 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:09 PM PDT 24 173934550 ps
T1824 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.183443244 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:09 PM PDT 24 23424353 ps
T163 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3630854509 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:11 PM PDT 24 151316809 ps
T1825 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3747067860 Mar 24 01:04:41 PM PDT 24 Mar 24 01:04:43 PM PDT 24 61239891 ps
T1826 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3976650862 Mar 24 12:42:36 PM PDT 24 Mar 24 12:42:38 PM PDT 24 27121267 ps
T1827 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2605718517 Mar 24 12:42:13 PM PDT 24 Mar 24 12:42:15 PM PDT 24 174937448 ps
T1828 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2366938521 Mar 24 01:05:08 PM PDT 24 Mar 24 01:05:10 PM PDT 24 25353922 ps
T1829 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3689140178 Mar 24 12:42:26 PM PDT 24 Mar 24 12:42:30 PM PDT 24 114221955 ps
T1830 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1780860299 Mar 24 12:42:26 PM PDT 24 Mar 24 12:42:27 PM PDT 24 24461219 ps
T245 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3665168738 Mar 24 12:42:23 PM PDT 24 Mar 24 12:42:24 PM PDT 24 224920921 ps
T246 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2700081963 Mar 24 12:42:28 PM PDT 24 Mar 24 12:42:29 PM PDT 24 42877945 ps
T174 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1209669295 Mar 24 01:04:44 PM PDT 24 Mar 24 01:04:49 PM PDT 24 569630112 ps
T1831 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2675141106 Mar 24 01:04:50 PM PDT 24 Mar 24 01:04:52 PM PDT 24 25402726 ps
T1832 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2411135282 Mar 24 12:42:18 PM PDT 24 Mar 24 12:42:19 PM PDT 24 76988326 ps
T1833 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2075033399 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:10 PM PDT 24 51605555 ps
T153 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3411145043 Mar 24 01:04:53 PM PDT 24 Mar 24 01:04:56 PM PDT 24 164933349 ps
T1834 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1337051082 Mar 24 01:04:24 PM PDT 24 Mar 24 01:04:27 PM PDT 24 29219204 ps
T1835 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.398392739 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:13 PM PDT 24 665186112 ps
T1836 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.407781008 Mar 24 01:04:30 PM PDT 24 Mar 24 01:04:32 PM PDT 24 76896237 ps
T1837 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1043119574 Mar 24 01:05:12 PM PDT 24 Mar 24 01:05:16 PM PDT 24 24643324 ps
T1838 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3014038783 Mar 24 12:42:11 PM PDT 24 Mar 24 12:42:13 PM PDT 24 177145361 ps
T1839 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1975619482 Mar 24 01:04:42 PM PDT 24 Mar 24 01:04:43 PM PDT 24 179312136 ps
T1840 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.339193269 Mar 24 12:42:05 PM PDT 24 Mar 24 12:42:07 PM PDT 24 673693057 ps
T1841 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3914834050 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 47520764 ps
T1842 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3373080067 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:09 PM PDT 24 52112574 ps
T1843 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2516499439 Mar 24 12:42:38 PM PDT 24 Mar 24 12:42:41 PM PDT 24 345851683 ps
T1844 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3085532373 Mar 24 01:04:24 PM PDT 24 Mar 24 01:04:27 PM PDT 24 61067104 ps
T1845 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2821948331 Mar 24 12:42:05 PM PDT 24 Mar 24 12:42:08 PM PDT 24 182781983 ps
T169 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1520364222 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:12 PM PDT 24 422989557 ps
T165 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.12471200 Mar 24 01:04:46 PM PDT 24 Mar 24 01:04:49 PM PDT 24 383378907 ps
T1846 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3210535977 Mar 24 12:42:29 PM PDT 24 Mar 24 12:42:30 PM PDT 24 19229229 ps
T247 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2018469383 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:36 PM PDT 24 117148436 ps
T1847 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4070202742 Mar 24 01:05:03 PM PDT 24 Mar 24 01:05:08 PM PDT 24 462819912 ps
T1848 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2639927877 Mar 24 12:42:37 PM PDT 24 Mar 24 12:42:39 PM PDT 24 357301191 ps
T1849 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3950794135 Mar 24 01:05:04 PM PDT 24 Mar 24 01:05:08 PM PDT 24 17931017 ps
T1850 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3715569542 Mar 24 01:04:53 PM PDT 24 Mar 24 01:04:54 PM PDT 24 60801663 ps
T1851 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3373215831 Mar 24 01:04:34 PM PDT 24 Mar 24 01:04:36 PM PDT 24 50362278 ps
T1852 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3054427711 Mar 24 01:05:16 PM PDT 24 Mar 24 01:05:19 PM PDT 24 51154559 ps
T1853 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.682582968 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:34 PM PDT 24 50552779 ps
T1854 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1666036119 Mar 24 12:42:12 PM PDT 24 Mar 24 12:42:17 PM PDT 24 1030217259 ps
T1855 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1984492186 Mar 24 01:04:42 PM PDT 24 Mar 24 01:04:45 PM PDT 24 276786727 ps
T1856 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2201587032 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 28364344 ps
T150 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3558307403 Mar 24 01:04:36 PM PDT 24 Mar 24 01:04:40 PM PDT 24 1098003071 ps
T1857 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2488187719 Mar 24 01:05:14 PM PDT 24 Mar 24 01:05:17 PM PDT 24 291277823 ps
T1858 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3785175182 Mar 24 12:42:42 PM PDT 24 Mar 24 12:42:48 PM PDT 24 26070440 ps
T1859 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1350704409 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:17 PM PDT 24 49541093 ps
T1860 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2358914346 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:48 PM PDT 24 33506759 ps
T1861 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3981285617 Mar 24 01:04:42 PM PDT 24 Mar 24 01:04:43 PM PDT 24 116556496 ps
T1862 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1765692472 Mar 24 01:04:44 PM PDT 24 Mar 24 01:04:47 PM PDT 24 79788181 ps
T1863 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2073891867 Mar 24 01:05:08 PM PDT 24 Mar 24 01:05:11 PM PDT 24 128920730 ps
T1864 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.838285903 Mar 24 12:42:22 PM PDT 24 Mar 24 12:42:24 PM PDT 24 51697721 ps
T1865 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.922111163 Mar 24 01:04:49 PM PDT 24 Mar 24 01:04:54 PM PDT 24 386956994 ps
T151 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3273837862 Mar 24 01:04:41 PM PDT 24 Mar 24 01:04:44 PM PDT 24 74254388 ps
T1866 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.477671118 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:12 PM PDT 24 1511944645 ps
T1867 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4011381497 Mar 24 01:04:53 PM PDT 24 Mar 24 01:04:58 PM PDT 24 178638615 ps
T1868 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4293559368 Mar 24 01:04:23 PM PDT 24 Mar 24 01:04:27 PM PDT 24 29790417 ps
T1869 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2151502284 Mar 24 01:04:47 PM PDT 24 Mar 24 01:04:50 PM PDT 24 239781890 ps
T1870 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3822707322 Mar 24 01:04:34 PM PDT 24 Mar 24 01:04:41 PM PDT 24 761145111 ps
T160 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3605874927 Mar 24 12:42:40 PM PDT 24 Mar 24 12:42:44 PM PDT 24 142348866 ps
T1871 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2473827176 Mar 24 01:04:24 PM PDT 24 Mar 24 01:04:28 PM PDT 24 205224099 ps
T1872 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2788216740 Mar 24 01:05:03 PM PDT 24 Mar 24 01:05:07 PM PDT 24 451974501 ps
T1873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2564831570 Mar 24 01:04:50 PM PDT 24 Mar 24 01:04:51 PM PDT 24 940746246 ps
T1874 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3955645877 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:39 PM PDT 24 78619176 ps
T172 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1369297734 Mar 24 12:42:29 PM PDT 24 Mar 24 12:42:32 PM PDT 24 176638115 ps
T1875 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.807991308 Mar 24 01:04:31 PM PDT 24 Mar 24 01:04:35 PM PDT 24 131125284 ps
T1876 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1514813069 Mar 24 12:42:26 PM PDT 24 Mar 24 12:42:29 PM PDT 24 1108893553 ps
T1877 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3108154114 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:08 PM PDT 24 37773264 ps
T1878 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.792261281 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:34 PM PDT 24 29492048 ps
T1879 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2198422916 Mar 24 12:42:43 PM PDT 24 Mar 24 12:42:46 PM PDT 24 528019568 ps
T1880 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.824016241 Mar 24 01:05:09 PM PDT 24 Mar 24 01:05:12 PM PDT 24 235472087 ps
T1881 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1476161860 Mar 24 01:04:24 PM PDT 24 Mar 24 01:04:27 PM PDT 24 176485355 ps
T1882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1302532941 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:11 PM PDT 24 121657575 ps
T1883 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2255408955 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:38 PM PDT 24 543522730 ps
T1884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3564666741 Mar 24 12:42:21 PM PDT 24 Mar 24 12:42:29 PM PDT 24 3236911012 ps
T1885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.417882787 Mar 24 01:05:04 PM PDT 24 Mar 24 01:05:09 PM PDT 24 295156477 ps
T1886 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.57815943 Mar 24 12:42:40 PM PDT 24 Mar 24 12:42:42 PM PDT 24 24506384 ps
T1887 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2948745823 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:10 PM PDT 24 281094073 ps
T1888 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.593641002 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:11 PM PDT 24 89329017 ps
T1889 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2906563842 Mar 24 01:04:29 PM PDT 24 Mar 24 01:04:31 PM PDT 24 981673474 ps
T1890 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2756005349 Mar 24 01:04:57 PM PDT 24 Mar 24 01:05:00 PM PDT 24 163522378 ps
T1891 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.43086870 Mar 24 01:04:43 PM PDT 24 Mar 24 01:04:47 PM PDT 24 439569770 ps
T248 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3701343176 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:09 PM PDT 24 110340459 ps
T1892 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3682944059 Mar 24 12:42:37 PM PDT 24 Mar 24 12:42:40 PM PDT 24 116444468 ps
T1893 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3635325355 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 25618990 ps
T1894 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2516749020 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:36 PM PDT 24 94316751 ps
T1895 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2107227892 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:35 PM PDT 24 149665730 ps
T1896 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.910812745 Mar 24 01:04:36 PM PDT 24 Mar 24 01:04:38 PM PDT 24 118442620 ps
T1897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1961384585 Mar 24 12:42:22 PM PDT 24 Mar 24 12:42:25 PM PDT 24 491662198 ps
T1898 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3921467497 Mar 24 12:42:24 PM PDT 24 Mar 24 12:42:25 PM PDT 24 172765116 ps
T1899 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1924933766 Mar 24 01:05:12 PM PDT 24 Mar 24 01:05:15 PM PDT 24 33461074 ps
T166 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3192911454 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:17 PM PDT 24 93334652 ps
T1900 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2951585413 Mar 24 01:05:04 PM PDT 24 Mar 24 01:05:06 PM PDT 24 465282760 ps
T1901 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2019558866 Mar 24 01:04:34 PM PDT 24 Mar 24 01:04:36 PM PDT 24 76295307 ps
T249 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1079148208 Mar 24 01:04:47 PM PDT 24 Mar 24 01:04:49 PM PDT 24 27510040 ps
T148 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.372780976 Mar 24 12:42:38 PM PDT 24 Mar 24 12:42:41 PM PDT 24 216648045 ps
T1902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.495268804 Mar 24 12:42:16 PM PDT 24 Mar 24 12:42:20 PM PDT 24 1399559708 ps
T1903 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2494605631 Mar 24 01:04:51 PM PDT 24 Mar 24 01:04:52 PM PDT 24 16445094 ps
T250 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.466375046 Mar 24 12:42:27 PM PDT 24 Mar 24 12:42:28 PM PDT 24 31684420 ps
T1904 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1072740228 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:08 PM PDT 24 27461677 ps
T1905 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.364363762 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:36 PM PDT 24 103623269 ps
T1906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2834105792 Mar 24 01:04:48 PM PDT 24 Mar 24 01:04:51 PM PDT 24 131281972 ps
T1907 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.745461166 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 97217423 ps
T1908 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3565018340 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:09 PM PDT 24 426302452 ps
T1909 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2411509633 Mar 24 01:04:30 PM PDT 24 Mar 24 01:04:31 PM PDT 24 302329765 ps
T1910 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1018975843 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:36 PM PDT 24 39704958 ps
T1911 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2962103638 Mar 24 12:42:05 PM PDT 24 Mar 24 12:42:07 PM PDT 24 23885966 ps
T1912 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1574099056 Mar 24 12:42:31 PM PDT 24 Mar 24 12:42:34 PM PDT 24 156976503 ps
T1913 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.55337200 Mar 24 01:05:16 PM PDT 24 Mar 24 01:05:19 PM PDT 24 83285474 ps
T1914 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1211042499 Mar 24 12:42:12 PM PDT 24 Mar 24 12:42:22 PM PDT 24 802966665 ps
T1915 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3371749814 Mar 24 12:42:15 PM PDT 24 Mar 24 12:42:18 PM PDT 24 77403724 ps
T1916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2448683635 Mar 24 12:42:15 PM PDT 24 Mar 24 12:42:17 PM PDT 24 49039160 ps
T251 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1712182603 Mar 24 12:42:05 PM PDT 24 Mar 24 12:42:07 PM PDT 24 209628473 ps
T1917 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.125372607 Mar 24 01:05:05 PM PDT 24 Mar 24 01:05:10 PM PDT 24 350172399 ps
T1918 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3626006552 Mar 24 01:04:35 PM PDT 24 Mar 24 01:04:37 PM PDT 24 93730645 ps
T1919 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2794147746 Mar 24 01:04:52 PM PDT 24 Mar 24 01:05:04 PM PDT 24 5743060774 ps
T154 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2294102769 Mar 24 12:42:06 PM PDT 24 Mar 24 12:42:09 PM PDT 24 240550805 ps
T1920 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2714531534 Mar 24 12:42:15 PM PDT 24 Mar 24 12:42:19 PM PDT 24 188835651 ps
T1921 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.56549289 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:34 PM PDT 24 30614690 ps
T1922 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2627028809 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:08 PM PDT 24 97363957 ps
T1923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.323855116 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:14 PM PDT 24 741206951 ps
T1924 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.593069708 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:42 PM PDT 24 248327925 ps
T1925 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2573630556 Mar 24 12:42:26 PM PDT 24 Mar 24 12:42:27 PM PDT 24 19372808 ps
T1926 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1773450720 Mar 24 01:04:30 PM PDT 24 Mar 24 01:04:31 PM PDT 24 14068658 ps
T1927 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1343830387 Mar 24 01:04:53 PM PDT 24 Mar 24 01:04:55 PM PDT 24 114345315 ps
T1928 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.93257848 Mar 24 12:42:17 PM PDT 24 Mar 24 12:42:19 PM PDT 24 37124649 ps
T1929 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1419446436 Mar 24 01:04:26 PM PDT 24 Mar 24 01:04:28 PM PDT 24 44738485 ps
T1930 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4019992611 Mar 24 01:05:05 PM PDT 24 Mar 24 01:05:21 PM PDT 24 572757038 ps
T173 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.801764624 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:11 PM PDT 24 195139296 ps
T244 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.261325199 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:33 PM PDT 24 13026382 ps
T1931 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.922587536 Mar 24 12:42:06 PM PDT 24 Mar 24 12:42:08 PM PDT 24 27322700 ps
T1932 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1379846233 Mar 24 12:42:05 PM PDT 24 Mar 24 12:42:06 PM PDT 24 75840612 ps
T252 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2463741421 Mar 24 01:05:08 PM PDT 24 Mar 24 01:05:10 PM PDT 24 46968940 ps
T1933 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3624955624 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:10 PM PDT 24 82537783 ps
T1934 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.960861565 Mar 24 12:42:16 PM PDT 24 Mar 24 12:42:17 PM PDT 24 25516664 ps
T1935 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3753324400 Mar 24 12:42:29 PM PDT 24 Mar 24 12:42:30 PM PDT 24 19094966 ps
T1936 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1741648064 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:16 PM PDT 24 19347502 ps
T1937 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3404276077 Mar 24 12:42:23 PM PDT 24 Mar 24 12:42:24 PM PDT 24 15075233 ps
T1938 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2766188673 Mar 24 01:04:34 PM PDT 24 Mar 24 01:04:37 PM PDT 24 3557391560 ps
T253 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1808342548 Mar 24 01:04:34 PM PDT 24 Mar 24 01:04:36 PM PDT 24 329015684 ps
T1939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2919152323 Mar 24 01:04:36 PM PDT 24 Mar 24 01:04:42 PM PDT 24 1481938377 ps
T1940 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2312552585 Mar 24 01:04:26 PM PDT 24 Mar 24 01:04:41 PM PDT 24 544384194 ps
T1941 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3554522097 Mar 24 01:05:00 PM PDT 24 Mar 24 01:05:04 PM PDT 24 226323893 ps
T1942 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1434322455 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:36 PM PDT 24 18733093 ps
T1943 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1493498476 Mar 24 01:05:08 PM PDT 24 Mar 24 01:05:11 PM PDT 24 20904355 ps
T1944 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4039318407 Mar 24 01:05:03 PM PDT 24 Mar 24 01:05:07 PM PDT 24 207754902 ps
T1945 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3404271135 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:10 PM PDT 24 21518359 ps
T1946 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.940774482 Mar 24 01:04:49 PM PDT 24 Mar 24 01:04:51 PM PDT 24 24182170 ps
T1947 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.520516878 Mar 24 01:05:00 PM PDT 24 Mar 24 01:05:02 PM PDT 24 20581882 ps
T1948 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3021785749 Mar 24 01:04:41 PM PDT 24 Mar 24 01:04:43 PM PDT 24 690704309 ps
T170 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3005838791 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:44 PM PDT 24 75080231 ps
T1949 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1656226934 Mar 24 12:42:28 PM PDT 24 Mar 24 12:42:29 PM PDT 24 50140842 ps
T1950 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1103614817 Mar 24 01:04:36 PM PDT 24 Mar 24 01:04:45 PM PDT 24 5759177239 ps
T1951 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.167479070 Mar 24 12:42:16 PM PDT 24 Mar 24 12:42:17 PM PDT 24 45366750 ps
T1952 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2851977832 Mar 24 01:04:30 PM PDT 24 Mar 24 01:04:31 PM PDT 24 16913235 ps
T1953 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2202987457 Mar 24 01:04:44 PM PDT 24 Mar 24 01:04:46 PM PDT 24 218452516 ps
T1954 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3529190 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:09 PM PDT 24 16800890 ps
T1955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.676159409 Mar 24 12:42:15 PM PDT 24 Mar 24 12:42:16 PM PDT 24 12690688 ps
T1956 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1687701078 Mar 24 12:42:29 PM PDT 24 Mar 24 12:42:31 PM PDT 24 22399253 ps
T1957 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3413113840 Mar 24 01:05:03 PM PDT 24 Mar 24 01:05:07 PM PDT 24 111567108 ps
T1958 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4134091707 Mar 24 01:04:42 PM PDT 24 Mar 24 01:04:46 PM PDT 24 632067823 ps
T1959 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.403784597 Mar 24 12:42:54 PM PDT 24 Mar 24 12:42:55 PM PDT 24 44015970 ps
T1960 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2575333335 Mar 24 01:05:06 PM PDT 24 Mar 24 01:05:09 PM PDT 24 19147688 ps
T1961 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3976640230 Mar 24 01:04:24 PM PDT 24 Mar 24 01:04:26 PM PDT 24 88708350 ps
T1962 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2176039515 Mar 24 01:04:34 PM PDT 24 Mar 24 01:04:58 PM PDT 24 1008324199 ps
T1963 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3019265742 Mar 24 01:05:17 PM PDT 24 Mar 24 01:05:21 PM PDT 24 44777408 ps
T1964 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3127266845 Mar 24 01:05:08 PM PDT 24 Mar 24 01:05:10 PM PDT 24 12913911 ps
T1965 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3497247314 Mar 24 12:42:04 PM PDT 24 Mar 24 12:42:05 PM PDT 24 268225834 ps
T1966 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2367076840 Mar 24 01:04:52 PM PDT 24 Mar 24 01:04:53 PM PDT 24 37300653 ps
T1967 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1380184421 Mar 24 01:04:54 PM PDT 24 Mar 24 01:04:57 PM PDT 24 223748180 ps
T1968 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.700901813 Mar 24 12:42:25 PM PDT 24 Mar 24 12:42:27 PM PDT 24 28950595 ps
T1969 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.5188184 Mar 24 12:42:08 PM PDT 24 Mar 24 12:42:09 PM PDT 24 31827522 ps
T1970 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2666918605 Mar 24 01:05:02 PM PDT 24 Mar 24 01:05:04 PM PDT 24 29612524 ps
T1971 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4284608276 Mar 24 01:04:41 PM PDT 24 Mar 24 01:04:42 PM PDT 24 26801456 ps
T1972 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.619983512 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:37 PM PDT 24 62924317 ps
T1973 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3325577503 Mar 24 12:42:29 PM PDT 24 Mar 24 12:42:31 PM PDT 24 27689048 ps
T1974 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3673353099 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:39 PM PDT 24 4851491996 ps
T1975 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3751911466 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:37 PM PDT 24 521782257 ps
T1976 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3557880910 Mar 24 12:42:10 PM PDT 24 Mar 24 12:42:12 PM PDT 24 324360801 ps
T1977 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1584899265 Mar 24 01:04:37 PM PDT 24 Mar 24 01:04:38 PM PDT 24 164824386 ps
T1978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.237293643 Mar 24 01:05:07 PM PDT 24 Mar 24 01:05:12 PM PDT 24 91698073 ps
T1979 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3622556074 Mar 24 12:42:36 PM PDT 24 Mar 24 12:42:40 PM PDT 24 205972276 ps
T1980 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3537360142 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:16 PM PDT 24 99586920 ps
T1981 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1000764932 Mar 24 01:05:15 PM PDT 24 Mar 24 01:05:18 PM PDT 24 15841700 ps
T1982 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1648411065 Mar 24 12:42:34 PM PDT 24 Mar 24 12:42:37 PM PDT 24 79928225 ps
T1983 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1940264381 Mar 24 12:42:19 PM PDT 24 Mar 24 12:42:21 PM PDT 24 29412432 ps
T1984 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1174872109 Mar 24 12:42:42 PM PDT 24 Mar 24 12:42:43 PM PDT 24 73827867 ps
T1985 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3793591830 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:15 PM PDT 24 85037564 ps
T1986 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2784952995 Mar 24 01:04:56 PM PDT 24 Mar 24 01:05:00 PM PDT 24 292838878 ps
T1987 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2784914407 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:34 PM PDT 24 29813678 ps
T1988 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4099974206 Mar 24 01:04:46 PM PDT 24 Mar 24 01:04:52 PM PDT 24 1092726032 ps
T1989 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3819736322 Mar 24 01:05:13 PM PDT 24 Mar 24 01:05:16 PM PDT 24 34899899 ps
T1990 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1768974847 Mar 24 12:42:24 PM PDT 24 Mar 24 12:42:26 PM PDT 24 505546760 ps
T1991 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2424647923 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:42 PM PDT 24 34173183 ps
T1992 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3522466930 Mar 24 01:05:03 PM PDT 24 Mar 24 01:05:11 PM PDT 24 613503882 ps
T1993 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.219845591 Mar 24 01:04:29 PM PDT 24 Mar 24 01:04:33 PM PDT 24 40430957 ps
T1994 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1077925938 Mar 24 01:05:08 PM PDT 24 Mar 24 01:05:12 PM PDT 24 27405255 ps
T1995 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4013915357 Mar 24 01:05:05 PM PDT 24 Mar 24 01:05:09 PM PDT 24 52091392 ps
T1996 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2225861218 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:11 PM PDT 24 93930366 ps
T1997 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3019238273 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:34 PM PDT 24 195670647 ps
T1998 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.896916150 Mar 24 12:42:20 PM PDT 24 Mar 24 12:42:22 PM PDT 24 726130094 ps

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1296949862
Short name T9
Test name
Test status
Simulation time 1513660685 ps
CPU time 16.21 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:57:02 PM PDT 24
Peak memory 219540 kb
Host smart-46c26d63-fe3c-48a6-a021-43819639675c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296949862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1296949862
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3551415630
Short name T19
Test name
Test status
Simulation time 14282854331 ps
CPU time 452.93 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 02:05:00 PM PDT 24
Peak memory 226716 kb
Host smart-c975ff98-5d3b-4b4c-8a08-3740b49b94fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551415630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3551415630
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2334956996
Short name T54
Test name
Test status
Simulation time 1440803360 ps
CPU time 14.26 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 226440 kb
Host smart-cbf68acb-5903-4f19-9c7e-8e99eb58105c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334956996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2334956996
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3558140074
Short name T24
Test name
Test status
Simulation time 370775332 ps
CPU time 7.69 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 01:57:33 PM PDT 24
Peak memory 243212 kb
Host smart-e473ada4-fc7a-4e4c-bb0c-ceca9a618355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558140074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3558140074
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.978369445
Short name T50
Test name
Test status
Simulation time 18220337754 ps
CPU time 539.98 seconds
Started Mar 24 01:55:01 PM PDT 24
Finished Mar 24 02:04:01 PM PDT 24
Peak memory 422700 kb
Host smart-de2f693c-31d9-4f79-b104-6bff1d31e693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=978369445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.978369445
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.4111020192
Short name T129
Test name
Test status
Simulation time 88152808 ps
CPU time 2.74 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 218712 kb
Host smart-89edb098-5893-4252-b569-92a24bc49797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111020192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.4111020192
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2797222584
Short name T67
Test name
Test status
Simulation time 3630249427 ps
CPU time 93.42 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:59:02 PM PDT 24
Peak memory 269028 kb
Host smart-a1d2a459-12aa-475b-936f-7bbbb6a197bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797222584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2797222584
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3474767988
Short name T1
Test name
Test status
Simulation time 987691593 ps
CPU time 7.94 seconds
Started Mar 24 01:56:56 PM PDT 24
Finished Mar 24 01:57:04 PM PDT 24
Peak memory 218660 kb
Host smart-dfb9f38e-8b4d-449b-8c30-85dbcf117dd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474767988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3474767988
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.3252754577
Short name T57
Test name
Test status
Simulation time 1123506227 ps
CPU time 24 seconds
Started Mar 24 02:34:42 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 268856 kb
Host smart-115539f9-e4f6-4764-8dcd-bf569972da01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252754577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3252754577
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3218520724
Short name T25
Test name
Test status
Simulation time 322184490 ps
CPU time 12.11 seconds
Started Mar 24 02:35:22 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 226076 kb
Host smart-2421ac79-4a53-4a1f-a75b-5d3fb425fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218520724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3218520724
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1680888492
Short name T42
Test name
Test status
Simulation time 1247633897 ps
CPU time 24.87 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:36:33 PM PDT 24
Peak memory 235160 kb
Host smart-2d58a698-8f6e-49be-ba7e-bc225266dd1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680888492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1680888492
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.604487193
Short name T131
Test name
Test status
Simulation time 171660328 ps
CPU time 3.04 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 222416 kb
Host smart-90432b2b-20b2-4f8b-8be2-80484db29427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604487193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.604487193
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.668981573
Short name T38
Test name
Test status
Simulation time 26999596 ps
CPU time 0.96 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 209072 kb
Host smart-35194787-59b8-43a4-a32b-6c058bf70bd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668981573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.668981573
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2292689957
Short name T205
Test name
Test status
Simulation time 42257557701 ps
CPU time 205.81 seconds
Started Mar 24 01:55:34 PM PDT 24
Finished Mar 24 01:59:00 PM PDT 24
Peak memory 282268 kb
Host smart-124f5729-2a97-4afc-ba79-4f171b88642d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2292689957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2292689957
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.201185398
Short name T6
Test name
Test status
Simulation time 1173022001 ps
CPU time 8.65 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:56:38 PM PDT 24
Peak memory 217528 kb
Host smart-8bd34546-62fd-4ff3-bcac-2d8f44a51ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201185398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.201185398
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.581594476
Short name T12
Test name
Test status
Simulation time 53973190 ps
CPU time 1.07 seconds
Started Mar 24 01:57:31 PM PDT 24
Finished Mar 24 01:57:32 PM PDT 24
Peak memory 209872 kb
Host smart-d9774ffc-36b9-4cf3-bc25-c11c52222213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581594476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.581594476
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2812739770
Short name T138
Test name
Test status
Simulation time 442074608 ps
CPU time 2.98 seconds
Started Mar 24 01:04:31 PM PDT 24
Finished Mar 24 01:04:35 PM PDT 24
Peak memory 217732 kb
Host smart-9b70dac3-be01-43c0-9c69-de5a179427a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281273
9770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2812739770
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.980416739
Short name T238
Test name
Test status
Simulation time 54233405 ps
CPU time 0.96 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:26 PM PDT 24
Peak memory 209384 kb
Host smart-39711ce5-bead-4c3d-9717-06852b1687e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980416739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.980416739
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1287320239
Short name T159
Test name
Test status
Simulation time 143713729 ps
CPU time 3.45 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:19 PM PDT 24
Peak memory 221804 kb
Host smart-e5e95156-4b68-4e3d-9be8-5ee5bd498e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287320239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1287320239
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.475020894
Short name T55
Test name
Test status
Simulation time 1000611082 ps
CPU time 7.14 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:55:53 PM PDT 24
Peak memory 225276 kb
Host smart-dcf5ecff-2b0c-4717-b9d2-aa9632eb1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475020894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.475020894
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1890535895
Short name T293
Test name
Test status
Simulation time 1156407331 ps
CPU time 29.83 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:51 PM PDT 24
Peak memory 251420 kb
Host smart-7a114c73-11f5-4b7c-af48-fe2cab986ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890535895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1890535895
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.900707435
Short name T111
Test name
Test status
Simulation time 207562240916 ps
CPU time 3829.96 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 02:59:23 PM PDT 24
Peak memory 1005360 kb
Host smart-9af7ab28-d922-4041-94bd-d5e32bbfabd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=900707435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.900707435
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.501879102
Short name T167
Test name
Test status
Simulation time 223144646 ps
CPU time 3.62 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 222304 kb
Host smart-86c051f4-874a-42e8-8048-360a6faa096d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501879102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.501879102
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2156820983
Short name T10
Test name
Test status
Simulation time 958154446 ps
CPU time 10.16 seconds
Started Mar 24 02:36:49 PM PDT 24
Finished Mar 24 02:37:01 PM PDT 24
Peak memory 218576 kb
Host smart-ca37bee7-2f7a-43e6-9d7b-5d7cb3788a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156820983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2156820983
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2837497039
Short name T683
Test name
Test status
Simulation time 402696753520 ps
CPU time 648.6 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:45:41 PM PDT 24
Peak memory 317404 kb
Host smart-8d3c7166-078b-469b-bdd9-e3a60b8eeec6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2837497039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2837497039
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2103189298
Short name T157
Test name
Test status
Simulation time 312524307 ps
CPU time 2.09 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 221904 kb
Host smart-8fcda9d2-5c02-4518-8027-7bdcb321a879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103189298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2103189298
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.420156133
Short name T155
Test name
Test status
Simulation time 210236791 ps
CPU time 3.19 seconds
Started Mar 24 01:04:31 PM PDT 24
Finished Mar 24 01:04:35 PM PDT 24
Peak memory 222352 kb
Host smart-4780814b-57a3-451c-a017-5830778a3d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420156133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.420156133
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3273837862
Short name T151
Test name
Test status
Simulation time 74254388 ps
CPU time 2.62 seconds
Started Mar 24 01:04:41 PM PDT 24
Finished Mar 24 01:04:44 PM PDT 24
Peak memory 222052 kb
Host smart-2b3522e7-8419-449f-89e1-895440c4c42c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273837862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3273837862
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2140894084
Short name T255
Test name
Test status
Simulation time 63765711 ps
CPU time 1.01 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:18 PM PDT 24
Peak memory 209360 kb
Host smart-78f61662-4fed-45ca-8023-f58a74fe97e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140894084 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2140894084
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.416051003
Short name T94
Test name
Test status
Simulation time 145167382599 ps
CPU time 1144.04 seconds
Started Mar 24 02:35:30 PM PDT 24
Finished Mar 24 02:54:35 PM PDT 24
Peak memory 387268 kb
Host smart-1ff21dde-b790-4bef-b229-77e2dc70c610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=416051003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.416051003
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2865538281
Short name T105
Test name
Test status
Simulation time 17420543619 ps
CPU time 424.42 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 02:02:03 PM PDT 24
Peak memory 513672 kb
Host smart-6f23a66c-6839-4b51-aad3-a379bb6e6a54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2865538281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2865538281
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.155429319
Short name T134
Test name
Test status
Simulation time 47594283 ps
CPU time 3.58 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 217700 kb
Host smart-ec27d883-7415-4ae7-9123-8fd3156989f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155429319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.155429319
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3005838791
Short name T170
Test name
Test status
Simulation time 75080231 ps
CPU time 3.31 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 222052 kb
Host smart-1e0b321d-6e7f-4a06-85e2-1f0b8505ec89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005838791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3005838791
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3411145043
Short name T153
Test name
Test status
Simulation time 164933349 ps
CPU time 2.34 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:56 PM PDT 24
Peak memory 222012 kb
Host smart-4de1edb1-f041-4ca9-adf2-03d9f8c1d7ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411145043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3411145043
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.372780976
Short name T148
Test name
Test status
Simulation time 216648045 ps
CPU time 2.89 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 222056 kb
Host smart-58677656-c202-4368-9910-144d72353cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372780976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.372780976
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1235231918
Short name T263
Test name
Test status
Simulation time 10918505 ps
CPU time 0.96 seconds
Started Mar 24 01:54:36 PM PDT 24
Finished Mar 24 01:54:37 PM PDT 24
Peak memory 210024 kb
Host smart-e1dd08e5-23aa-4ffb-96f2-dc66d40b5300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235231918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1235231918
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2315126106
Short name T268
Test name
Test status
Simulation time 21557591 ps
CPU time 0.91 seconds
Started Mar 24 02:34:43 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 210012 kb
Host smart-8248ac20-d4d3-43c6-a2ef-4ff55a281b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315126106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2315126106
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2268708188
Short name T264
Test name
Test status
Simulation time 17120334 ps
CPU time 0.8 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 209864 kb
Host smart-ef0e6f76-4d63-495c-a10a-a16c63fbcbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268708188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2268708188
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2191149539
Short name T271
Test name
Test status
Simulation time 11181682 ps
CPU time 0.89 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 209876 kb
Host smart-64de7072-2623-4987-ace4-96cb733d2a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191149539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2191149539
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1964290008
Short name T269
Test name
Test status
Simulation time 30582060 ps
CPU time 0.82 seconds
Started Mar 24 01:55:00 PM PDT 24
Finished Mar 24 01:55:01 PM PDT 24
Peak memory 209872 kb
Host smart-adbc63ab-7395-4c7f-aeb4-ea8e1e18a25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964290008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1964290008
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2708459297
Short name T37
Test name
Test status
Simulation time 229689736 ps
CPU time 8.89 seconds
Started Mar 24 01:56:34 PM PDT 24
Finished Mar 24 01:56:43 PM PDT 24
Peak memory 226648 kb
Host smart-75f1a55e-ce39-4181-86cf-5c9127c5c356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708459297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2708459297
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2124145293
Short name T140
Test name
Test status
Simulation time 428556896 ps
CPU time 3.1 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 222308 kb
Host smart-00e91cfa-b945-44b5-a304-b5d34150c92c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124145293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2124145293
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.859718564
Short name T145
Test name
Test status
Simulation time 168960829 ps
CPU time 2.26 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 217564 kb
Host smart-2e7ebdcf-d3ae-4b91-81b7-38ab2e873e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859718564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.859718564
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2046744397
Short name T52
Test name
Test status
Simulation time 58609667965 ps
CPU time 118.34 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 276808 kb
Host smart-b08b962d-94de-43b0-9237-f66945cc33a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046744397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2046744397
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1821569690
Short name T51
Test name
Test status
Simulation time 1211027953 ps
CPU time 23.39 seconds
Started Mar 24 01:56:07 PM PDT 24
Finished Mar 24 01:56:31 PM PDT 24
Peak memory 218540 kb
Host smart-9d536051-1754-464a-b0d3-bc3792869fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821569690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1821569690
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3198858958
Short name T70
Test name
Test status
Simulation time 40940212 ps
CPU time 1.68 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:01 PM PDT 24
Peak memory 214324 kb
Host smart-2fdde1ae-a97f-4578-81a0-20e7da0b9454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198858958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3198858958
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1419446436
Short name T1929
Test name
Test status
Simulation time 44738485 ps
CPU time 1.05 seconds
Started Mar 24 01:04:26 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 209408 kb
Host smart-41545864-b65b-461d-98cd-2fdcf166f379
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419446436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1419446436
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.183443244
Short name T1824
Test name
Test status
Simulation time 23424353 ps
CPU time 1.35 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 208800 kb
Host smart-5a9ae626-7927-4bb5-b542-c9dee2178f7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183443244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.183443244
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1929951491
Short name T1819
Test name
Test status
Simulation time 81844451 ps
CPU time 2.91 seconds
Started Mar 24 01:04:23 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 208604 kb
Host smart-64eb5887-808d-43bf-85a4-4fe5dbb9aa0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929951491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1929951491
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.5188184
Short name T1969
Test name
Test status
Simulation time 31827522 ps
CPU time 1.14 seconds
Started Mar 24 12:42:08 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 208004 kb
Host smart-383d6c1b-b933-4c07-906b-6e33deb6c40b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5188184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash.5188184
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2529973528
Short name T1735
Test name
Test status
Simulation time 15265577 ps
CPU time 1.1 seconds
Started Mar 24 12:42:10 PM PDT 24
Finished Mar 24 12:42:11 PM PDT 24
Peak memory 209708 kb
Host smart-3bee5550-b0ab-4020-a9a8-157b4897c5b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529973528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2529973528
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.534534699
Short name T1764
Test name
Test status
Simulation time 29456798 ps
CPU time 1.12 seconds
Started Mar 24 01:04:26 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 211732 kb
Host smart-6a401dda-1a16-4b3e-8aeb-fb73cea9e90b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534534699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.534534699
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.57815943
Short name T1886
Test name
Test status
Simulation time 24506384 ps
CPU time 1.49 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 217848 kb
Host smart-cfaa8ba1-e229-4ae0-b277-49d0a82a0816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57815943 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.57815943
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.744029474
Short name T1746
Test name
Test status
Simulation time 458835562 ps
CPU time 2.32 seconds
Started Mar 24 01:04:29 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 218780 kb
Host smart-82d19e91-9525-45af-a6a2-31fcb5bc24c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744029474 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.744029474
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3404276077
Short name T1937
Test name
Test status
Simulation time 15075233 ps
CPU time 0.97 seconds
Started Mar 24 12:42:23 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 208988 kb
Host smart-cfa05bed-ba7d-40e6-baab-c3eb69c2533e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404276077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3404276077
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1283934850
Short name T1754
Test name
Test status
Simulation time 89654980 ps
CPU time 1.17 seconds
Started Mar 24 12:42:19 PM PDT 24
Finished Mar 24 12:42:20 PM PDT 24
Peak memory 207916 kb
Host smart-c6b1cf87-d657-4dc2-9846-e47bb5a2edca
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283934850 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1283934850
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3976640230
Short name T1961
Test name
Test status
Simulation time 88708350 ps
CPU time 1.13 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:26 PM PDT 24
Peak memory 208036 kb
Host smart-c83c0b7b-a7bb-4246-a9b9-5731216525ae
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976640230 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3976640230
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1163850547
Short name T1717
Test name
Test status
Simulation time 499708209 ps
CPU time 5.23 seconds
Started Mar 24 01:04:23 PM PDT 24
Finished Mar 24 01:04:30 PM PDT 24
Peak memory 208536 kb
Host smart-4f199b5d-409b-4097-bdb5-af32f535737b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163850547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1163850547
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.961071670
Short name T1777
Test name
Test status
Simulation time 260598892 ps
CPU time 3.56 seconds
Started Mar 24 12:42:12 PM PDT 24
Finished Mar 24 12:42:16 PM PDT 24
Peak memory 209032 kb
Host smart-91396c3f-d49d-41a6-b305-a5bdb410ea7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961071670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.961071670
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2312552585
Short name T1940
Test name
Test status
Simulation time 544384194 ps
CPU time 13.54 seconds
Started Mar 24 01:04:26 PM PDT 24
Finished Mar 24 01:04:41 PM PDT 24
Peak memory 208160 kb
Host smart-b9f6609b-d7fa-465d-88d3-d469fb901423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312552585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2312552585
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3270375030
Short name T1809
Test name
Test status
Simulation time 5910105869 ps
CPU time 35.46 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 209292 kb
Host smart-4d9614c2-f0ce-4060-8ff1-6113684bdffc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270375030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3270375030
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1302532941
Short name T1882
Test name
Test status
Simulation time 121657575 ps
CPU time 3.38 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:11 PM PDT 24
Peak memory 210656 kb
Host smart-0be37b91-044f-4e1c-a981-9c7ae6ac3062
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302532941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1302532941
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.405407251
Short name T1740
Test name
Test status
Simulation time 257415720 ps
CPU time 1.45 seconds
Started Mar 24 01:04:20 PM PDT 24
Finished Mar 24 01:04:22 PM PDT 24
Peak memory 210808 kb
Host smart-70e7cd03-015a-438a-97ad-ac88244f7a1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405407251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.405407251
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1334642534
Short name T1716
Test name
Test status
Simulation time 1014133457 ps
CPU time 3.13 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 218756 kb
Host smart-7f093605-1274-457e-8004-998a321cc297
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133464
2534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1334642534
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.323855116
Short name T1923
Test name
Test status
Simulation time 741206951 ps
CPU time 4.84 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:14 PM PDT 24
Peak memory 218204 kb
Host smart-1827f59d-3e18-494f-8837-945c17ffcd31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323855
116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.323855116
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2473827176
Short name T1871
Test name
Test status
Simulation time 205224099 ps
CPU time 3.01 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 209360 kb
Host smart-56f80cea-c53a-4b58-adbc-c38bf0330966
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473827176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2473827176
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3497247314
Short name T1965
Test name
Test status
Simulation time 268225834 ps
CPU time 1.53 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 209332 kb
Host smart-65d87b9b-7ebe-40f1-9840-041b35a1dab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497247314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3497247314
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1337051082
Short name T1834
Test name
Test status
Simulation time 29219204 ps
CPU time 1.59 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 209500 kb
Host smart-bca8d7b1-e575-4ab4-9d10-f280021078cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337051082 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1337051082
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2588860479
Short name T1823
Test name
Test status
Simulation time 173934550 ps
CPU time 2.08 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 217560 kb
Host smart-482f2cc5-a124-4e29-91b4-1af1d91e3365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588860479 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2588860479
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1476161860
Short name T1881
Test name
Test status
Simulation time 176485355 ps
CPU time 1.43 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 211520 kb
Host smart-d87238c3-f3a0-476c-9ae6-6fe71e7c1b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476161860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1476161860
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2411135282
Short name T1832
Test name
Test status
Simulation time 76988326 ps
CPU time 1.14 seconds
Started Mar 24 12:42:18 PM PDT 24
Finished Mar 24 12:42:19 PM PDT 24
Peak memory 209500 kb
Host smart-f3235997-4711-4ae1-ba08-a50dcf04d92c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411135282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2411135282
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2962103638
Short name T1911
Test name
Test status
Simulation time 23885966 ps
CPU time 1.82 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 217676 kb
Host smart-c369109e-b766-48a2-af7f-0b61939ff380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962103638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2962103638
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4293559368
Short name T1868
Test name
Test status
Simulation time 29790417 ps
CPU time 1.86 seconds
Started Mar 24 01:04:23 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 218896 kb
Host smart-43c3e158-74be-495f-b97f-1dbdf5d9f69b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293559368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.4293559368
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3085532373
Short name T1844
Test name
Test status
Simulation time 61067104 ps
CPU time 2.12 seconds
Started Mar 24 01:04:24 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 221880 kb
Host smart-25d33d8a-5b2d-4338-a4f8-95e213c5a6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085532373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3085532373
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2830110646
Short name T240
Test name
Test status
Simulation time 47837986 ps
CPU time 1.06 seconds
Started Mar 24 01:04:27 PM PDT 24
Finished Mar 24 01:04:30 PM PDT 24
Peak memory 209296 kb
Host smart-f1c3bd77-c821-45b1-9b89-0f13c961acc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830110646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2830110646
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.922587536
Short name T1931
Test name
Test status
Simulation time 27322700 ps
CPU time 1.34 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 209260 kb
Host smart-304bd07c-e306-4f6a-97de-0ae67f70341a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922587536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.922587536
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2411509633
Short name T1909
Test name
Test status
Simulation time 302329765 ps
CPU time 1.27 seconds
Started Mar 24 01:04:30 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 207908 kb
Host smart-190985ea-cb75-41b9-a095-70442b6d4f69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411509633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2411509633
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3014038783
Short name T1838
Test name
Test status
Simulation time 177145361 ps
CPU time 1.87 seconds
Started Mar 24 12:42:11 PM PDT 24
Finished Mar 24 12:42:13 PM PDT 24
Peak memory 208452 kb
Host smart-56dbead3-3e22-4bdd-a352-1e6250ae6f60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014038783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3014038783
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1773450720
Short name T1926
Test name
Test status
Simulation time 14068658 ps
CPU time 1.1 seconds
Started Mar 24 01:04:30 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 209996 kb
Host smart-6be02b9d-3cb9-4179-b7ba-6497218a549d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773450720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1773450720
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3207769448
Short name T241
Test name
Test status
Simulation time 30244433 ps
CPU time 0.94 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:17 PM PDT 24
Peak memory 209756 kb
Host smart-275b5ded-35c6-44c7-87b6-2879242070c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207769448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3207769448
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.593641002
Short name T1888
Test name
Test status
Simulation time 89329017 ps
CPU time 1.64 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:11 PM PDT 24
Peak memory 217632 kb
Host smart-7131a348-2a2e-4afc-a885-e2d573b0e0fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593641002 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.593641002
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.732366425
Short name T1727
Test name
Test status
Simulation time 62288271 ps
CPU time 1.44 seconds
Started Mar 24 01:04:29 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 217732 kb
Host smart-66d20923-f64c-4353-a083-f2a53f4116ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732366425 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.732366425
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2851977832
Short name T1952
Test name
Test status
Simulation time 16913235 ps
CPU time 0.94 seconds
Started Mar 24 01:04:30 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 209124 kb
Host smart-b4877704-403f-4bd4-8ca4-663779c46b5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851977832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2851977832
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3210535977
Short name T1846
Test name
Test status
Simulation time 19229229 ps
CPU time 0.93 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:30 PM PDT 24
Peak memory 209088 kb
Host smart-86d2c07a-66a6-4ffd-a2e0-e87323b016b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210535977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3210535977
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2627028809
Short name T1922
Test name
Test status
Simulation time 97363957 ps
CPU time 1 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 207912 kb
Host smart-7619cec2-a7be-4f17-8e2d-7ea10794941f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627028809 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2627028809
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.407781008
Short name T1836
Test name
Test status
Simulation time 76896237 ps
CPU time 2.39 seconds
Started Mar 24 01:04:30 PM PDT 24
Finished Mar 24 01:04:32 PM PDT 24
Peak memory 208052 kb
Host smart-675c1598-1d5a-498c-b21b-316e1f450eda
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407781008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.407781008
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2821948331
Short name T1845
Test name
Test status
Simulation time 182781983 ps
CPU time 2.66 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 209004 kb
Host smart-c75cf69d-3623-4ca1-ae6f-2a4b7081bc45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821948331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2821948331
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4290977068
Short name T1776
Test name
Test status
Simulation time 5611644114 ps
CPU time 10 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:46 PM PDT 24
Peak memory 209432 kb
Host smart-ffe65daa-be3a-46e8-a71e-88e825cf08d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290977068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4290977068
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2196118529
Short name T1812
Test name
Test status
Simulation time 3206657181 ps
CPU time 18.51 seconds
Started Mar 24 01:04:31 PM PDT 24
Finished Mar 24 01:04:50 PM PDT 24
Peak memory 209392 kb
Host smart-b5df75af-01f6-4768-952b-6ce5a721bcc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196118529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2196118529
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3566302047
Short name T1805
Test name
Test status
Simulation time 1152966416 ps
CPU time 5.29 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:14 PM PDT 24
Peak memory 208484 kb
Host smart-ab649614-608b-4cd0-8bf2-167e3d8e7a2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566302047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3566302047
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1768974847
Short name T1990
Test name
Test status
Simulation time 505546760 ps
CPU time 1.94 seconds
Started Mar 24 12:42:24 PM PDT 24
Finished Mar 24 12:42:26 PM PDT 24
Peak memory 210848 kb
Host smart-39b8c4d3-98c6-4d15-b2f1-898296560773
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768974847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1768974847
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1915901401
Short name T1738
Test name
Test status
Simulation time 121425576 ps
CPU time 3.46 seconds
Started Mar 24 01:04:35 PM PDT 24
Finished Mar 24 01:04:39 PM PDT 24
Peak memory 211048 kb
Host smart-0c9ae684-acc2-4848-bafb-53d92d8d7a26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915901401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1915901401
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3825318716
Short name T1791
Test name
Test status
Simulation time 115212839 ps
CPU time 3.05 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 219276 kb
Host smart-09953aac-ee47-4d65-a132-291572df4a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382531
8716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3825318716
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1993573885
Short name T1721
Test name
Test status
Simulation time 102906988 ps
CPU time 1.9 seconds
Started Mar 24 01:04:30 PM PDT 24
Finished Mar 24 01:04:33 PM PDT 24
Peak memory 209308 kb
Host smart-d858f941-d000-4e50-b9fd-0c67288d9d55
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993573885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1993573885
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3745195312
Short name T1737
Test name
Test status
Simulation time 207360127 ps
CPU time 1.12 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:19 PM PDT 24
Peak memory 209368 kb
Host smart-144f08aa-3fad-4142-91d7-e3c07b57b063
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745195312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3745195312
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.437841338
Short name T257
Test name
Test status
Simulation time 155111651 ps
CPU time 1.25 seconds
Started Mar 24 01:04:35 PM PDT 24
Finished Mar 24 01:04:36 PM PDT 24
Peak memory 209428 kb
Host smart-e1413184-24be-4ef4-904b-21863e815c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437841338 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.437841338
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.123202702
Short name T1780
Test name
Test status
Simulation time 86412235 ps
CPU time 1.06 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 209328 kb
Host smart-bd057c99-3873-491c-aea5-c903e5350a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123202702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.123202702
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3373215831
Short name T1851
Test name
Test status
Simulation time 50362278 ps
CPU time 1.57 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:36 PM PDT 24
Peak memory 211036 kb
Host smart-34f7f873-8d23-4dca-bef2-a6f4b37de29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373215831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3373215831
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.219845591
Short name T1993
Test name
Test status
Simulation time 40430957 ps
CPU time 2.96 seconds
Started Mar 24 01:04:29 PM PDT 24
Finished Mar 24 01:04:33 PM PDT 24
Peak memory 218032 kb
Host smart-6d0b77df-f2ad-47e9-aa61-3f1f5121b0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219845591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.219845591
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3371749814
Short name T1915
Test name
Test status
Simulation time 77403724 ps
CPU time 2.43 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:18 PM PDT 24
Peak memory 217676 kb
Host smart-aa4f7301-fb2c-424f-8a39-34fe5bcafcc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371749814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3371749814
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2294102769
Short name T154
Test name
Test status
Simulation time 240550805 ps
CPU time 2.73 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 217556 kb
Host smart-f51c549c-07f5-4d6d-a5a1-39dd7f859aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294102769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2294102769
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1077925938
Short name T1994
Test name
Test status
Simulation time 27405255 ps
CPU time 2.01 seconds
Started Mar 24 01:05:08 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 219264 kb
Host smart-f5cac272-8258-4170-9573-97edb3ed4c60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077925938 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1077925938
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2734265652
Short name T1723
Test name
Test status
Simulation time 42799844 ps
CPU time 1.18 seconds
Started Mar 24 12:42:30 PM PDT 24
Finished Mar 24 12:42:31 PM PDT 24
Peak memory 218756 kb
Host smart-7a69660e-7132-425f-9e30-9297c6f9e943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734265652 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2734265652
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.261325199
Short name T244
Test name
Test status
Simulation time 13026382 ps
CPU time 0.96 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:33 PM PDT 24
Peak memory 209564 kb
Host smart-f4b852c8-26b1-4fa0-90a1-8a8ba045f4f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261325199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.261325199
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3529190
Short name T1954
Test name
Test status
Simulation time 16800890 ps
CPU time 1 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209372 kb
Host smart-9d83732d-16b0-4d2c-8165-177075a3e9db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3529190
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2893299141
Short name T1800
Test name
Test status
Simulation time 364909706 ps
CPU time 1.33 seconds
Started Mar 24 01:05:10 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 209412 kb
Host smart-606b8ae3-bd69-4298-88b5-acd8efe0564e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893299141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2893299141
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3976650862
Short name T1826
Test name
Test status
Simulation time 27121267 ps
CPU time 1.51 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:38 PM PDT 24
Peak memory 209368 kb
Host smart-0e3ec7b4-d071-440b-9ca9-a265de7aaa48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976650862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3976650862
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1144818500
Short name T1733
Test name
Test status
Simulation time 78119879 ps
CPU time 2.86 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 217780 kb
Host smart-cbf87e5e-7fa6-4884-89bc-49dfe7962154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144818500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1144818500
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2073891867
Short name T1863
Test name
Test status
Simulation time 128920730 ps
CPU time 2.24 seconds
Started Mar 24 01:05:08 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 218788 kb
Host smart-c02d94e5-dc12-49d5-8bd2-9a6ff90c4108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073891867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2073891867
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1520364222
Short name T169
Test name
Test status
Simulation time 422989557 ps
CPU time 4.1 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 217616 kb
Host smart-c1f770d4-2219-438a-bd2d-623222f2db3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520364222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1520364222
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3246182906
Short name T133
Test name
Test status
Simulation time 565552610 ps
CPU time 2.29 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:43 PM PDT 24
Peak memory 217516 kb
Host smart-ec284ec6-8314-4f9d-83e5-80aeaef80a96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246182906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.3246182906
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.13537568
Short name T1789
Test name
Test status
Simulation time 15588064 ps
CPU time 1.16 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 219208 kb
Host smart-a219b17f-ae6d-48a5-9b7c-5e9250e3ca90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537568 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.13537568
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1646495578
Short name T1732
Test name
Test status
Simulation time 18711581 ps
CPU time 1.56 seconds
Started Mar 24 12:42:30 PM PDT 24
Finished Mar 24 12:42:33 PM PDT 24
Peak memory 219752 kb
Host smart-ab4aac06-3d70-4ebd-b16f-a4a424c89967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646495578 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1646495578
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2573630556
Short name T1925
Test name
Test status
Simulation time 19372808 ps
CPU time 0.97 seconds
Started Mar 24 12:42:26 PM PDT 24
Finished Mar 24 12:42:27 PM PDT 24
Peak memory 209008 kb
Host smart-478f32fe-d83d-45b3-aa70-c8c34f49b150
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573630556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2573630556
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3127266845
Short name T1964
Test name
Test status
Simulation time 12913911 ps
CPU time 1.01 seconds
Started Mar 24 01:05:08 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 208952 kb
Host smart-5b921e06-d744-482f-8088-6aa66a5875e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127266845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3127266845
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1030946851
Short name T256
Test name
Test status
Simulation time 58339515 ps
CPU time 1.15 seconds
Started Mar 24 12:42:25 PM PDT 24
Finished Mar 24 12:42:26 PM PDT 24
Peak memory 209336 kb
Host smart-3456ac78-2dc7-4128-a565-14dc70e0a911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030946851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1030946851
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1493498476
Short name T1943
Test name
Test status
Simulation time 20904355 ps
CPU time 1.51 seconds
Started Mar 24 01:05:08 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 209436 kb
Host smart-a5347c99-e1c8-4b4f-80f7-dc9cbeef6c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493498476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1493498476
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1574099056
Short name T1912
Test name
Test status
Simulation time 156976503 ps
CPU time 2.01 seconds
Started Mar 24 12:42:31 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 217588 kb
Host smart-ec5524c1-f966-4737-9e55-c82e196ae716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574099056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1574099056
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1581130483
Short name T272
Test name
Test status
Simulation time 82354641 ps
CPU time 1.88 seconds
Started Mar 24 12:42:28 PM PDT 24
Finished Mar 24 12:42:31 PM PDT 24
Peak memory 221656 kb
Host smart-1b80391c-518c-404d-ab65-530c833569ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581130483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1581130483
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.824016241
Short name T1880
Test name
Test status
Simulation time 235472087 ps
CPU time 2.69 seconds
Started Mar 24 01:05:09 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 217456 kb
Host smart-e573496c-24ec-4da6-b48f-0327c88d4642
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824016241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.824016241
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2327359060
Short name T130
Test name
Test status
Simulation time 31145076 ps
CPU time 1.79 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 219744 kb
Host smart-5b4a89f9-81d8-4d1c-ae7a-b32cb669680e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327359060 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2327359060
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2782702288
Short name T1771
Test name
Test status
Simulation time 20225080 ps
CPU time 1.03 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 218788 kb
Host smart-15e2e82f-371e-4d8b-b424-4d2e39cdd5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782702288 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2782702288
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1018975843
Short name T1910
Test name
Test status
Simulation time 39704958 ps
CPU time 0.89 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 209300 kb
Host smart-b50262f9-a2a4-4381-8c38-0f878a0d1d86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018975843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1018975843
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2463741421
Short name T252
Test name
Test status
Simulation time 46968940 ps
CPU time 0.98 seconds
Started Mar 24 01:05:08 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 209368 kb
Host smart-1731b02f-e2f6-4ba4-95fe-8471b4a3c61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463741421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2463741421
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3120154423
Short name T1753
Test name
Test status
Simulation time 16322674 ps
CPU time 1.01 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 209352 kb
Host smart-1e1e66d5-25da-4c4d-9376-c622962fb20d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120154423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3120154423
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.606611376
Short name T1787
Test name
Test status
Simulation time 18372755 ps
CPU time 1.23 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 209460 kb
Host smart-29d80d98-6939-4afd-bf4e-b3473ca3c783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606611376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.606611376
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1149823091
Short name T1803
Test name
Test status
Simulation time 312703063 ps
CPU time 3.1 seconds
Started Mar 24 01:05:09 PM PDT 24
Finished Mar 24 01:05:13 PM PDT 24
Peak memory 217860 kb
Host smart-93322f55-2424-4940-a96c-e5a2cfca0c98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149823091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1149823091
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.471272081
Short name T141
Test name
Test status
Simulation time 1694931850 ps
CPU time 3.02 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 217884 kb
Host smart-a176d1bd-8b52-4663-be08-941ec0dc0213
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471272081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.471272081
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3605874927
Short name T160
Test name
Test status
Simulation time 142348866 ps
CPU time 3.05 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 221908 kb
Host smart-4710d6ff-dd5d-4698-8108-e1ad4e3889ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605874927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3605874927
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3630854509
Short name T163
Test name
Test status
Simulation time 151316809 ps
CPU time 1.92 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 221924 kb
Host smart-539229db-7841-41cf-83d7-84c03cd36822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630854509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3630854509
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1982615673
Short name T1763
Test name
Test status
Simulation time 40418542 ps
CPU time 0.99 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 219060 kb
Host smart-d6a05957-cd0b-44c3-9d9b-d40aa123c4c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982615673 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1982615673
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2338721268
Short name T1775
Test name
Test status
Simulation time 47989922 ps
CPU time 1.53 seconds
Started Mar 24 01:05:12 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 217672 kb
Host smart-ca563e5a-d8b4-4d54-923a-2238aa897648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338721268 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2338721268
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3701343176
Short name T248
Test name
Test status
Simulation time 110340459 ps
CPU time 0.95 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209376 kb
Host smart-32014810-e795-4073-b4d2-644a4f86a5d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701343176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3701343176
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3753324400
Short name T1935
Test name
Test status
Simulation time 19094966 ps
CPU time 0.89 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:30 PM PDT 24
Peak memory 209284 kb
Host smart-d5636d2a-3e12-4f5a-854b-f68529925390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753324400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3753324400
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1038535730
Short name T1816
Test name
Test status
Simulation time 26477672 ps
CPU time 1.33 seconds
Started Mar 24 12:42:23 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 209352 kb
Host smart-c4ed7eb4-f2fa-4399-8d88-e349e9d30145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038535730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1038535730
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.835549529
Short name T143
Test name
Test status
Simulation time 55618653 ps
CPU time 1.07 seconds
Started Mar 24 01:05:16 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 209420 kb
Host smart-9986eebe-85f3-4f37-a6a4-e9de0ede8f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835549529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.835549529
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2358914346
Short name T1860
Test name
Test status
Simulation time 33506759 ps
CPU time 2.3 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 217728 kb
Host smart-4e89383c-5534-4a1a-8710-3c9731fd54ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358914346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2358914346
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.398392739
Short name T1835
Test name
Test status
Simulation time 665186112 ps
CPU time 4.18 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:13 PM PDT 24
Peak memory 217776 kb
Host smart-e353a352-e267-427b-8282-06d3ce604b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398392739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.398392739
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1741648064
Short name T1936
Test name
Test status
Simulation time 19347502 ps
CPU time 1.16 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:16 PM PDT 24
Peak memory 219612 kb
Host smart-c7c9ad18-34ce-4f3f-9572-3c464fcb2b27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741648064 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1741648064
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3262601140
Short name T1792
Test name
Test status
Simulation time 42657182 ps
CPU time 1.53 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 219220 kb
Host smart-a9190f1c-7f9b-4ef3-bf72-2940efc50bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262601140 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3262601140
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3793591830
Short name T1985
Test name
Test status
Simulation time 85037564 ps
CPU time 1.01 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 208972 kb
Host smart-db81c527-52e8-49df-b2b8-1ed0ecbe8259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793591830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3793591830
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.466375046
Short name T250
Test name
Test status
Simulation time 31684420 ps
CPU time 0.83 seconds
Started Mar 24 12:42:27 PM PDT 24
Finished Mar 24 12:42:28 PM PDT 24
Peak memory 209124 kb
Host smart-66b4c72c-71d5-4147-8d26-478759616890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466375046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.466375046
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2516749020
Short name T1894
Test name
Test status
Simulation time 94316751 ps
CPU time 1.28 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 209304 kb
Host smart-324349c6-b076-4238-b9ce-fd3aa596d074
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516749020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2516749020
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3054427711
Short name T1852
Test name
Test status
Simulation time 51154559 ps
CPU time 1.48 seconds
Started Mar 24 01:05:16 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 209528 kb
Host smart-1a15b209-f757-44fd-9e93-321c3dc80c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054427711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3054427711
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3682944059
Short name T1892
Test name
Test status
Simulation time 116444468 ps
CPU time 2.98 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 217620 kb
Host smart-5f2bf409-8e3e-4bfc-aec3-22e2a10cea17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682944059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3682944059
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3819736322
Short name T1989
Test name
Test status
Simulation time 34899899 ps
CPU time 1.33 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:16 PM PDT 24
Peak memory 218768 kb
Host smart-0f5c4acf-d6d8-4963-8852-66de5d370153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819736322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3819736322
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2544824137
Short name T164
Test name
Test status
Simulation time 168326593 ps
CPU time 1.98 seconds
Started Mar 24 01:05:16 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 221928 kb
Host smart-2dabbcdd-28aa-4efe-a8cb-a976b1007d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544824137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2544824137
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3689306066
Short name T146
Test name
Test status
Simulation time 103800118 ps
CPU time 3.11 seconds
Started Mar 24 12:42:25 PM PDT 24
Finished Mar 24 12:42:28 PM PDT 24
Peak memory 221908 kb
Host smart-5921190c-4fb1-4b79-b43c-87fed441285d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689306066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3689306066
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3537360142
Short name T1980
Test name
Test status
Simulation time 99586920 ps
CPU time 1.19 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:16 PM PDT 24
Peak memory 217792 kb
Host smart-c3c93e73-7f0a-4b57-a43e-12448f267abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537360142 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3537360142
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.830651816
Short name T1788
Test name
Test status
Simulation time 36841287 ps
CPU time 1.29 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 218616 kb
Host smart-61dda75e-9ee7-4c99-91f0-acb1f7d61e7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830651816 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.830651816
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2581752620
Short name T1710
Test name
Test status
Simulation time 48076013 ps
CPU time 0.85 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 208508 kb
Host smart-4989063c-ae78-40a3-83fc-4a7b1145e233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581752620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2581752620
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3914834050
Short name T1841
Test name
Test status
Simulation time 47520764 ps
CPU time 0.92 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 209372 kb
Host smart-a2993eea-f7c5-4862-8843-d74aceba0c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914834050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3914834050
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1000764932
Short name T1981
Test name
Test status
Simulation time 15841700 ps
CPU time 1.21 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 209436 kb
Host smart-12ffee6d-0bb2-41b3-9ad4-edf8592461e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000764932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1000764932
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2784914407
Short name T1987
Test name
Test status
Simulation time 29813678 ps
CPU time 1.17 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 209324 kb
Host smart-3e98de41-98c2-44a7-bf82-4271c0333e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784914407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2784914407
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2488187719
Short name T1857
Test name
Test status
Simulation time 291277823 ps
CPU time 2.32 seconds
Started Mar 24 01:05:14 PM PDT 24
Finished Mar 24 01:05:17 PM PDT 24
Peak memory 218100 kb
Host smart-fd5b4769-ed93-479b-9103-dda83f87657b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488187719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2488187719
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2895938950
Short name T1747
Test name
Test status
Simulation time 209456201 ps
CPU time 1.95 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 217672 kb
Host smart-809678c2-c3a0-4586-b7f0-29a9ba4916eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895938950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2895938950
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.473076271
Short name T175
Test name
Test status
Simulation time 133219353 ps
CPU time 2.76 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:17 PM PDT 24
Peak memory 217628 kb
Host smart-b2b8dd38-74fc-4379-a1cc-167905e0b85f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473076271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.473076271
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1043119574
Short name T1837
Test name
Test status
Simulation time 24643324 ps
CPU time 1.8 seconds
Started Mar 24 01:05:12 PM PDT 24
Finished Mar 24 01:05:16 PM PDT 24
Peak memory 219116 kb
Host smart-994a0c0a-5c2e-459e-ab46-46a0d2f92637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043119574 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1043119574
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1434322455
Short name T1942
Test name
Test status
Simulation time 18733093 ps
CPU time 1.03 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 218676 kb
Host smart-9b774680-5af8-4d9b-b714-1324e013612b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434322455 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1434322455
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1706663927
Short name T236
Test name
Test status
Simulation time 19389774 ps
CPU time 1.01 seconds
Started Mar 24 01:05:12 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 209400 kb
Host smart-04576814-608b-4fed-be11-1eaa35ed97ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706663927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1706663927
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2424647923
Short name T1991
Test name
Test status
Simulation time 34173183 ps
CPU time 0.88 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 209380 kb
Host smart-3d7d5832-ddaf-4cf1-bc9d-0ff320b8c714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424647923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2424647923
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2500967849
Short name T1813
Test name
Test status
Simulation time 75151760 ps
CPU time 1.28 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 209440 kb
Host smart-712549ee-7bc2-4652-9c1d-88ad90e698ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500967849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2500967849
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3785175182
Short name T1858
Test name
Test status
Simulation time 26070440 ps
CPU time 1.33 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 209332 kb
Host smart-c0e39ff1-d9a0-4356-a6fe-accd56e1621f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785175182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3785175182
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3518800595
Short name T142
Test name
Test status
Simulation time 203803272 ps
CPU time 2.92 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 217752 kb
Host smart-9487e7b2-9e1d-4977-a321-f7d51143b8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518800595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3518800595
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4264369026
Short name T1739
Test name
Test status
Simulation time 70614592 ps
CPU time 2.93 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:20 PM PDT 24
Peak memory 217968 kb
Host smart-9839e8ca-f69d-45d9-ad5b-e00e6e57feb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264369026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4264369026
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.358743605
Short name T144
Test name
Test status
Simulation time 746289939 ps
CPU time 3.82 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 217420 kb
Host smart-f7dab96d-2758-4b66-bc6f-6a3cc3b539a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358743605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.358743605
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.529603286
Short name T161
Test name
Test status
Simulation time 113848919 ps
CPU time 2.99 seconds
Started Mar 24 01:05:16 PM PDT 24
Finished Mar 24 01:05:21 PM PDT 24
Peak memory 221904 kb
Host smart-98d4d6c7-1d3f-4e82-b159-3f527d00aa57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529603286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.529603286
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2201587032
Short name T1856
Test name
Test status
Simulation time 28364344 ps
CPU time 1.68 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 218124 kb
Host smart-9964e8c3-748b-487e-8d54-bd3510070a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201587032 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2201587032
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.593069708
Short name T1924
Test name
Test status
Simulation time 248327925 ps
CPU time 1.28 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 219124 kb
Host smart-382ab8aa-28a0-4b22-b96a-f27851e7a02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593069708 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.593069708
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3635325355
Short name T1893
Test name
Test status
Simulation time 25618990 ps
CPU time 0.85 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 209228 kb
Host smart-115ec5c2-3920-43ee-acca-710b709adb39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635325355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3635325355
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.700901813
Short name T1968
Test name
Test status
Simulation time 28950595 ps
CPU time 0.98 seconds
Started Mar 24 12:42:25 PM PDT 24
Finished Mar 24 12:42:27 PM PDT 24
Peak memory 209288 kb
Host smart-bd3ea052-7337-4a6e-9de1-3350231f3643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700901813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.700901813
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.55337200
Short name T1913
Test name
Test status
Simulation time 83285474 ps
CPU time 1.07 seconds
Started Mar 24 01:05:16 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 209540 kb
Host smart-477912e3-ac57-4dfb-a8b2-0f9e5a7a9cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55337200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
same_csr_outstanding.55337200
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.56549289
Short name T1921
Test name
Test status
Simulation time 30614690 ps
CPU time 1.12 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 209328 kb
Host smart-168b7536-e9a0-4dd1-9baa-17a4736249e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56549289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
same_csr_outstanding.56549289
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1860331796
Short name T1759
Test name
Test status
Simulation time 24523573 ps
CPU time 1.58 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 217648 kb
Host smart-b16170d3-1e18-46dc-b6e5-efd6b8eb101d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860331796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1860331796
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.875631039
Short name T1797
Test name
Test status
Simulation time 182607404 ps
CPU time 4.09 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 217768 kb
Host smart-1597c853-d3fa-484a-8909-09862d481b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875631039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.875631039
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3192911454
Short name T166
Test name
Test status
Simulation time 93334652 ps
CPU time 2.44 seconds
Started Mar 24 01:05:13 PM PDT 24
Finished Mar 24 01:05:17 PM PDT 24
Peak memory 217644 kb
Host smart-e04de2a7-2d91-444a-8af6-064ac904fc7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192911454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3192911454
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1924933766
Short name T1899
Test name
Test status
Simulation time 33461074 ps
CPU time 1.01 seconds
Started Mar 24 01:05:12 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 219300 kb
Host smart-288cc26a-307e-48db-b775-a6777f07ae39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924933766 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1924933766
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4056791278
Short name T1750
Test name
Test status
Simulation time 22746037 ps
CPU time 1.63 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:35 PM PDT 24
Peak memory 217628 kb
Host smart-5017ea7a-e95d-4663-aaf7-373968f61b29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056791278 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4056791278
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1091395688
Short name T1817
Test name
Test status
Simulation time 13548676 ps
CPU time 1.03 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 209020 kb
Host smart-58633cf1-6b7c-4ad2-a57b-b7a3629b584f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091395688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1091395688
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3019238273
Short name T1997
Test name
Test status
Simulation time 195670647 ps
CPU time 0.82 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 208528 kb
Host smart-cca1b149-9e4c-4de4-82ad-4a9aa99a7b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019238273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3019238273
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1350704409
Short name T1859
Test name
Test status
Simulation time 49541093 ps
CPU time 1.17 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:17 PM PDT 24
Peak memory 208932 kb
Host smart-e73157f8-fd5c-4653-be4f-fea78f9881e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350704409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1350704409
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1666094813
Short name T258
Test name
Test status
Simulation time 53900264 ps
CPU time 0.98 seconds
Started Mar 24 12:42:31 PM PDT 24
Finished Mar 24 12:42:32 PM PDT 24
Peak memory 209356 kb
Host smart-779a839f-22b7-4c83-b337-1765a6c61a4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666094813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1666094813
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3578688379
Short name T162
Test name
Test status
Simulation time 408623914 ps
CPU time 4.19 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 217772 kb
Host smart-ea18e899-c9b0-47d1-bbae-ec44bb9d683d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578688379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3578688379
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.745461166
Short name T1907
Test name
Test status
Simulation time 97217423 ps
CPU time 2.2 seconds
Started Mar 24 01:05:15 PM PDT 24
Finished Mar 24 01:05:18 PM PDT 24
Peak memory 217708 kb
Host smart-9a131acc-b267-49c9-b082-48c5c58b838f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745461166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.745461166
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1511792357
Short name T168
Test name
Test status
Simulation time 44799196 ps
CPU time 1.85 seconds
Started Mar 24 01:05:14 PM PDT 24
Finished Mar 24 01:05:16 PM PDT 24
Peak memory 221508 kb
Host smart-162ebee6-7c2f-4ec8-b616-a1e0c625cae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511792357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1511792357
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.619983512
Short name T1972
Test name
Test status
Simulation time 62924317 ps
CPU time 2.55 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:37 PM PDT 24
Peak memory 217500 kb
Host smart-32d376ca-3925-4c0c-9476-c52e5f41f57c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619983512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.619983512
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4259912314
Short name T1821
Test name
Test status
Simulation time 59592303 ps
CPU time 1.07 seconds
Started Mar 24 01:05:17 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 219236 kb
Host smart-2b58d703-0908-4b44-ade1-392d2a27fc96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259912314 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.4259912314
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.682582968
Short name T1853
Test name
Test status
Simulation time 50552779 ps
CPU time 1.09 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 219628 kb
Host smart-390fbdc7-fb04-4ad2-b518-8155cf6cc0c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682582968 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.682582968
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2018469383
Short name T247
Test name
Test status
Simulation time 117148436 ps
CPU time 0.92 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 209240 kb
Host smart-895ff0c5-244a-481a-9321-caf1ba1198d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018469383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2018469383
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3345139334
Short name T1749
Test name
Test status
Simulation time 16279308 ps
CPU time 0.91 seconds
Started Mar 24 01:05:20 PM PDT 24
Finished Mar 24 01:05:21 PM PDT 24
Peak memory 209372 kb
Host smart-6d9bffd5-e769-4981-8bef-49b5f5b29501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345139334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3345139334
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3921467497
Short name T1898
Test name
Test status
Simulation time 172765116 ps
CPU time 1.58 seconds
Started Mar 24 12:42:24 PM PDT 24
Finished Mar 24 12:42:25 PM PDT 24
Peak memory 209308 kb
Host smart-3dd7c00c-fe54-436f-b058-d9872e47de29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921467497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3921467497
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.967435794
Short name T1810
Test name
Test status
Simulation time 515947667 ps
CPU time 1.28 seconds
Started Mar 24 01:05:18 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 209428 kb
Host smart-5dc9cb45-b8cc-4bfd-966b-215d4cda99d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967435794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.967435794
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3019265742
Short name T1963
Test name
Test status
Simulation time 44777408 ps
CPU time 2.46 seconds
Started Mar 24 01:05:17 PM PDT 24
Finished Mar 24 01:05:21 PM PDT 24
Peak memory 218816 kb
Host smart-e905c5e3-9506-4999-8bb9-2a8cc8177803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019265742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3019265742
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1369297734
Short name T172
Test name
Test status
Simulation time 176638115 ps
CPU time 2.05 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:32 PM PDT 24
Peak memory 222064 kb
Host smart-926fc520-efc6-42ae-89f4-b9c04ea496f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369297734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1369297734
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1385384632
Short name T158
Test name
Test status
Simulation time 156932428 ps
CPU time 3.38 seconds
Started Mar 24 01:05:19 PM PDT 24
Finished Mar 24 01:05:22 PM PDT 24
Peak memory 222532 kb
Host smart-babbdb99-936e-4291-800b-f52d3893cf19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385384632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1385384632
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.170563052
Short name T1709
Test name
Test status
Simulation time 348352089 ps
CPU time 0.97 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:18 PM PDT 24
Peak memory 209336 kb
Host smart-ea5e51c6-eee6-49a8-a0c0-c61fb139cde2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170563052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.170563052
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1808342548
Short name T253
Test name
Test status
Simulation time 329015684 ps
CPU time 1.37 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:36 PM PDT 24
Peak memory 209456 kb
Host smart-f8b18ec1-0c30-4c32-8ce9-5f17aa8990d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808342548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1808342548
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2378599970
Short name T1736
Test name
Test status
Simulation time 379381744 ps
CPU time 2.17 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:37 PM PDT 24
Peak memory 209020 kb
Host smart-22e0fa16-b964-4602-ab98-22af93e19119
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378599970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2378599970
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2633721059
Short name T1708
Test name
Test status
Simulation time 27310894 ps
CPU time 1.62 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 209344 kb
Host smart-a3c24b78-e43d-4d7b-ab73-1f189d2146d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633721059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2633721059
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3537683896
Short name T136
Test name
Test status
Simulation time 200080649 ps
CPU time 1.13 seconds
Started Mar 24 01:04:35 PM PDT 24
Finished Mar 24 01:04:36 PM PDT 24
Peak memory 218192 kb
Host smart-2ea6bb8f-b58f-47a7-bb0f-cd86b52f1916
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537683896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3537683896
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3943127585
Short name T1770
Test name
Test status
Simulation time 17026443 ps
CPU time 0.95 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:31 PM PDT 24
Peak memory 209896 kb
Host smart-3cf65781-23b6-4c26-9b5e-2b5d36b255c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943127585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3943127585
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1673502910
Short name T1757
Test name
Test status
Simulation time 30207558 ps
CPU time 1.08 seconds
Started Mar 24 12:42:22 PM PDT 24
Finished Mar 24 12:42:23 PM PDT 24
Peak memory 219620 kb
Host smart-fe1ece54-647e-49e4-883d-ab9a0d24979a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673502910 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1673502910
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3626006552
Short name T1918
Test name
Test status
Simulation time 93730645 ps
CPU time 1.94 seconds
Started Mar 24 01:04:35 PM PDT 24
Finished Mar 24 01:04:37 PM PDT 24
Peak memory 218744 kb
Host smart-6661df7c-6d86-4c42-999d-b99009c7b133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626006552 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3626006552
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4162579474
Short name T1715
Test name
Test status
Simulation time 15621010 ps
CPU time 1.03 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:37 PM PDT 24
Peak memory 209308 kb
Host smart-422f86f4-c81b-4545-81c5-6d7d54d4a351
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162579474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4162579474
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.676159409
Short name T1955
Test name
Test status
Simulation time 12690688 ps
CPU time 0.96 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:16 PM PDT 24
Peak memory 209280 kb
Host smart-61edf4f0-e43b-426e-bb3a-851f513733be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676159409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.676159409
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2281296053
Short name T1714
Test name
Test status
Simulation time 279422260 ps
CPU time 1.42 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 209316 kb
Host smart-f24a59e1-2139-471c-987d-1af90881d08c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281296053 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2281296053
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2906563842
Short name T1889
Test name
Test status
Simulation time 981673474 ps
CPU time 1.2 seconds
Started Mar 24 01:04:29 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 209296 kb
Host smart-7d71bf20-a662-47d0-9fa0-1ce6e6b20c5b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906563842 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2906563842
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4208649107
Short name T1755
Test name
Test status
Simulation time 2393304111 ps
CPU time 14.54 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:30 PM PDT 24
Peak memory 209096 kb
Host smart-16b367fb-e2cc-44bd-87da-23d30fdc984a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208649107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4208649107
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.716062352
Short name T1795
Test name
Test status
Simulation time 400558212 ps
CPU time 5.37 seconds
Started Mar 24 01:04:31 PM PDT 24
Finished Mar 24 01:04:37 PM PDT 24
Peak memory 208608 kb
Host smart-58fb0639-b9d7-44a7-88f2-7dd9d5cc88ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716062352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.716062352
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1992818508
Short name T1774
Test name
Test status
Simulation time 734438201 ps
CPU time 17.15 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 209256 kb
Host smart-7044d4fc-bcc0-4c2d-be0e-54b29e23aa33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992818508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1992818508
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2176039515
Short name T1962
Test name
Test status
Simulation time 1008324199 ps
CPU time 23 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:58 PM PDT 24
Peak memory 209128 kb
Host smart-41eae1c7-092b-49c2-8889-a24f4623c415
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176039515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2176039515
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1961384585
Short name T1897
Test name
Test status
Simulation time 491662198 ps
CPU time 2.63 seconds
Started Mar 24 12:42:22 PM PDT 24
Finished Mar 24 12:42:25 PM PDT 24
Peak memory 211068 kb
Host smart-a9d44aab-724b-432f-89c3-10688d5fe335
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961384585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1961384585
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.807991308
Short name T1875
Test name
Test status
Simulation time 131125284 ps
CPU time 3.59 seconds
Started Mar 24 01:04:31 PM PDT 24
Finished Mar 24 01:04:35 PM PDT 24
Peak memory 210988 kb
Host smart-671027a8-7d74-46ad-a98e-1e4afe55f3dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807991308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.807991308
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3822707322
Short name T1870
Test name
Test status
Simulation time 761145111 ps
CPU time 6.34 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:41 PM PDT 24
Peak memory 219188 kb
Host smart-562b7756-8a30-4d06-b51b-60b53f4e5f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382270
7322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3822707322
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.896916150
Short name T1998
Test name
Test status
Simulation time 726130094 ps
CPU time 1.7 seconds
Started Mar 24 12:42:20 PM PDT 24
Finished Mar 24 12:42:22 PM PDT 24
Peak memory 217708 kb
Host smart-b344e2b2-6fe3-4a8f-98b1-9966796e7c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896916
150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.896916150
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2766188673
Short name T1938
Test name
Test status
Simulation time 3557391560 ps
CPU time 2.25 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:37 PM PDT 24
Peak memory 209388 kb
Host smart-80689a4a-eddf-428a-80f4-a1318b0f8268
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766188673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2766188673
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2948745823
Short name T1887
Test name
Test status
Simulation time 281094073 ps
CPU time 2.45 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 209256 kb
Host smart-c5b194ce-8a65-4da7-9abb-31abd7bd8c52
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948745823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2948745823
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2019558866
Short name T1901
Test name
Test status
Simulation time 76295307 ps
CPU time 1.48 seconds
Started Mar 24 01:04:34 PM PDT 24
Finished Mar 24 01:04:36 PM PDT 24
Peak memory 211424 kb
Host smart-5ef14b00-d561-4e4d-86b3-16ad8b3a39cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019558866 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2019558866
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2448683635
Short name T1916
Test name
Test status
Simulation time 49039160 ps
CPU time 2.03 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:17 PM PDT 24
Peak memory 211428 kb
Host smart-92333a3c-1410-4968-b791-9e3d7a76f9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448683635 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2448683635
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1584899265
Short name T1977
Test name
Test status
Simulation time 164824386 ps
CPU time 1.05 seconds
Started Mar 24 01:04:37 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 209480 kb
Host smart-4ebb8373-f1fd-4b33-9a5d-b0eef4ef3e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584899265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1584899265
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3339789136
Short name T1748
Test name
Test status
Simulation time 88402530 ps
CPU time 1.13 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 209436 kb
Host smart-af9e2317-c149-432e-bd86-bfc3a98d5a68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339789136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3339789136
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3897177924
Short name T1731
Test name
Test status
Simulation time 84925532 ps
CPU time 2.07 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 217680 kb
Host smart-3ac03a70-ae30-4e49-9dcf-7f6cc2204196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897177924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3897177924
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.584164301
Short name T1769
Test name
Test status
Simulation time 29511639 ps
CPU time 2.14 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 217784 kb
Host smart-684ba11b-6903-4697-9d64-7d02e0c47b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584164301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.584164301
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1053232881
Short name T147
Test name
Test status
Simulation time 101593382 ps
CPU time 2.78 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:20 PM PDT 24
Peak memory 221860 kb
Host smart-5e2f508c-2769-4883-b47b-821197164eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053232881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1053232881
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3558307403
Short name T150
Test name
Test status
Simulation time 1098003071 ps
CPU time 3.99 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:40 PM PDT 24
Peak memory 217508 kb
Host smart-01f83a4a-2887-4469-a218-94c3f6a9e104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558307403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3558307403
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1804325237
Short name T1713
Test name
Test status
Simulation time 94360117 ps
CPU time 1.41 seconds
Started Mar 24 12:42:23 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 209296 kb
Host smart-f230a3db-8740-4c88-9d72-5ad27b97dbdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804325237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1804325237
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3397191637
Short name T1719
Test name
Test status
Simulation time 59603992 ps
CPU time 1.32 seconds
Started Mar 24 01:04:45 PM PDT 24
Finished Mar 24 01:04:47 PM PDT 24
Peak memory 209396 kb
Host smart-6509346e-d186-4c27-8291-367ef44e8627
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397191637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3397191637
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3851013125
Short name T1741
Test name
Test status
Simulation time 18121002 ps
CPU time 1.16 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 209148 kb
Host smart-f0200ed9-9fec-4734-8ab5-17fe0b59bd62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851013125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3851013125
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3981285617
Short name T1861
Test name
Test status
Simulation time 116556496 ps
CPU time 1.2 seconds
Started Mar 24 01:04:42 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 208636 kb
Host smart-de949124-bfda-4008-a13a-57e155cd8811
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981285617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3981285617
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1992556175
Short name T1726
Test name
Test status
Simulation time 71227799 ps
CPU time 1.01 seconds
Started Mar 24 01:04:43 PM PDT 24
Finished Mar 24 01:04:45 PM PDT 24
Peak memory 209880 kb
Host smart-69e9b779-36c1-42d3-9f9b-f926dbbfaa21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992556175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1992556175
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3665168738
Short name T245
Test name
Test status
Simulation time 224920921 ps
CPU time 1.17 seconds
Started Mar 24 12:42:23 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 209784 kb
Host smart-c3f78173-0a35-41b1-82f7-b870d9c7dc58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665168738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3665168738
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.131583537
Short name T1822
Test name
Test status
Simulation time 27698543 ps
CPU time 1.34 seconds
Started Mar 24 01:04:42 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 219216 kb
Host smart-cc4f00f5-83e5-44ba-9e2d-fb0e1b12b504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131583537 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.131583537
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1379846233
Short name T1932
Test name
Test status
Simulation time 75840612 ps
CPU time 1.27 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 222420 kb
Host smart-8a8061b6-f4d1-4570-834a-7aade6ad2782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379846233 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1379846233
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1712182603
Short name T251
Test name
Test status
Simulation time 209628473 ps
CPU time 1.07 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 209228 kb
Host smart-f3051f8b-614d-44dc-b235-8cb98cca204a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712182603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1712182603
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.4284608276
Short name T1971
Test name
Test status
Simulation time 26801456 ps
CPU time 0.86 seconds
Started Mar 24 01:04:41 PM PDT 24
Finished Mar 24 01:04:42 PM PDT 24
Peak memory 209240 kb
Host smart-fc6bbbd8-4899-4010-9a5d-5180e9ba311d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284608276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.4284608276
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1984492186
Short name T1855
Test name
Test status
Simulation time 276786727 ps
CPU time 1.49 seconds
Started Mar 24 01:04:42 PM PDT 24
Finished Mar 24 01:04:45 PM PDT 24
Peak memory 207960 kb
Host smart-43d1352e-5bb5-4a7c-aa3d-f49fa02cabb0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984492186 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1984492186
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3624955624
Short name T1933
Test name
Test status
Simulation time 82537783 ps
CPU time 0.88 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 209100 kb
Host smart-afec5575-3b28-4524-a3b5-5ab65406e4dd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624955624 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3624955624
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2919152323
Short name T1939
Test name
Test status
Simulation time 1481938377 ps
CPU time 5.29 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:42 PM PDT 24
Peak memory 209180 kb
Host smart-cf843d73-97b7-4054-bd82-812f5631a304
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919152323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2919152323
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3088545019
Short name T1744
Test name
Test status
Simulation time 3327494434 ps
CPU time 20.38 seconds
Started Mar 24 12:42:23 PM PDT 24
Finished Mar 24 12:42:43 PM PDT 24
Peak memory 209340 kb
Host smart-3b5b2399-246a-45ba-82ac-ab0233a0e700
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088545019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3088545019
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1103614817
Short name T1950
Test name
Test status
Simulation time 5759177239 ps
CPU time 9.29 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:45 PM PDT 24
Peak memory 209460 kb
Host smart-37b217e8-b4f1-4a7f-8d88-a346fc075174
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103614817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1103614817
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1385454282
Short name T1728
Test name
Test status
Simulation time 5071541699 ps
CPU time 11.54 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:18 PM PDT 24
Peak memory 208460 kb
Host smart-031ab37f-c644-4532-9e4e-f6143eaaa0ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385454282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1385454282
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.339193269
Short name T1840
Test name
Test status
Simulation time 673693057 ps
CPU time 1.95 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 211232 kb
Host smart-bc0b31c9-16c1-4d9a-9bf8-4e31f5cf406a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339193269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.339193269
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.910812745
Short name T1896
Test name
Test status
Simulation time 118442620 ps
CPU time 1.69 seconds
Started Mar 24 01:04:36 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 210672 kb
Host smart-3894571f-6897-44e9-aa43-fb166dae96fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910812745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.910812745
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1666036119
Short name T1854
Test name
Test status
Simulation time 1030217259 ps
CPU time 4.54 seconds
Started Mar 24 12:42:12 PM PDT 24
Finished Mar 24 12:42:17 PM PDT 24
Peak memory 217564 kb
Host smart-46df9cfa-b46c-4aba-849b-2bc7fba84d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166603
6119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1666036119
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3021785749
Short name T1948
Test name
Test status
Simulation time 690704309 ps
CPU time 2.34 seconds
Started Mar 24 01:04:41 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 219724 kb
Host smart-b2bf4d8b-0b50-4822-852a-3c14ebff8a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302178
5749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3021785749
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1403486854
Short name T1772
Test name
Test status
Simulation time 126537696 ps
CPU time 1.4 seconds
Started Mar 24 01:04:35 PM PDT 24
Finished Mar 24 01:04:37 PM PDT 24
Peak memory 209392 kb
Host smart-ce7d64e5-0091-499e-8a4d-2054f8233727
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403486854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1403486854
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3557880910
Short name T1976
Test name
Test status
Simulation time 324360801 ps
CPU time 1.52 seconds
Started Mar 24 12:42:10 PM PDT 24
Finished Mar 24 12:42:12 PM PDT 24
Peak memory 209280 kb
Host smart-1470e441-b874-4dbe-990a-c08b0b442973
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557880910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3557880910
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1940264381
Short name T1983
Test name
Test status
Simulation time 29412432 ps
CPU time 1.4 seconds
Started Mar 24 12:42:19 PM PDT 24
Finished Mar 24 12:42:21 PM PDT 24
Peak memory 208940 kb
Host smart-921ca29d-9bc4-4210-bb98-5973a546d901
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940264381 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1940264381
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3459018333
Short name T259
Test name
Test status
Simulation time 199556154 ps
CPU time 2.1 seconds
Started Mar 24 01:04:37 PM PDT 24
Finished Mar 24 01:04:39 PM PDT 24
Peak memory 211528 kb
Host smart-574b7a68-8a70-470a-9eaa-a68a95ad0bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459018333 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3459018333
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1072740228
Short name T1904
Test name
Test status
Simulation time 27461677 ps
CPU time 0.95 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 209308 kb
Host smart-b80a53ee-1236-4be0-abca-62c6c692374d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072740228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1072740228
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.692476618
Short name T1778
Test name
Test status
Simulation time 21916116 ps
CPU time 1.29 seconds
Started Mar 24 01:04:40 PM PDT 24
Finished Mar 24 01:04:42 PM PDT 24
Peak memory 209452 kb
Host smart-c0df9169-2e71-40d9-8c73-abe6c860a711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692476618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.692476618
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3747067860
Short name T1825
Test name
Test status
Simulation time 61239891 ps
CPU time 1.81 seconds
Started Mar 24 01:04:41 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 218484 kb
Host smart-eee6cdfc-0f37-435e-9573-b885756df954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747067860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3747067860
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.725563649
Short name T1720
Test name
Test status
Simulation time 55918284 ps
CPU time 2.82 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 217792 kb
Host smart-d809bf4e-4a3f-4095-9b59-0edc78b765eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725563649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.725563649
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1576295050
Short name T171
Test name
Test status
Simulation time 229603290 ps
CPU time 2.5 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 217552 kb
Host smart-6acaea2c-5ce7-49f7-98f2-f8ee9985a42b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576295050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1576295050
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1694537505
Short name T1782
Test name
Test status
Simulation time 21401092 ps
CPU time 0.97 seconds
Started Mar 24 01:04:47 PM PDT 24
Finished Mar 24 01:04:49 PM PDT 24
Peak memory 209364 kb
Host smart-6984c7f3-6d3a-437a-877a-90345ec25bb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694537505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1694537505
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3955645877
Short name T1874
Test name
Test status
Simulation time 78619176 ps
CPU time 1.2 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 209304 kb
Host smart-7f5c219e-0164-436c-9bc9-96d7b6b7376f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955645877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.3955645877
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.364363762
Short name T1905
Test name
Test status
Simulation time 103623269 ps
CPU time 1.81 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 208192 kb
Host smart-fc5de86c-f31f-4ea1-a621-66534e08ec4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364363762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.364363762
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.510680736
Short name T1730
Test name
Test status
Simulation time 68720542 ps
CPU time 1.4 seconds
Started Mar 24 01:04:46 PM PDT 24
Finished Mar 24 01:04:48 PM PDT 24
Peak memory 209280 kb
Host smart-74ba56e1-5ea0-4c1d-9a09-7674ea420ae3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510680736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.510680736
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2313498205
Short name T1768
Test name
Test status
Simulation time 30886965 ps
CPU time 1.01 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:37 PM PDT 24
Peak memory 210600 kb
Host smart-3c8e7029-88f8-4636-b75e-39a79b4e2b15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313498205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2313498205
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.756243456
Short name T243
Test name
Test status
Simulation time 16412246 ps
CPU time 1.13 seconds
Started Mar 24 01:04:44 PM PDT 24
Finished Mar 24 01:04:46 PM PDT 24
Peak memory 209860 kb
Host smart-82955950-fbc6-4b20-9e37-4b804410e8ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756243456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.756243456
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2675141106
Short name T1831
Test name
Test status
Simulation time 25402726 ps
CPU time 1.68 seconds
Started Mar 24 01:04:50 PM PDT 24
Finished Mar 24 01:04:52 PM PDT 24
Peak memory 222680 kb
Host smart-74d5387b-85fc-41e3-b853-ad33088cbd62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675141106 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2675141106
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.960861565
Short name T1934
Test name
Test status
Simulation time 25516664 ps
CPU time 1.12 seconds
Started Mar 24 12:42:16 PM PDT 24
Finished Mar 24 12:42:17 PM PDT 24
Peak memory 217744 kb
Host smart-7a9c6b91-f6bf-4a15-b5a3-2b45ec889bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960861565 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.960861565
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1079148208
Short name T249
Test name
Test status
Simulation time 27510040 ps
CPU time 0.92 seconds
Started Mar 24 01:04:47 PM PDT 24
Finished Mar 24 01:04:49 PM PDT 24
Peak memory 208880 kb
Host smart-07401739-d6b6-4073-ba31-91e5bd633080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079148208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1079148208
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.167479070
Short name T1951
Test name
Test status
Simulation time 45366750 ps
CPU time 0.89 seconds
Started Mar 24 12:42:16 PM PDT 24
Finished Mar 24 12:42:17 PM PDT 24
Peak memory 208764 kb
Host smart-aed1d8d7-07b6-422c-a1c8-49a1095a84ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167479070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.167479070
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2202987457
Short name T1953
Test name
Test status
Simulation time 218452516 ps
CPU time 1.29 seconds
Started Mar 24 01:04:44 PM PDT 24
Finished Mar 24 01:04:46 PM PDT 24
Peak memory 209324 kb
Host smart-a225138a-610b-4ac4-8d76-27aa5b291002
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202987457 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2202987457
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.403784597
Short name T1959
Test name
Test status
Simulation time 44015970 ps
CPU time 1.6 seconds
Started Mar 24 12:42:54 PM PDT 24
Finished Mar 24 12:42:55 PM PDT 24
Peak memory 208052 kb
Host smart-c33cba1c-a688-4406-ab0b-094a906a0e1e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403784597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.403784597
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3128205950
Short name T1786
Test name
Test status
Simulation time 2315569008 ps
CPU time 6.47 seconds
Started Mar 24 01:04:41 PM PDT 24
Finished Mar 24 01:04:48 PM PDT 24
Peak memory 208604 kb
Host smart-c639b3a3-9f4f-4828-ae35-320bcc4565f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128205950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3128205950
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3673860419
Short name T1729
Test name
Test status
Simulation time 7930092096 ps
CPU time 5.97 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:22 PM PDT 24
Peak memory 209336 kb
Host smart-b4c57ffa-c752-4ff0-87ad-91c0b2fdf6fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673860419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3673860419
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1211042499
Short name T1914
Test name
Test status
Simulation time 802966665 ps
CPU time 9.99 seconds
Started Mar 24 12:42:12 PM PDT 24
Finished Mar 24 12:42:22 PM PDT 24
Peak memory 208488 kb
Host smart-f0c58af7-b981-4299-a300-9168eb309731
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211042499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1211042499
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1221539674
Short name T1765
Test name
Test status
Simulation time 1687777075 ps
CPU time 5.02 seconds
Started Mar 24 01:04:41 PM PDT 24
Finished Mar 24 01:04:46 PM PDT 24
Peak memory 209008 kb
Host smart-0662028f-bd3e-4707-a38c-06bc7f735953
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221539674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1221539674
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3820280014
Short name T176
Test name
Test status
Simulation time 239411266 ps
CPU time 2.03 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 210624 kb
Host smart-29060fe4-d2b9-414b-9fbc-6b5ea08ae3eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820280014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3820280014
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4134091707
Short name T1958
Test name
Test status
Simulation time 632067823 ps
CPU time 4.41 seconds
Started Mar 24 01:04:42 PM PDT 24
Finished Mar 24 01:04:46 PM PDT 24
Peak memory 211028 kb
Host smart-6cb5b816-8ada-4985-a28d-95c0e211a991
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134091707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4134091707
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1514813069
Short name T1876
Test name
Test status
Simulation time 1108893553 ps
CPU time 3.06 seconds
Started Mar 24 12:42:26 PM PDT 24
Finished Mar 24 12:42:29 PM PDT 24
Peak memory 217620 kb
Host smart-7b1b6404-602e-4218-a4d1-33d9f0738249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151481
3069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1514813069
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.43086870
Short name T1891
Test name
Test status
Simulation time 439569770 ps
CPU time 2.94 seconds
Started Mar 24 01:04:43 PM PDT 24
Finished Mar 24 01:04:47 PM PDT 24
Peak memory 217840 kb
Host smart-2e6d908c-7975-4d27-8e37-8fb15c66f45b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430868
70 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.43086870
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1975619482
Short name T1839
Test name
Test status
Simulation time 179312136 ps
CPU time 1.14 seconds
Started Mar 24 01:04:42 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 209572 kb
Host smart-763b6ab7-a03e-4ae7-8b42-594e7f84ec45
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975619482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1975619482
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2075033399
Short name T1833
Test name
Test status
Simulation time 51605555 ps
CPU time 1.12 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 209376 kb
Host smart-95d6484c-a8ba-4f3d-9d15-db971b66d5c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075033399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2075033399
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.108683667
Short name T1802
Test name
Test status
Simulation time 47984206 ps
CPU time 1.15 seconds
Started Mar 24 01:04:42 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 209444 kb
Host smart-95d6e349-2d23-4ced-9a6c-6323a3c6827e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108683667 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.108683667
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2905441993
Short name T181
Test name
Test status
Simulation time 100545685 ps
CPU time 1.46 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:38 PM PDT 24
Peak memory 211484 kb
Host smart-74c80d47-60d0-4a1a-a2fc-3de8d7a621ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905441993 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2905441993
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.509845279
Short name T1806
Test name
Test status
Simulation time 24592429 ps
CPU time 1.06 seconds
Started Mar 24 01:04:46 PM PDT 24
Finished Mar 24 01:04:47 PM PDT 24
Peak memory 209432 kb
Host smart-017bf457-cf58-4e44-8d43-4d4dda589453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509845279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.509845279
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.68650851
Short name T1820
Test name
Test status
Simulation time 79508667 ps
CPU time 1.29 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 211452 kb
Host smart-5c178e81-e8a1-40ac-bbe2-951b1f87b3e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68650851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_s
ame_csr_outstanding.68650851
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1765692472
Short name T1862
Test name
Test status
Simulation time 79788181 ps
CPU time 2.45 seconds
Started Mar 24 01:04:44 PM PDT 24
Finished Mar 24 01:04:47 PM PDT 24
Peak memory 217780 kb
Host smart-7bc16d85-88dd-4b4a-9deb-789acf3aa083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765692472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1765692472
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3622556074
Short name T1979
Test name
Test status
Simulation time 205972276 ps
CPU time 3.36 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 217672 kb
Host smart-b7f3b2f3-240e-4cff-8a3b-406fd9e59a42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622556074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3622556074
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1209669295
Short name T174
Test name
Test status
Simulation time 569630112 ps
CPU time 4.67 seconds
Started Mar 24 01:04:44 PM PDT 24
Finished Mar 24 01:04:49 PM PDT 24
Peak memory 217644 kb
Host smart-2cb59cb7-47bf-46d6-ad82-fa544adba9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209669295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1209669295
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1637028167
Short name T1794
Test name
Test status
Simulation time 31767765 ps
CPU time 1.4 seconds
Started Mar 24 01:04:48 PM PDT 24
Finished Mar 24 01:04:50 PM PDT 24
Peak memory 219384 kb
Host smart-a7e308dd-170e-47f7-9849-59e4ff8e39ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637028167 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1637028167
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1687701078
Short name T1956
Test name
Test status
Simulation time 22399253 ps
CPU time 1.21 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:31 PM PDT 24
Peak memory 217764 kb
Host smart-c24aa0fc-4db4-4f64-a16a-8a5e113c981c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687701078 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1687701078
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.564526778
Short name T237
Test name
Test status
Simulation time 19027492 ps
CPU time 1.15 seconds
Started Mar 24 12:42:24 PM PDT 24
Finished Mar 24 12:42:26 PM PDT 24
Peak memory 209232 kb
Host smart-ff25a7df-7165-4a54-ae9f-fbde4be4a68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564526778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.564526778
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.779407420
Short name T1734
Test name
Test status
Simulation time 72989010 ps
CPU time 1.07 seconds
Started Mar 24 01:04:50 PM PDT 24
Finished Mar 24 01:04:52 PM PDT 24
Peak memory 209356 kb
Host smart-7878ae6c-6b7f-4816-bbf9-fa5b9d213c7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779407420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.779407420
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1062949682
Short name T1711
Test name
Test status
Simulation time 56385064 ps
CPU time 1.28 seconds
Started Mar 24 01:04:48 PM PDT 24
Finished Mar 24 01:04:50 PM PDT 24
Peak memory 209336 kb
Host smart-488fe615-9b2d-42e0-b31d-d42803c85bad
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062949682 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1062949682
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3287274854
Short name T1760
Test name
Test status
Simulation time 40255282 ps
CPU time 1.26 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:35 PM PDT 24
Peak memory 209212 kb
Host smart-67f10697-3c28-41a7-8523-6fde5195bf6d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287274854 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3287274854
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1878184672
Short name T1815
Test name
Test status
Simulation time 224171170 ps
CPU time 6.01 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:47 PM PDT 24
Peak memory 209076 kb
Host smart-107edb04-5d64-43f0-9b00-cc8395982fe0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878184672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1878184672
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.437979403
Short name T177
Test name
Test status
Simulation time 433614224 ps
CPU time 4.84 seconds
Started Mar 24 01:04:48 PM PDT 24
Finished Mar 24 01:04:53 PM PDT 24
Peak memory 209164 kb
Host smart-bca692cf-8d17-479a-b7ed-c64ee01d241a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437979403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.437979403
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4099974206
Short name T1988
Test name
Test status
Simulation time 1092726032 ps
CPU time 5.57 seconds
Started Mar 24 01:04:46 PM PDT 24
Finished Mar 24 01:04:52 PM PDT 24
Peak memory 209056 kb
Host smart-6ea5327b-db42-4c37-806b-ae2f0f2e9207
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099974206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4099974206
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.966652025
Short name T1796
Test name
Test status
Simulation time 14485008524 ps
CPU time 15.57 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 209236 kb
Host smart-cb4c98e8-eff7-4402-9084-8f71d7ee95d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966652025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.966652025
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2151502284
Short name T1869
Test name
Test status
Simulation time 239781890 ps
CPU time 1.85 seconds
Started Mar 24 01:04:47 PM PDT 24
Finished Mar 24 01:04:50 PM PDT 24
Peak memory 210532 kb
Host smart-4149702c-e9e9-4679-aac6-e36211672b23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151502284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2151502284
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3144116629
Short name T1818
Test name
Test status
Simulation time 185184591 ps
CPU time 2.53 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 210768 kb
Host smart-e3dd0384-337a-46ff-911c-7ab122edee0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144116629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3144116629
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2834105792
Short name T1906
Test name
Test status
Simulation time 131281972 ps
CPU time 2.4 seconds
Started Mar 24 01:04:48 PM PDT 24
Finished Mar 24 01:04:51 PM PDT 24
Peak memory 217692 kb
Host smart-7eed915b-1421-4e2e-9d86-91819b5dbde4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283410
5792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2834105792
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.495268804
Short name T1902
Test name
Test status
Simulation time 1399559708 ps
CPU time 3.4 seconds
Started Mar 24 12:42:16 PM PDT 24
Finished Mar 24 12:42:20 PM PDT 24
Peak memory 218600 kb
Host smart-c34e7ad4-6f57-4b8e-b2cd-c5dcd157c8fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495268
804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.495268804
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2516499439
Short name T1843
Test name
Test status
Simulation time 345851683 ps
CPU time 2.73 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 209580 kb
Host smart-dc9a72a1-c9c5-4068-af69-d4a97341655f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516499439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2516499439
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2564831570
Short name T1873
Test name
Test status
Simulation time 940746246 ps
CPU time 1.74 seconds
Started Mar 24 01:04:50 PM PDT 24
Finished Mar 24 01:04:51 PM PDT 24
Peak memory 209372 kb
Host smart-d4312738-bf6b-4570-94c8-ea8a2ddfb7ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564831570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2564831570
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1780860299
Short name T1830
Test name
Test status
Simulation time 24461219 ps
CPU time 1.06 seconds
Started Mar 24 12:42:26 PM PDT 24
Finished Mar 24 12:42:27 PM PDT 24
Peak memory 209368 kb
Host smart-54d0b9de-b3d9-4511-ac99-5e619b8a8162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780860299 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1780860299
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.940774482
Short name T1946
Test name
Test status
Simulation time 24182170 ps
CPU time 1.09 seconds
Started Mar 24 01:04:49 PM PDT 24
Finished Mar 24 01:04:51 PM PDT 24
Peak memory 209440 kb
Host smart-05f2aed6-4416-4604-9ef5-48cce309e27b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940774482 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.940774482
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2417212111
Short name T1745
Test name
Test status
Simulation time 33510337 ps
CPU time 1.08 seconds
Started Mar 24 12:42:24 PM PDT 24
Finished Mar 24 12:42:26 PM PDT 24
Peak memory 209344 kb
Host smart-c0d89458-78ce-4998-adc3-52c23e28ab44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417212111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2417212111
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2684093636
Short name T1784
Test name
Test status
Simulation time 76328678 ps
CPU time 1.36 seconds
Started Mar 24 01:04:48 PM PDT 24
Finished Mar 24 01:04:50 PM PDT 24
Peak memory 209468 kb
Host smart-23f39399-6fc2-4582-97b1-c4170b116e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684093636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2684093636
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1648411065
Short name T1982
Test name
Test status
Simulation time 79928225 ps
CPU time 2.59 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:37 PM PDT 24
Peak memory 218060 kb
Host smart-f67d61a3-14ac-478d-8585-81f81204cd76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648411065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1648411065
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.922111163
Short name T1865
Test name
Test status
Simulation time 386956994 ps
CPU time 4.31 seconds
Started Mar 24 01:04:49 PM PDT 24
Finished Mar 24 01:04:54 PM PDT 24
Peak memory 217716 kb
Host smart-3bacf846-6990-4d2f-a838-895f35b6bf98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922111163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.922111163
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.12471200
Short name T165
Test name
Test status
Simulation time 383378907 ps
CPU time 2.93 seconds
Started Mar 24 01:04:46 PM PDT 24
Finished Mar 24 01:04:49 PM PDT 24
Peak memory 222168 kb
Host smart-1e8773a7-f199-484d-a8e5-460df0056e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12471200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_er
r.12471200
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1461025224
Short name T139
Test name
Test status
Simulation time 71970791 ps
CPU time 1.36 seconds
Started Mar 24 12:42:10 PM PDT 24
Finished Mar 24 12:42:11 PM PDT 24
Peak memory 217700 kb
Host smart-7992a25a-375b-4fab-bc8c-bcf21032125f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461025224 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1461025224
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3715569542
Short name T1850
Test name
Test status
Simulation time 60801663 ps
CPU time 1.23 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:54 PM PDT 24
Peak memory 218836 kb
Host smart-990476ac-ef60-4123-9534-d7eca85da8f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715569542 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3715569542
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1174872109
Short name T1984
Test name
Test status
Simulation time 73827867 ps
CPU time 1.01 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:42:43 PM PDT 24
Peak memory 209260 kb
Host smart-1d323e0a-8f71-4aa8-894d-a49f6bca8d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174872109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1174872109
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2192832981
Short name T239
Test name
Test status
Simulation time 66424856 ps
CPU time 0.94 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:54 PM PDT 24
Peak memory 217568 kb
Host smart-c019addd-cfd3-4655-bf06-7c432c237bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192832981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2192832981
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2367076840
Short name T1966
Test name
Test status
Simulation time 37300653 ps
CPU time 1.04 seconds
Started Mar 24 01:04:52 PM PDT 24
Finished Mar 24 01:04:53 PM PDT 24
Peak memory 209352 kb
Host smart-4047f586-ea93-4176-b6c7-a23c99fc5533
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367076840 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2367076840
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.792261281
Short name T1878
Test name
Test status
Simulation time 29492048 ps
CPU time 0.96 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 207792 kb
Host smart-903aa1f3-46dd-4264-bd55-1ab7fef69358
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792261281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.792261281
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1917529947
Short name T1761
Test name
Test status
Simulation time 729677003 ps
CPU time 5.11 seconds
Started Mar 24 01:04:50 PM PDT 24
Finished Mar 24 01:04:56 PM PDT 24
Peak memory 209168 kb
Host smart-aa173032-14ef-40b6-984a-93ac7f9a3500
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917529947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1917529947
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.625607972
Short name T1752
Test name
Test status
Simulation time 577889804 ps
CPU time 11.69 seconds
Started Mar 24 12:42:24 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 209116 kb
Host smart-e3eb5fc2-ac35-453e-be2e-30432d6e37e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625607972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.625607972
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2794147746
Short name T1919
Test name
Test status
Simulation time 5743060774 ps
CPU time 11.95 seconds
Started Mar 24 01:04:52 PM PDT 24
Finished Mar 24 01:05:04 PM PDT 24
Peak memory 209348 kb
Host smart-d7fb99ce-fd82-4bd7-b351-ac5433909ccc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794147746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2794147746
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3673353099
Short name T1974
Test name
Test status
Simulation time 4851491996 ps
CPU time 4.99 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 209316 kb
Host smart-4bdfd809-bf5d-473f-83d1-a95f3c4de412
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673353099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3673353099
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1380184421
Short name T1967
Test name
Test status
Simulation time 223748180 ps
CPU time 2.8 seconds
Started Mar 24 01:04:54 PM PDT 24
Finished Mar 24 01:04:57 PM PDT 24
Peak memory 210868 kb
Host smart-fb9ba26f-aaa1-4e0a-ba9e-eabf8d55c1c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380184421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1380184421
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2461681893
Short name T1724
Test name
Test status
Simulation time 525122960 ps
CPU time 1.81 seconds
Started Mar 24 12:42:19 PM PDT 24
Finished Mar 24 12:42:21 PM PDT 24
Peak memory 209204 kb
Host smart-88213a8d-386e-4106-af51-e8d87da655c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461681893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2461681893
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2714531534
Short name T1920
Test name
Test status
Simulation time 188835651 ps
CPU time 3.82 seconds
Started Mar 24 12:42:15 PM PDT 24
Finished Mar 24 12:42:19 PM PDT 24
Peak memory 218644 kb
Host smart-fece21dd-4871-4946-bf2c-0f16bdaf972f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271453
1534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2714531534
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4011381497
Short name T1867
Test name
Test status
Simulation time 178638615 ps
CPU time 4.09 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:58 PM PDT 24
Peak memory 217676 kb
Host smart-ff2e663e-83b1-4663-abbe-dfd1750031de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401138
1497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4011381497
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1343830387
Short name T1927
Test name
Test status
Simulation time 114345315 ps
CPU time 2 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:55 PM PDT 24
Peak memory 209568 kb
Host smart-1c3c9728-57e7-4fd8-a3c3-075159205f9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343830387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1343830387
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.838285903
Short name T1864
Test name
Test status
Simulation time 51697721 ps
CPU time 1.19 seconds
Started Mar 24 12:42:22 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 209276 kb
Host smart-b52b9f17-9973-4ffc-b8f4-b4b72086b826
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838285903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.838285903
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2576342054
Short name T1785
Test name
Test status
Simulation time 60836359 ps
CPU time 1.41 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:54 PM PDT 24
Peak memory 209520 kb
Host smart-100272a6-d582-4542-9217-2bf49e38aa07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576342054 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2576342054
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3950599963
Short name T1762
Test name
Test status
Simulation time 74881215 ps
CPU time 1.45 seconds
Started Mar 24 12:42:20 PM PDT 24
Finished Mar 24 12:42:22 PM PDT 24
Peak memory 211476 kb
Host smart-cb3e4271-c92d-4f7f-a288-7b5d4b102d59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950599963 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3950599963
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2494605631
Short name T1903
Test name
Test status
Simulation time 16445094 ps
CPU time 1.07 seconds
Started Mar 24 01:04:51 PM PDT 24
Finished Mar 24 01:04:52 PM PDT 24
Peak memory 209460 kb
Host smart-d9615ac9-1502-45fa-9b96-1226f627c24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494605631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2494605631
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3325577503
Short name T1973
Test name
Test status
Simulation time 27689048 ps
CPU time 1.23 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:31 PM PDT 24
Peak memory 209308 kb
Host smart-c52fcc47-830e-4102-b46b-30e5bdc35353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325577503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3325577503
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2198422916
Short name T1879
Test name
Test status
Simulation time 528019568 ps
CPU time 3.21 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 217656 kb
Host smart-1d74dfdb-2ac1-4a01-aac4-a67cfc5a329b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198422916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2198422916
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2537529429
Short name T1743
Test name
Test status
Simulation time 448626125 ps
CPU time 3.5 seconds
Started Mar 24 01:04:53 PM PDT 24
Finished Mar 24 01:04:56 PM PDT 24
Peak memory 218280 kb
Host smart-820872e5-3ce9-4f4a-880c-2813b8b70dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537529429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2537529429
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1934617408
Short name T152
Test name
Test status
Simulation time 69689905 ps
CPU time 2.14 seconds
Started Mar 24 12:42:26 PM PDT 24
Finished Mar 24 12:42:29 PM PDT 24
Peak memory 221784 kb
Host smart-7b5f5c71-0f5d-460f-a162-73d79a6e0db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934617408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1934617408
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2225861218
Short name T1996
Test name
Test status
Simulation time 93930366 ps
CPU time 1.88 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:11 PM PDT 24
Peak memory 219520 kb
Host smart-dd29dc09-e49b-4dfc-9f5a-4aa3ae11183c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225861218 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2225861218
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3950794135
Short name T1849
Test name
Test status
Simulation time 17931017 ps
CPU time 1.18 seconds
Started Mar 24 01:05:04 PM PDT 24
Finished Mar 24 01:05:08 PM PDT 24
Peak memory 217712 kb
Host smart-5a3e2df2-ede7-4308-ba97-276bc07da46a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950794135 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.3950794135
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1217751882
Short name T137
Test name
Test status
Simulation time 14761644 ps
CPU time 0.96 seconds
Started Mar 24 01:05:02 PM PDT 24
Finished Mar 24 01:05:05 PM PDT 24
Peak memory 209376 kb
Host smart-a3c31544-d319-48ec-8119-0210eb044dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217751882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1217751882
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1582637386
Short name T1799
Test name
Test status
Simulation time 27076691 ps
CPU time 1.06 seconds
Started Mar 24 12:42:19 PM PDT 24
Finished Mar 24 12:42:21 PM PDT 24
Peak memory 209248 kb
Host smart-197bb3a5-39b3-44a0-97b6-171a0f6b9b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582637386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1582637386
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2107227892
Short name T1895
Test name
Test status
Simulation time 149665730 ps
CPU time 1.09 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:42:35 PM PDT 24
Peak memory 207864 kb
Host smart-44facc8a-1efd-4a74-ab03-1d824a7d5a19
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107227892 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2107227892
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2907591551
Short name T179
Test name
Test status
Simulation time 43568781 ps
CPU time 1.18 seconds
Started Mar 24 01:04:56 PM PDT 24
Finished Mar 24 01:04:58 PM PDT 24
Peak memory 209312 kb
Host smart-52ba3b90-cdb6-451b-9bfb-adb230b8b453
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907591551 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2907591551
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2070360486
Short name T1751
Test name
Test status
Simulation time 895603034 ps
CPU time 4.26 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 209020 kb
Host smart-7811add3-576b-4c58-91e7-a60b5b6990e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070360486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2070360486
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2784952995
Short name T1986
Test name
Test status
Simulation time 292838878 ps
CPU time 3.61 seconds
Started Mar 24 01:04:56 PM PDT 24
Finished Mar 24 01:05:00 PM PDT 24
Peak memory 209164 kb
Host smart-1b73ceaa-5bbc-46fb-ae77-c2358ba1f084
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784952995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2784952995
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2108139200
Short name T1790
Test name
Test status
Simulation time 3206764149 ps
CPU time 14.62 seconds
Started Mar 24 01:04:58 PM PDT 24
Finished Mar 24 01:05:13 PM PDT 24
Peak memory 209432 kb
Host smart-3599cd8a-c693-4917-b9a3-7f2d78eebb6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108139200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2108139200
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3565405970
Short name T1783
Test name
Test status
Simulation time 1493959916 ps
CPU time 5.18 seconds
Started Mar 24 12:42:29 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 209060 kb
Host smart-2f3eaf91-2e0d-4d59-991b-21685511d787
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565405970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3565405970
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2631398206
Short name T1779
Test name
Test status
Simulation time 57076804 ps
CPU time 1.95 seconds
Started Mar 24 12:42:28 PM PDT 24
Finished Mar 24 12:42:30 PM PDT 24
Peak memory 210816 kb
Host smart-576a3a37-63a5-4543-8fd1-b1299a872c77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631398206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2631398206
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3554522097
Short name T1941
Test name
Test status
Simulation time 226323893 ps
CPU time 3.37 seconds
Started Mar 24 01:05:00 PM PDT 24
Finished Mar 24 01:05:04 PM PDT 24
Peak memory 210988 kb
Host smart-4017f9e8-65e4-45e4-b86f-dcbfccaf8d9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554522097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3554522097
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3689140178
Short name T1829
Test name
Test status
Simulation time 114221955 ps
CPU time 2.63 seconds
Started Mar 24 12:42:26 PM PDT 24
Finished Mar 24 12:42:30 PM PDT 24
Peak memory 219104 kb
Host smart-f00107db-ea23-4d5b-8be6-829a59a1b505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368914
0178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3689140178
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.554620755
Short name T1767
Test name
Test status
Simulation time 459786622 ps
CPU time 2.12 seconds
Started Mar 24 01:05:05 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 217732 kb
Host smart-3db76d40-676d-4799-8a7f-3f134de6fd59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554620
755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.554620755
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2756005349
Short name T1890
Test name
Test status
Simulation time 163522378 ps
CPU time 2.5 seconds
Started Mar 24 01:04:57 PM PDT 24
Finished Mar 24 01:05:00 PM PDT 24
Peak memory 209388 kb
Host smart-7f3573a1-04bc-4824-aea8-45039c7a4e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756005349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2756005349
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3406755023
Short name T1766
Test name
Test status
Simulation time 241687595 ps
CPU time 1.25 seconds
Started Mar 24 12:42:26 PM PDT 24
Finished Mar 24 12:42:29 PM PDT 24
Peak memory 209388 kb
Host smart-b02e5028-9a68-4bcf-a0f5-25bdb927fa80
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406755023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3406755023
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.520516878
Short name T1947
Test name
Test status
Simulation time 20581882 ps
CPU time 1.31 seconds
Started Mar 24 01:05:00 PM PDT 24
Finished Mar 24 01:05:02 PM PDT 24
Peak memory 209480 kb
Host smart-7acf77f3-091a-412f-867b-1793fcfb5504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520516878 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.520516878
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.705884144
Short name T1781
Test name
Test status
Simulation time 63980709 ps
CPU time 1 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:38 PM PDT 24
Peak memory 209348 kb
Host smart-795855b4-8e7d-4f0d-bdce-556a41e6e8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705884144 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.705884144
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2575333335
Short name T1960
Test name
Test status
Simulation time 19147688 ps
CPU time 1.22 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 211540 kb
Host smart-772383f6-2601-4667-8786-8ce36553685e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575333335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2575333335
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2605718517
Short name T1827
Test name
Test status
Simulation time 174937448 ps
CPU time 1.97 seconds
Started Mar 24 12:42:13 PM PDT 24
Finished Mar 24 12:42:15 PM PDT 24
Peak memory 211304 kb
Host smart-8581675a-094f-4dec-a111-324952c7b694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605718517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2605718517
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1388956902
Short name T1798
Test name
Test status
Simulation time 165116756 ps
CPU time 2.83 seconds
Started Mar 24 01:04:57 PM PDT 24
Finished Mar 24 01:05:00 PM PDT 24
Peak memory 218956 kb
Host smart-b02c125b-d370-4506-9d38-095638f126ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388956902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1388956902
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.223869652
Short name T1814
Test name
Test status
Simulation time 119801197 ps
CPU time 2.46 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 217672 kb
Host smart-1dd5c71b-4490-460b-9331-ba6b44962cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223869652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.223869652
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2265130910
Short name T149
Test name
Test status
Simulation time 58150391 ps
CPU time 1.99 seconds
Started Mar 24 12:42:22 PM PDT 24
Finished Mar 24 12:42:24 PM PDT 24
Peak memory 221252 kb
Host smart-cbf9bb03-4943-4d22-bbe1-06c4623fa459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265130910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2265130910
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.801764624
Short name T173
Test name
Test status
Simulation time 195139296 ps
CPU time 2.84 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 222232 kb
Host smart-d32ee27d-416c-4101-9ea9-53a086eceff5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801764624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.801764624
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3751911466
Short name T1975
Test name
Test status
Simulation time 521782257 ps
CPU time 1.43 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:37 PM PDT 24
Peak memory 222112 kb
Host smart-0ec126e0-497f-469b-ab04-c4b02b65f52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751911466 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3751911466
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4039318407
Short name T1944
Test name
Test status
Simulation time 207754902 ps
CPU time 2.02 seconds
Started Mar 24 01:05:03 PM PDT 24
Finished Mar 24 01:05:07 PM PDT 24
Peak memory 219872 kb
Host smart-4e7e9e22-cbfc-4ca0-90bf-6f4e900c2ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039318407 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4039318407
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2700081963
Short name T246
Test name
Test status
Simulation time 42877945 ps
CPU time 1 seconds
Started Mar 24 12:42:28 PM PDT 24
Finished Mar 24 12:42:29 PM PDT 24
Peak memory 209252 kb
Host smart-d8c7595b-5e1d-4994-b86e-ce9ffb860835
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700081963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2700081963
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3108154114
Short name T1877
Test name
Test status
Simulation time 37773264 ps
CPU time 0.86 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:08 PM PDT 24
Peak memory 209228 kb
Host smart-00edb2fb-080f-4ac7-ab69-a87fea5cbed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108154114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3108154114
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3902964835
Short name T1718
Test name
Test status
Simulation time 58561252 ps
CPU time 0.91 seconds
Started Mar 24 01:05:05 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209352 kb
Host smart-5c76cc05-d05a-479a-9eac-98183024bbb0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902964835 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3902964835
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.93257848
Short name T1928
Test name
Test status
Simulation time 37124649 ps
CPU time 1.54 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:19 PM PDT 24
Peak memory 207928 kb
Host smart-d03e930b-35d8-4f9b-9278-b851591aee95
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93257848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_alert_test.93257848
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3217620084
Short name T135
Test name
Test status
Simulation time 2449687530 ps
CPU time 11.08 seconds
Started Mar 24 12:42:21 PM PDT 24
Finished Mar 24 12:42:32 PM PDT 24
Peak memory 208576 kb
Host smart-f81b4b93-b2d6-4c26-8a68-0fbeb4e0e668
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217620084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3217620084
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4019992611
Short name T1930
Test name
Test status
Simulation time 572757038 ps
CPU time 13.82 seconds
Started Mar 24 01:05:05 PM PDT 24
Finished Mar 24 01:05:21 PM PDT 24
Peak memory 208808 kb
Host smart-2354316b-2ac3-44f9-a36e-d7e451c51818
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019992611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4019992611
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3522466930
Short name T1992
Test name
Test status
Simulation time 613503882 ps
CPU time 6.21 seconds
Started Mar 24 01:05:03 PM PDT 24
Finished Mar 24 01:05:11 PM PDT 24
Peak memory 208412 kb
Host smart-0b80e618-f897-4e16-8e80-9c9dd8efa34e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522466930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3522466930
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3564666741
Short name T1884
Test name
Test status
Simulation time 3236911012 ps
CPU time 7.19 seconds
Started Mar 24 12:42:21 PM PDT 24
Finished Mar 24 12:42:29 PM PDT 24
Peak memory 209224 kb
Host smart-a46aab39-a743-4acf-9a11-80743a436c06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564666741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3564666741
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.237293643
Short name T1978
Test name
Test status
Simulation time 91698073 ps
CPU time 3.03 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 210988 kb
Host smart-eb8d6109-afce-4c83-a196-815c8bc6fed7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237293643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.237293643
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2639927877
Short name T1848
Test name
Test status
Simulation time 357301191 ps
CPU time 1.72 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 210860 kb
Host smart-f8e35364-84f0-40af-b96b-66972d502cb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639927877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2639927877
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3693836697
Short name T1758
Test name
Test status
Simulation time 176379415 ps
CPU time 5.48 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:23 PM PDT 24
Peak memory 218664 kb
Host smart-78ad82eb-f69b-4eed-9501-8f33955b98ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369383
6697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3693836697
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4070202742
Short name T1847
Test name
Test status
Simulation time 462819912 ps
CPU time 3.23 seconds
Started Mar 24 01:05:03 PM PDT 24
Finished Mar 24 01:05:08 PM PDT 24
Peak memory 222124 kb
Host smart-b96bc77e-bf69-4d3c-b331-3f0f21a18005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407020
2742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4070202742
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.417882787
Short name T1885
Test name
Test status
Simulation time 295156477 ps
CPU time 1.96 seconds
Started Mar 24 01:05:04 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209384 kb
Host smart-9bf725d1-492e-42fd-a85e-c0e4ab1ccd65
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417882787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.417882787
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.951677985
Short name T1722
Test name
Test status
Simulation time 200639603 ps
CPU time 1.86 seconds
Started Mar 24 12:42:30 PM PDT 24
Finished Mar 24 12:42:32 PM PDT 24
Peak memory 208488 kb
Host smart-db5084e3-abcc-4040-b755-9a33ffeff35a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951677985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.951677985
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2141893245
Short name T254
Test name
Test status
Simulation time 90093514 ps
CPU time 1.33 seconds
Started Mar 24 12:42:31 PM PDT 24
Finished Mar 24 12:42:33 PM PDT 24
Peak memory 209372 kb
Host smart-c0b733c3-1c8e-4e5a-be5d-4c6578c5dfac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141893245 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2141893245
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2666918605
Short name T1970
Test name
Test status
Simulation time 29612524 ps
CPU time 1.24 seconds
Started Mar 24 01:05:02 PM PDT 24
Finished Mar 24 01:05:04 PM PDT 24
Peak memory 209500 kb
Host smart-60ff6e25-61ee-438f-ae12-9581f197b1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666918605 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2666918605
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3565018340
Short name T1908
Test name
Test status
Simulation time 426302452 ps
CPU time 1.04 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209416 kb
Host smart-984dbcb3-7b23-4bb9-9734-4b6e45686db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565018340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3565018340
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.797713738
Short name T1801
Test name
Test status
Simulation time 26835963 ps
CPU time 1.46 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:19 PM PDT 24
Peak memory 209328 kb
Host smart-62f58ee5-e9c7-4611-b937-082a52f25569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797713738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.797713738
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1298481093
Short name T1756
Test name
Test status
Simulation time 176483278 ps
CPU time 3.06 seconds
Started Mar 24 01:05:04 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 217860 kb
Host smart-db24c161-ceb3-4563-a30b-7104892c3f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298481093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1298481093
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3012045909
Short name T1793
Test name
Test status
Simulation time 621705535 ps
CPU time 5.54 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 217660 kb
Host smart-479dc7e3-313d-4a4f-b11c-fb808cb1da5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012045909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3012045909
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.125372607
Short name T1917
Test name
Test status
Simulation time 350172399 ps
CPU time 2.75 seconds
Started Mar 24 01:05:05 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 222552 kb
Host smart-430440f1-28f7-43af-83b5-eeab57c5497d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125372607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.125372607
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3404271135
Short name T1945
Test name
Test status
Simulation time 21518359 ps
CPU time 1.37 seconds
Started Mar 24 01:05:07 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 219300 kb
Host smart-65d7ba9d-f0a9-473a-b403-5cc072cb3fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404271135 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3404271135
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.4014948251
Short name T1725
Test name
Test status
Simulation time 42947900 ps
CPU time 1.83 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 223364 kb
Host smart-b05a1d9b-7556-48d2-9fec-b4b7d2892398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014948251 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.4014948251
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1585658676
Short name T242
Test name
Test status
Simulation time 12451531 ps
CPU time 0.99 seconds
Started Mar 24 12:42:22 PM PDT 24
Finished Mar 24 12:42:23 PM PDT 24
Peak memory 208844 kb
Host smart-73c21323-95f3-4611-bace-8db2e242cf34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585658676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1585658676
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2366938521
Short name T1828
Test name
Test status
Simulation time 25353922 ps
CPU time 0.87 seconds
Started Mar 24 01:05:08 PM PDT 24
Finished Mar 24 01:05:10 PM PDT 24
Peak memory 209368 kb
Host smart-1cc796d6-4878-4bad-bc57-c7ec849425f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366938521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2366938521
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2788216740
Short name T1872
Test name
Test status
Simulation time 451974501 ps
CPU time 1.68 seconds
Started Mar 24 01:05:03 PM PDT 24
Finished Mar 24 01:05:07 PM PDT 24
Peak memory 209308 kb
Host smart-b7d08523-943d-4019-ae77-0f251c8ba91e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788216740 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2788216740
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3292748424
Short name T178
Test name
Test status
Simulation time 144917890 ps
CPU time 1.02 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 209240 kb
Host smart-ad8b6690-1be6-4545-80ff-aafb4ce118ff
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292748424 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3292748424
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2545207637
Short name T1804
Test name
Test status
Simulation time 2468653386 ps
CPU time 15.32 seconds
Started Mar 24 12:42:18 PM PDT 24
Finished Mar 24 12:42:34 PM PDT 24
Peak memory 209360 kb
Host smart-5a673c9e-f787-4840-9a1f-d597eb2f1899
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545207637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2545207637
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.477671118
Short name T1866
Test name
Test status
Simulation time 1511944645 ps
CPU time 4.54 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:12 PM PDT 24
Peak memory 209192 kb
Host smart-5ebd8116-6dfe-43a6-a426-b836c1790780
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477671118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.477671118
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1624933885
Short name T180
Test name
Test status
Simulation time 952429266 ps
CPU time 23.04 seconds
Started Mar 24 01:05:01 PM PDT 24
Finished Mar 24 01:05:26 PM PDT 24
Peak memory 209176 kb
Host smart-33253c4e-8c63-475f-8f70-84bf68041da2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624933885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1624933885
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3322167188
Short name T1807
Test name
Test status
Simulation time 535706521 ps
CPU time 5.09 seconds
Started Mar 24 12:42:11 PM PDT 24
Finished Mar 24 12:42:16 PM PDT 24
Peak memory 208936 kb
Host smart-3383f733-8d98-4411-b9f6-557062d55c1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322167188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3322167188
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3253744281
Short name T1712
Test name
Test status
Simulation time 50650134 ps
CPU time 1.27 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:36 PM PDT 24
Peak memory 210576 kb
Host smart-e5e6e87f-ebad-49aa-a7d9-46bcc030eec9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253744281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3253744281
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3373080067
Short name T1842
Test name
Test status
Simulation time 52112574 ps
CPU time 1.44 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 210752 kb
Host smart-416eb857-0c9d-4742-ba02-b548bbd3aa89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373080067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3373080067
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2255408955
Short name T1883
Test name
Test status
Simulation time 543522730 ps
CPU time 4 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:38 PM PDT 24
Peak memory 217716 kb
Host smart-d5164d2a-d55b-40f8-a2b1-31e624cf39b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225540
8955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2255408955
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2951585413
Short name T1900
Test name
Test status
Simulation time 465282760 ps
CPU time 1.43 seconds
Started Mar 24 01:05:04 PM PDT 24
Finished Mar 24 01:05:06 PM PDT 24
Peak memory 219108 kb
Host smart-45aa93a4-981e-466d-b7e9-db48cddef024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295158
5413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2951585413
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3413113840
Short name T1957
Test name
Test status
Simulation time 111567108 ps
CPU time 1.91 seconds
Started Mar 24 01:05:03 PM PDT 24
Finished Mar 24 01:05:07 PM PDT 24
Peak memory 209388 kb
Host smart-60d37477-7adf-4869-9c7b-6eed0bb4ad33
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413113840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3413113840
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3912618490
Short name T1742
Test name
Test status
Simulation time 980116831 ps
CPU time 4.6 seconds
Started Mar 24 12:42:22 PM PDT 24
Finished Mar 24 12:42:27 PM PDT 24
Peak memory 209292 kb
Host smart-e9b572b2-af7c-4430-9d33-68fb7308499e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912618490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3912618490
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1656226934
Short name T1949
Test name
Test status
Simulation time 50140842 ps
CPU time 1 seconds
Started Mar 24 12:42:28 PM PDT 24
Finished Mar 24 12:42:29 PM PDT 24
Peak memory 209396 kb
Host smart-0295d82c-5fe0-4551-aef0-2df00eeb1461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656226934 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1656226934
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4013915357
Short name T1995
Test name
Test status
Simulation time 52091392 ps
CPU time 1.45 seconds
Started Mar 24 01:05:05 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209120 kb
Host smart-be7ae9a7-11e0-4f3a-9ff5-361ad12e392a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013915357 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4013915357
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2646297827
Short name T260
Test name
Test status
Simulation time 214382283 ps
CPU time 1.29 seconds
Started Mar 24 01:05:06 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 209444 kb
Host smart-5b7529a9-615d-47db-8e9f-857256f0ac53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646297827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2646297827
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3995219032
Short name T1773
Test name
Test status
Simulation time 21683942 ps
CPU time 1.43 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 209340 kb
Host smart-d9bbafce-06be-4206-b22f-5b07226d7610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995219032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3995219032
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1889320668
Short name T1811
Test name
Test status
Simulation time 501430954 ps
CPU time 3.08 seconds
Started Mar 24 12:42:23 PM PDT 24
Finished Mar 24 12:42:27 PM PDT 24
Peak memory 217772 kb
Host smart-4a5887e6-9672-45ea-a5a9-df4ce9ff603f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889320668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1889320668
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.881835854
Short name T1808
Test name
Test status
Simulation time 120928162 ps
CPU time 3.27 seconds
Started Mar 24 01:05:03 PM PDT 24
Finished Mar 24 01:05:08 PM PDT 24
Peak memory 217876 kb
Host smart-831f5775-cbcb-43cd-b50d-6e7492909af7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881835854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.881835854
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3820947310
Short name T132
Test name
Test status
Simulation time 127529856 ps
CPU time 3.38 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:37 PM PDT 24
Peak memory 222016 kb
Host smart-1fb55b24-3063-49e7-a204-3c0676dd1b33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820947310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3820947310
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.527895651
Short name T156
Test name
Test status
Simulation time 199134533 ps
CPU time 1.9 seconds
Started Mar 24 01:05:01 PM PDT 24
Finished Mar 24 01:05:06 PM PDT 24
Peak memory 221964 kb
Host smart-af1ca124-0357-4a73-b9a8-f9cb8fff6d53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527895651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.527895651
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1657394042
Short name T371
Test name
Test status
Simulation time 41217736 ps
CPU time 1.31 seconds
Started Mar 24 01:54:37 PM PDT 24
Finished Mar 24 01:54:39 PM PDT 24
Peak memory 209960 kb
Host smart-0104ecb8-0069-4f1c-b5f4-a6355cbcb468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657394042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1657394042
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3623182012
Short name T816
Test name
Test status
Simulation time 45904699 ps
CPU time 1.26 seconds
Started Mar 24 02:34:42 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 209952 kb
Host smart-94a1b6c7-8d05-46ed-baa5-ef4bf1a4aedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623182012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3623182012
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3138166201
Short name T1348
Test name
Test status
Simulation time 54374088 ps
CPU time 0.9 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:33 PM PDT 24
Peak memory 209992 kb
Host smart-271503a3-d3da-45a0-8fd4-5d77940e1e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138166201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3138166201
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3697495070
Short name T1463
Test name
Test status
Simulation time 25830959 ps
CPU time 0.78 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:53 PM PDT 24
Peak memory 209864 kb
Host smart-72e4a594-1a58-44b0-ac76-c552e002e07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697495070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3697495070
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1476117118
Short name T1071
Test name
Test status
Simulation time 303717111 ps
CPU time 10.3 seconds
Started Mar 24 01:54:33 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 218500 kb
Host smart-1259ae31-a228-4846-b34b-d8f7a6f92e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476117118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1476117118
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.781249962
Short name T1461
Test name
Test status
Simulation time 3133238848 ps
CPU time 14.34 seconds
Started Mar 24 02:34:37 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 219536 kb
Host smart-ed26cfd2-b0ed-4987-97ec-4b71eb420564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781249962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.781249962
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.136215319
Short name T1347
Test name
Test status
Simulation time 785788568 ps
CPU time 17.62 seconds
Started Mar 24 01:54:33 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 210012 kb
Host smart-611a0071-c2da-4d0b-98bc-94d562d496b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136215319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.136215319
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2598691235
Short name T1207
Test name
Test status
Simulation time 2438981361 ps
CPU time 3.33 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 217808 kb
Host smart-0f8f4625-24eb-4252-bce4-35aac421dd0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598691235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2598691235
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.201709114
Short name T1455
Test name
Test status
Simulation time 13300576071 ps
CPU time 96.67 seconds
Started Mar 24 02:34:46 PM PDT 24
Finished Mar 24 02:36:23 PM PDT 24
Peak memory 220136 kb
Host smart-7da56405-15da-4921-8af7-3a85bf2bee14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201709114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.201709114
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1295224980
Short name T1584
Test name
Test status
Simulation time 309386712 ps
CPU time 3.54 seconds
Started Mar 24 02:34:42 PM PDT 24
Finished Mar 24 02:34:46 PM PDT 24
Peak memory 218232 kb
Host smart-0038d5f6-5470-4d0b-9ac9-a8ba5dd5d15e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295224980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
295224980
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.611563521
Short name T1651
Test name
Test status
Simulation time 321288454 ps
CPU time 8.22 seconds
Started Mar 24 01:54:34 PM PDT 24
Finished Mar 24 01:54:42 PM PDT 24
Peak memory 218276 kb
Host smart-22dda31b-1534-439e-855a-4731094134f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611563521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.611563521
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.199989832
Short name T1508
Test name
Test status
Simulation time 892009657 ps
CPU time 11.78 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:04 PM PDT 24
Peak memory 218536 kb
Host smart-cb350094-6555-4e0a-bb36-419500a546fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199989832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.199989832
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2892334553
Short name T1305
Test name
Test status
Simulation time 402057366 ps
CPU time 6.53 seconds
Started Mar 24 01:54:36 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 218564 kb
Host smart-15e484b7-7a30-4bce-9a64-f37344a38a07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892334553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2892334553
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1248886339
Short name T467
Test name
Test status
Simulation time 1259417159 ps
CPU time 34.2 seconds
Started Mar 24 02:34:41 PM PDT 24
Finished Mar 24 02:35:15 PM PDT 24
Peak memory 213736 kb
Host smart-0e0aba85-e25a-453d-9e98-82c5c50bdb5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248886339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1248886339
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1933566519
Short name T1439
Test name
Test status
Simulation time 6744430858 ps
CPU time 17.7 seconds
Started Mar 24 01:54:31 PM PDT 24
Finished Mar 24 01:54:50 PM PDT 24
Peak memory 214440 kb
Host smart-5bd383c6-cd82-4dc3-901b-3a3521faee9d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933566519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1933566519
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1468330611
Short name T914
Test name
Test status
Simulation time 1824448960 ps
CPU time 6.67 seconds
Started Mar 24 01:54:33 PM PDT 24
Finished Mar 24 01:54:40 PM PDT 24
Peak memory 214352 kb
Host smart-57258ea0-f90f-46f4-9962-501f49094f0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468330611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1468330611
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.31895168
Short name T509
Test name
Test status
Simulation time 320007353 ps
CPU time 3.52 seconds
Started Mar 24 02:34:42 PM PDT 24
Finished Mar 24 02:34:46 PM PDT 24
Peak memory 213796 kb
Host smart-6f6203bf-d38d-44ee-b125-50153c09cc6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31895168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.31895168
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1545871869
Short name T1672
Test name
Test status
Simulation time 4842909639 ps
CPU time 85.91 seconds
Started Mar 24 02:34:42 PM PDT 24
Finished Mar 24 02:36:09 PM PDT 24
Peak memory 283128 kb
Host smart-07d11aa4-a4b7-48e3-ab63-39f5f24ab648
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545871869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1545871869
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3022582406
Short name T689
Test name
Test status
Simulation time 1576890631 ps
CPU time 37.2 seconds
Started Mar 24 01:54:34 PM PDT 24
Finished Mar 24 01:55:11 PM PDT 24
Peak memory 267888 kb
Host smart-f06f0a55-362b-43b2-a166-ce20e966d759
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022582406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3022582406
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2874920744
Short name T992
Test name
Test status
Simulation time 1867348914 ps
CPU time 17.75 seconds
Started Mar 24 01:54:33 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 250920 kb
Host smart-3c0699cc-700d-4f88-a6d9-9f963294a06c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874920744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2874920744
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3213110077
Short name T1701
Test name
Test status
Simulation time 2482368623 ps
CPU time 10.9 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:03 PM PDT 24
Peak memory 225292 kb
Host smart-fc0200be-94be-4e92-aca9-80473886bd20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213110077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3213110077
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3423625264
Short name T514
Test name
Test status
Simulation time 74825452 ps
CPU time 1.73 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:34 PM PDT 24
Peak memory 218568 kb
Host smart-7121480f-eab4-4773-a5d9-f5806702c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423625264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3423625264
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3643087398
Short name T669
Test name
Test status
Simulation time 291550618 ps
CPU time 2.35 seconds
Started Mar 24 02:34:40 PM PDT 24
Finished Mar 24 02:34:42 PM PDT 24
Peak memory 218652 kb
Host smart-92ee5e43-b9c6-4283-9730-35af217a3ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643087398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3643087398
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4159621996
Short name T527
Test name
Test status
Simulation time 412974895 ps
CPU time 11 seconds
Started Mar 24 02:34:47 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 214412 kb
Host smart-80e4902e-b080-4bce-ab1c-393b1552dcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159621996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4159621996
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4278664112
Short name T1185
Test name
Test status
Simulation time 284623715 ps
CPU time 10.67 seconds
Started Mar 24 01:54:31 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 218412 kb
Host smart-ed3f3b83-5171-4c59-81fd-ea691891c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278664112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4278664112
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2768657020
Short name T87
Test name
Test status
Simulation time 392158800 ps
CPU time 25.18 seconds
Started Mar 24 01:54:35 PM PDT 24
Finished Mar 24 01:55:00 PM PDT 24
Peak memory 267648 kb
Host smart-5eb57f42-4c65-48f8-969a-5f2c784b2711
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768657020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2768657020
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3269402360
Short name T117
Test name
Test status
Simulation time 461696106 ps
CPU time 25.95 seconds
Started Mar 24 02:34:44 PM PDT 24
Finished Mar 24 02:35:10 PM PDT 24
Peak memory 284884 kb
Host smart-2bc5a947-2578-4552-9855-579567893cf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269402360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3269402360
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2722154887
Short name T1029
Test name
Test status
Simulation time 276390896 ps
CPU time 15.05 seconds
Started Mar 24 02:34:44 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 219488 kb
Host smart-fc406084-db71-4544-9332-53e6963fa050
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722154887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2722154887
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.635565965
Short name T506
Test name
Test status
Simulation time 643858979 ps
CPU time 13.46 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:46 PM PDT 24
Peak memory 218528 kb
Host smart-463c899c-c7b2-4d7c-adfb-a3ad6e9904a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635565965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.635565965
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.144242028
Short name T1272
Test name
Test status
Simulation time 1247526945 ps
CPU time 9.77 seconds
Started Mar 24 01:54:31 PM PDT 24
Finished Mar 24 01:54:41 PM PDT 24
Peak memory 218564 kb
Host smart-1da42fae-e032-4ae4-bf99-974a46ef9730
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144242028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.144242028
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.236836520
Short name T1346
Test name
Test status
Simulation time 321891253 ps
CPU time 12.59 seconds
Started Mar 24 02:34:47 PM PDT 24
Finished Mar 24 02:35:01 PM PDT 24
Peak memory 218684 kb
Host smart-b8c0dcce-fbdc-448d-9405-8379166dcb38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236836520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.236836520
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2960935072
Short name T583
Test name
Test status
Simulation time 970346851 ps
CPU time 10.05 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:42 PM PDT 24
Peak memory 218588 kb
Host smart-c680b135-593d-487b-905f-98c3d610805d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960935072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
960935072
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.349286181
Short name T473
Test name
Test status
Simulation time 940850608 ps
CPU time 15.89 seconds
Started Mar 24 02:34:40 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 218656 kb
Host smart-ca4524a7-6937-4a4a-9d4c-2d64e61082d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349286181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.349286181
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3013872869
Short name T60
Test name
Test status
Simulation time 2080945576 ps
CPU time 10.58 seconds
Started Mar 24 02:34:40 PM PDT 24
Finished Mar 24 02:34:51 PM PDT 24
Peak memory 226608 kb
Host smart-1d99f721-2306-4053-af60-cbfd3cd62ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013872869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3013872869
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.433885761
Short name T1544
Test name
Test status
Simulation time 361552198 ps
CPU time 14.2 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:47 PM PDT 24
Peak memory 225488 kb
Host smart-bfb27508-994e-4b6b-9db3-e659b10a9cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433885761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.433885761
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1571730614
Short name T1069
Test name
Test status
Simulation time 133316959 ps
CPU time 2.36 seconds
Started Mar 24 02:34:40 PM PDT 24
Finished Mar 24 02:34:42 PM PDT 24
Peak memory 218248 kb
Host smart-520c206a-4283-424b-a995-956bdbd4f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571730614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1571730614
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.4177509558
Short name T751
Test name
Test status
Simulation time 46336043 ps
CPU time 1.76 seconds
Started Mar 24 01:54:33 PM PDT 24
Finished Mar 24 01:54:35 PM PDT 24
Peak memory 218372 kb
Host smart-01629073-97a9-4aaf-8dfb-6b013f1ca460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177509558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.4177509558
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.355757851
Short name T1405
Test name
Test status
Simulation time 1110944144 ps
CPU time 28.51 seconds
Started Mar 24 02:34:37 PM PDT 24
Finished Mar 24 02:35:05 PM PDT 24
Peak memory 251468 kb
Host smart-834f788b-1698-4a12-9569-005724463d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355757851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.355757851
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.743108220
Short name T908
Test name
Test status
Simulation time 2342663445 ps
CPU time 25.05 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:57 PM PDT 24
Peak memory 251468 kb
Host smart-18c86051-5198-49a1-b2a2-8ea69abeb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743108220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.743108220
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.301359473
Short name T1212
Test name
Test status
Simulation time 686049623 ps
CPU time 6.05 seconds
Started Mar 24 02:34:43 PM PDT 24
Finished Mar 24 02:34:50 PM PDT 24
Peak memory 250948 kb
Host smart-241220fb-d3f2-4c41-af83-c85270107640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301359473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.301359473
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3866306231
Short name T830
Test name
Test status
Simulation time 173926883 ps
CPU time 2.83 seconds
Started Mar 24 01:54:36 PM PDT 24
Finished Mar 24 01:54:39 PM PDT 24
Peak memory 222548 kb
Host smart-7aeb3c39-1a76-48f4-99ac-4f21d7d74fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866306231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3866306231
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2226736152
Short name T895
Test name
Test status
Simulation time 761419753 ps
CPU time 16.81 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:49 PM PDT 24
Peak memory 218464 kb
Host smart-dd198534-063d-473d-b1b7-60308b93bf10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226736152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2226736152
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3430224135
Short name T947
Test name
Test status
Simulation time 28408547659 ps
CPU time 170.72 seconds
Started Mar 24 02:34:43 PM PDT 24
Finished Mar 24 02:37:34 PM PDT 24
Peak memory 282000 kb
Host smart-8cfb0f4b-eac0-4c1a-a12e-3610b83f7469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430224135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3430224135
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4110141268
Short name T1154
Test name
Test status
Simulation time 65464221096 ps
CPU time 634.54 seconds
Started Mar 24 01:54:35 PM PDT 24
Finished Mar 24 02:05:10 PM PDT 24
Peak memory 522944 kb
Host smart-d06479e8-fb39-4178-9576-b52f8add6611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4110141268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.4110141268
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2458422385
Short name T1382
Test name
Test status
Simulation time 12206349 ps
CPU time 0.78 seconds
Started Mar 24 01:54:31 PM PDT 24
Finished Mar 24 01:54:33 PM PDT 24
Peak memory 209228 kb
Host smart-d342bca6-96c6-4b3f-8fcb-7fa22fcce3aa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458422385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2458422385
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3233243359
Short name T1087
Test name
Test status
Simulation time 25154873 ps
CPU time 0.92 seconds
Started Mar 24 02:34:37 PM PDT 24
Finished Mar 24 02:34:38 PM PDT 24
Peak memory 212036 kb
Host smart-e9e1d917-7b45-46eb-aceb-ea002131b2b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233243359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3233243359
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1630291291
Short name T1066
Test name
Test status
Simulation time 64804877 ps
CPU time 1.04 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:52 PM PDT 24
Peak memory 209976 kb
Host smart-f528c763-dbfa-44d7-81e2-c9a49c58e754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630291291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1630291291
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3083289419
Short name T1059
Test name
Test status
Simulation time 18162830 ps
CPU time 0.94 seconds
Started Mar 24 01:54:40 PM PDT 24
Finished Mar 24 01:54:41 PM PDT 24
Peak memory 209968 kb
Host smart-bd5f9dcc-5df5-4100-a571-d095d8c47bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083289419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3083289419
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1469286201
Short name T888
Test name
Test status
Simulation time 1240322293 ps
CPU time 7.54 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 226616 kb
Host smart-22b57dce-46aa-40f8-b107-31a68aa0a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469286201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1469286201
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.587099842
Short name T706
Test name
Test status
Simulation time 1250865467 ps
CPU time 12.58 seconds
Started Mar 24 01:54:39 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 218544 kb
Host smart-bff71863-f453-4389-8cb0-25f98e2b80ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587099842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.587099842
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2480214365
Short name T1482
Test name
Test status
Simulation time 69041652 ps
CPU time 2.65 seconds
Started Mar 24 02:34:42 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 217420 kb
Host smart-5cdce32e-4094-47c0-9998-8c02af7a813a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480214365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2480214365
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.335715901
Short name T1280
Test name
Test status
Simulation time 170277055 ps
CPU time 1.2 seconds
Started Mar 24 01:54:36 PM PDT 24
Finished Mar 24 01:54:37 PM PDT 24
Peak memory 210044 kb
Host smart-7a52f575-38d4-45e2-bd9c-11e3527a4acb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335715901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.335715901
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1635720324
Short name T924
Test name
Test status
Simulation time 8761046403 ps
CPU time 65.02 seconds
Started Mar 24 01:54:38 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 219492 kb
Host smart-74ea56be-fd97-4df5-8629-31be870e5b61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635720324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1635720324
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2216501779
Short name T1081
Test name
Test status
Simulation time 1744203137 ps
CPU time 29.37 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 218596 kb
Host smart-175c7e86-a597-4b82-ab8a-f154928820b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216501779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2216501779
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1727290914
Short name T378
Test name
Test status
Simulation time 131975395 ps
CPU time 2.44 seconds
Started Mar 24 02:34:41 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 217776 kb
Host smart-23d1a27f-c4bb-4bd7-aa0c-aee639c386ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727290914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
727290914
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2004362572
Short name T1540
Test name
Test status
Simulation time 123584928 ps
CPU time 2.17 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:54:45 PM PDT 24
Peak memory 217676 kb
Host smart-577d8d7b-64f5-4904-8ee7-19abe133f1ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004362572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
004362572
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1566652919
Short name T403
Test name
Test status
Simulation time 134670097 ps
CPU time 2.81 seconds
Started Mar 24 02:34:48 PM PDT 24
Finished Mar 24 02:34:51 PM PDT 24
Peak memory 218596 kb
Host smart-6d06243c-8dc9-4d8c-b240-193b7c90fbcf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566652919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1566652919
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2058254102
Short name T802
Test name
Test status
Simulation time 174449698 ps
CPU time 6.09 seconds
Started Mar 24 01:54:37 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 218568 kb
Host smart-6137d3b3-8859-401a-bbbd-1e842dd74c0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058254102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2058254102
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2019764690
Short name T568
Test name
Test status
Simulation time 3757924188 ps
CPU time 20.73 seconds
Started Mar 24 01:54:41 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 214216 kb
Host smart-7155fef2-3f41-4422-b6d7-363d7fecf133
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019764690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2019764690
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2845568473
Short name T1671
Test name
Test status
Simulation time 600482331 ps
CPU time 9.05 seconds
Started Mar 24 02:34:43 PM PDT 24
Finished Mar 24 02:34:52 PM PDT 24
Peak memory 213500 kb
Host smart-5d96dfc0-dfde-4ef8-92ca-e18e7c66fc0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845568473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2845568473
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3234429804
Short name T1679
Test name
Test status
Simulation time 570909317 ps
CPU time 1.65 seconds
Started Mar 24 02:34:46 PM PDT 24
Finished Mar 24 02:34:48 PM PDT 24
Peak memory 213408 kb
Host smart-ec16082d-0305-4939-af46-144f154703bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234429804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3234429804
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.620267574
Short name T1157
Test name
Test status
Simulation time 1472859152 ps
CPU time 6.9 seconds
Started Mar 24 01:54:37 PM PDT 24
Finished Mar 24 01:54:44 PM PDT 24
Peak memory 214328 kb
Host smart-bc1153bf-71d8-4061-99c4-837dc87a9314
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620267574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.620267574
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2413238052
Short name T630
Test name
Test status
Simulation time 2206691908 ps
CPU time 59.77 seconds
Started Mar 24 01:54:38 PM PDT 24
Finished Mar 24 01:55:38 PM PDT 24
Peak memory 277384 kb
Host smart-089c3649-5a64-4587-aaf8-d0ef13d77889
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413238052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2413238052
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3221529151
Short name T987
Test name
Test status
Simulation time 4166980957 ps
CPU time 58.39 seconds
Started Mar 24 02:34:41 PM PDT 24
Finished Mar 24 02:35:40 PM PDT 24
Peak memory 281012 kb
Host smart-c2281278-a0e8-411d-b286-a2aeaf687d0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221529151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3221529151
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1778819664
Short name T585
Test name
Test status
Simulation time 572251049 ps
CPU time 13 seconds
Started Mar 24 02:34:43 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 247756 kb
Host smart-b5535c00-2516-4b57-979f-52bc226cd3cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778819664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1778819664
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2758199003
Short name T847
Test name
Test status
Simulation time 1197799560 ps
CPU time 15.43 seconds
Started Mar 24 01:54:38 PM PDT 24
Finished Mar 24 01:54:54 PM PDT 24
Peak memory 251532 kb
Host smart-be26050b-8598-4e60-86fb-d41e06bf13bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758199003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2758199003
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.431051009
Short name T1355
Test name
Test status
Simulation time 175390551 ps
CPU time 1.62 seconds
Started Mar 24 01:54:36 PM PDT 24
Finished Mar 24 01:54:38 PM PDT 24
Peak memory 222188 kb
Host smart-b2fffeb3-47ff-4dda-b1cb-0089c2ba3a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431051009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.431051009
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.462739039
Short name T677
Test name
Test status
Simulation time 16489564 ps
CPU time 1.48 seconds
Started Mar 24 02:34:44 PM PDT 24
Finished Mar 24 02:34:45 PM PDT 24
Peak memory 221908 kb
Host smart-e3032e43-b204-48c3-b659-8877263b7dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462739039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.462739039
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2675366306
Short name T1242
Test name
Test status
Simulation time 1030249313 ps
CPU time 15.04 seconds
Started Mar 24 01:54:37 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 214800 kb
Host smart-1b06e295-2057-4dce-b051-463c19f27ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675366306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2675366306
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3901344976
Short name T511
Test name
Test status
Simulation time 400402608 ps
CPU time 9.2 seconds
Started Mar 24 02:34:48 PM PDT 24
Finished Mar 24 02:34:57 PM PDT 24
Peak memory 218156 kb
Host smart-06d012bc-e0ea-4ddc-9c00-3ad5856f1fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901344976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3901344976
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.1276257338
Short name T119
Test name
Test status
Simulation time 522680959 ps
CPU time 24.52 seconds
Started Mar 24 01:54:40 PM PDT 24
Finished Mar 24 01:55:05 PM PDT 24
Peak memory 281332 kb
Host smart-886fb954-337b-47a8-a9f0-4e38bf5ccdca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276257338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.1276257338
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1000823496
Short name T1146
Test name
Test status
Simulation time 1759034050 ps
CPU time 13.33 seconds
Started Mar 24 02:34:50 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 218596 kb
Host smart-ba8ee604-fc41-4238-a8e4-8365e8e0a7e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000823496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1000823496
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1163068417
Short name T401
Test name
Test status
Simulation time 1037560516 ps
CPU time 14.12 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:54:57 PM PDT 24
Peak memory 219460 kb
Host smart-21a08b39-34c2-4502-befc-ba3ac23c39d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163068417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1163068417
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1069641042
Short name T1356
Test name
Test status
Simulation time 484333955 ps
CPU time 13.54 seconds
Started Mar 24 01:54:43 PM PDT 24
Finished Mar 24 01:54:57 PM PDT 24
Peak memory 218780 kb
Host smart-d1174ba1-1730-4d05-83fb-46ade9d5f060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069641042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1069641042
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.3663029124
Short name T801
Test name
Test status
Simulation time 393276366 ps
CPU time 9.37 seconds
Started Mar 24 02:34:45 PM PDT 24
Finished Mar 24 02:34:55 PM PDT 24
Peak memory 218564 kb
Host smart-daad0413-33a2-40f8-808d-51b7c35b393c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663029124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.3663029124
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2979656654
Short name T709
Test name
Test status
Simulation time 639661170 ps
CPU time 12.95 seconds
Started Mar 24 01:54:41 PM PDT 24
Finished Mar 24 01:54:55 PM PDT 24
Peak memory 218580 kb
Host smart-273036bd-c71c-48f3-abe1-420c2c1b9b2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979656654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
979656654
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3110086741
Short name T648
Test name
Test status
Simulation time 1070300153 ps
CPU time 10.91 seconds
Started Mar 24 02:34:45 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 218568 kb
Host smart-f42ac886-fe1e-44ca-b986-4ba3d263113b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110086741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
110086741
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2866862266
Short name T762
Test name
Test status
Simulation time 577155053 ps
CPU time 6.7 seconds
Started Mar 24 01:54:37 PM PDT 24
Finished Mar 24 01:54:45 PM PDT 24
Peak memory 225456 kb
Host smart-32050d7b-4c0d-411a-84a0-5e42be834baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866862266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2866862266
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.419135107
Short name T607
Test name
Test status
Simulation time 534056968 ps
CPU time 10.24 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:03 PM PDT 24
Peak memory 225324 kb
Host smart-4512772d-6cc8-4843-9dde-7181d39a1d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419135107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.419135107
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2079964684
Short name T779
Test name
Test status
Simulation time 101540527 ps
CPU time 2.19 seconds
Started Mar 24 02:34:51 PM PDT 24
Finished Mar 24 02:34:55 PM PDT 24
Peak memory 214676 kb
Host smart-73eea133-fee1-485b-a40c-81b97af0e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079964684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2079964684
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.392269254
Short name T198
Test name
Test status
Simulation time 95185653 ps
CPU time 1.89 seconds
Started Mar 24 01:54:39 PM PDT 24
Finished Mar 24 01:54:42 PM PDT 24
Peak memory 214212 kb
Host smart-4004ed6d-647a-4fec-9c03-ed9745e3275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392269254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.392269254
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3315010126
Short name T1619
Test name
Test status
Simulation time 438586309 ps
CPU time 15.4 seconds
Started Mar 24 01:54:36 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 251520 kb
Host smart-0bbb543b-6699-4c50-a201-38c1494237ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315010126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3315010126
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.570600330
Short name T652
Test name
Test status
Simulation time 405014788 ps
CPU time 25.04 seconds
Started Mar 24 02:34:43 PM PDT 24
Finished Mar 24 02:35:08 PM PDT 24
Peak memory 251504 kb
Host smart-f182e4f3-12ed-4e43-9a32-4c258227a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570600330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.570600330
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1870582016
Short name T903
Test name
Test status
Simulation time 1009788716 ps
CPU time 7.69 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 247080 kb
Host smart-09319eca-19f2-4810-829d-22b130458774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870582016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1870582016
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3616497904
Short name T1562
Test name
Test status
Simulation time 105763853 ps
CPU time 3.31 seconds
Started Mar 24 01:54:35 PM PDT 24
Finished Mar 24 01:54:39 PM PDT 24
Peak memory 222904 kb
Host smart-5bb76add-ce6e-443c-8f97-aa1e17253be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616497904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3616497904
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.17040071
Short name T1062
Test name
Test status
Simulation time 2501698764 ps
CPU time 83.91 seconds
Started Mar 24 01:54:43 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 251580 kb
Host smart-889aaf6e-12bb-4f50-b5a1-344080a36d24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17040071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.lc_ctrl_stress_all.17040071
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2838310157
Short name T975
Test name
Test status
Simulation time 30008615763 ps
CPU time 438.84 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:42:11 PM PDT 24
Peak memory 310708 kb
Host smart-62fb98db-757d-4ae6-b908-339dfc1bb10a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838310157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2838310157
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2486899640
Short name T1622
Test name
Test status
Simulation time 11020251 ps
CPU time 0.9 seconds
Started Mar 24 01:54:34 PM PDT 24
Finished Mar 24 01:54:35 PM PDT 24
Peak memory 209024 kb
Host smart-149cbbe8-2806-4a4a-a513-bc9e21060ad8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486899640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2486899640
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4201698253
Short name T1003
Test name
Test status
Simulation time 21902193 ps
CPU time 0.77 seconds
Started Mar 24 02:34:47 PM PDT 24
Finished Mar 24 02:34:49 PM PDT 24
Peak memory 209024 kb
Host smart-91efa001-2ba0-4f88-b9d9-ea7bae6d4fb5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201698253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.4201698253
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1079982663
Short name T623
Test name
Test status
Simulation time 32207876 ps
CPU time 0.86 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:35:26 PM PDT 24
Peak memory 209924 kb
Host smart-1700d2e4-2d66-47d1-983f-75a72b10a315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079982663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1079982663
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2677557414
Short name T376
Test name
Test status
Simulation time 45831516 ps
CPU time 0.85 seconds
Started Mar 24 01:55:22 PM PDT 24
Finished Mar 24 01:55:23 PM PDT 24
Peak memory 209724 kb
Host smart-1db5a830-3032-4c3b-b507-d7feafb0f15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677557414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2677557414
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3093642081
Short name T970
Test name
Test status
Simulation time 562705774 ps
CPU time 12.24 seconds
Started Mar 24 02:35:21 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 218524 kb
Host smart-d9832ee2-9c04-4185-bf3f-21132b100401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093642081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3093642081
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3703669281
Short name T744
Test name
Test status
Simulation time 278428588 ps
CPU time 14.09 seconds
Started Mar 24 01:55:18 PM PDT 24
Finished Mar 24 01:55:33 PM PDT 24
Peak memory 218864 kb
Host smart-569884e8-be5a-4357-b2ce-40b4b49cb4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703669281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3703669281
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1543836304
Short name T1091
Test name
Test status
Simulation time 215173037 ps
CPU time 5.26 seconds
Started Mar 24 02:35:26 PM PDT 24
Finished Mar 24 02:35:31 PM PDT 24
Peak memory 210024 kb
Host smart-801ffd0c-b94b-4e17-9e82-0e3bf8563466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543836304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1543836304
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1970987320
Short name T1469
Test name
Test status
Simulation time 2983490507 ps
CPU time 7.55 seconds
Started Mar 24 01:55:22 PM PDT 24
Finished Mar 24 01:55:30 PM PDT 24
Peak memory 210084 kb
Host smart-5ad05b5f-2de1-4900-b5cb-7bc9ec22b788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970987320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1970987320
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1789988074
Short name T1575
Test name
Test status
Simulation time 3357784798 ps
CPU time 43.72 seconds
Started Mar 24 01:55:22 PM PDT 24
Finished Mar 24 01:56:06 PM PDT 24
Peak memory 219572 kb
Host smart-6696b911-e3e1-46de-ad95-ff0efb91202c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789988074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1789988074
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2814286106
Short name T880
Test name
Test status
Simulation time 2418821865 ps
CPU time 70.54 seconds
Started Mar 24 02:35:26 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 219596 kb
Host smart-8de71774-a1a1-4c8e-8ed3-d7f64b3e4cfb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814286106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2814286106
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1244967948
Short name T513
Test name
Test status
Simulation time 149682412 ps
CPU time 4.09 seconds
Started Mar 24 01:55:21 PM PDT 24
Finished Mar 24 01:55:25 PM PDT 24
Peak memory 218492 kb
Host smart-a267aec9-97b1-40eb-ada8-85b62e0d38e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244967948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1244967948
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3889666751
Short name T959
Test name
Test status
Simulation time 421938800 ps
CPU time 13.72 seconds
Started Mar 24 02:35:19 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 218552 kb
Host smart-6609f5a1-6891-42b6-8ca8-6142cfa8f6a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889666751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.3889666751
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2431973187
Short name T616
Test name
Test status
Simulation time 83656630 ps
CPU time 2.39 seconds
Started Mar 24 01:55:16 PM PDT 24
Finished Mar 24 01:55:19 PM PDT 24
Peak memory 213528 kb
Host smart-4a654c92-958f-4edf-b678-654b4dcf2989
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431973187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2431973187
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.64455042
Short name T884
Test name
Test status
Simulation time 738125516 ps
CPU time 5.47 seconds
Started Mar 24 02:35:23 PM PDT 24
Finished Mar 24 02:35:28 PM PDT 24
Peak memory 214164 kb
Host smart-96bfc34d-2843-453c-a495-ca41d862fc89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64455042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.64455042
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3366858540
Short name T1273
Test name
Test status
Simulation time 2926116800 ps
CPU time 89.86 seconds
Started Mar 24 02:35:21 PM PDT 24
Finished Mar 24 02:36:51 PM PDT 24
Peak memory 280252 kb
Host smart-6cd8081a-afe9-437a-8f67-8f9c21c4ff14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366858540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3366858540
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.92820362
Short name T489
Test name
Test status
Simulation time 3933833857 ps
CPU time 68.54 seconds
Started Mar 24 01:55:21 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 267920 kb
Host smart-820f5add-146e-4dbe-ba27-aab094316c82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92820362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_state_failure.92820362
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3850113174
Short name T1164
Test name
Test status
Simulation time 430202073 ps
CPU time 19.18 seconds
Started Mar 24 01:55:23 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 251212 kb
Host smart-072a85be-be02-43ce-b821-824cb54158ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850113174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3850113174
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.647230407
Short name T636
Test name
Test status
Simulation time 7783669972 ps
CPU time 19.27 seconds
Started Mar 24 02:35:19 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 251528 kb
Host smart-d9de35e9-13fb-4d8f-a7d1-55b56862265d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647230407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.647230407
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3758801813
Short name T693
Test name
Test status
Simulation time 258768245 ps
CPU time 3.75 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:37 PM PDT 24
Peak memory 222708 kb
Host smart-9e9c922d-8020-44db-9f13-c74b48e31734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758801813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3758801813
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4262792951
Short name T1306
Test name
Test status
Simulation time 160960878 ps
CPU time 2.17 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 222224 kb
Host smart-792dac62-4120-4a8e-b473-e13354360d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262792951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4262792951
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2129552686
Short name T605
Test name
Test status
Simulation time 639338906 ps
CPU time 17.27 seconds
Started Mar 24 02:35:24 PM PDT 24
Finished Mar 24 02:35:41 PM PDT 24
Peak memory 219504 kb
Host smart-e629340e-2120-41aa-8679-be4f2045bae0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129552686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2129552686
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3899881039
Short name T1396
Test name
Test status
Simulation time 226751535 ps
CPU time 9.45 seconds
Started Mar 24 01:55:23 PM PDT 24
Finished Mar 24 01:55:33 PM PDT 24
Peak memory 218660 kb
Host smart-7e0fb40c-503e-4834-b87f-1c7d44d41089
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899881039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3899881039
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1642917336
Short name T548
Test name
Test status
Simulation time 481899245 ps
CPU time 13.64 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 218588 kb
Host smart-3c5aa9d9-b753-47d4-a768-6fb2d7c906ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642917336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1642917336
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.545682733
Short name T795
Test name
Test status
Simulation time 1435368583 ps
CPU time 14.51 seconds
Started Mar 24 01:55:22 PM PDT 24
Finished Mar 24 01:55:36 PM PDT 24
Peak memory 218524 kb
Host smart-049c901f-cfae-44e7-bbd4-d0a6f95d9a80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545682733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.545682733
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2389054499
Short name T1129
Test name
Test status
Simulation time 1961441020 ps
CPU time 11.78 seconds
Started Mar 24 01:55:22 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 218560 kb
Host smart-6dbca999-272e-41ad-a54f-87a97929a13a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389054499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2389054499
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2770722454
Short name T199
Test name
Test status
Simulation time 946841283 ps
CPU time 10.32 seconds
Started Mar 24 02:35:27 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 218560 kb
Host smart-010f9a75-8b60-48ab-a68a-c123dc383dc5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770722454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2770722454
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3068884312
Short name T1296
Test name
Test status
Simulation time 252988482 ps
CPU time 6.11 seconds
Started Mar 24 01:55:17 PM PDT 24
Finished Mar 24 01:55:23 PM PDT 24
Peak memory 224708 kb
Host smart-78c397a6-d03f-4ecc-b10a-ad8432f9b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068884312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3068884312
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3404467325
Short name T761
Test name
Test status
Simulation time 90889105 ps
CPU time 1.5 seconds
Started Mar 24 01:55:16 PM PDT 24
Finished Mar 24 01:55:18 PM PDT 24
Peak memory 214008 kb
Host smart-3188d2db-429e-4ce8-bfc8-90b8cbb6e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404467325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3404467325
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.63367619
Short name T1064
Test name
Test status
Simulation time 94583015 ps
CPU time 6.87 seconds
Started Mar 24 02:35:18 PM PDT 24
Finished Mar 24 02:35:25 PM PDT 24
Peak memory 218400 kb
Host smart-8d4b1082-3557-49a4-89e7-a135cbe67fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63367619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.63367619
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1951215415
Short name T965
Test name
Test status
Simulation time 238038814 ps
CPU time 28.25 seconds
Started Mar 24 01:55:18 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 250860 kb
Host smart-d5b06ab9-5a84-41e2-9f8b-fceaa264372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951215415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1951215415
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3534954456
Short name T619
Test name
Test status
Simulation time 241775856 ps
CPU time 21.32 seconds
Started Mar 24 02:35:20 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 251504 kb
Host smart-fab705c7-a8cf-4fbb-ab12-da81fcfa03aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534954456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3534954456
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2456841195
Short name T638
Test name
Test status
Simulation time 183937116 ps
CPU time 8.7 seconds
Started Mar 24 01:55:15 PM PDT 24
Finished Mar 24 01:55:24 PM PDT 24
Peak memory 246864 kb
Host smart-7f6a60a6-8284-45da-9134-ad574c6d6a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456841195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2456841195
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3160436264
Short name T1392
Test name
Test status
Simulation time 52578980 ps
CPU time 5.84 seconds
Started Mar 24 02:35:20 PM PDT 24
Finished Mar 24 02:35:26 PM PDT 24
Peak memory 243156 kb
Host smart-eae2b5d1-d719-44b3-86cd-b142b2102d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160436264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3160436264
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.199261853
Short name T1506
Test name
Test status
Simulation time 67991495696 ps
CPU time 137.34 seconds
Started Mar 24 01:55:22 PM PDT 24
Finished Mar 24 01:57:39 PM PDT 24
Peak memory 283216 kb
Host smart-286eddf1-520f-4be3-8000-70e93a54123b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199261853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.199261853
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2482254464
Short name T365
Test name
Test status
Simulation time 25390703 ps
CPU time 1.11 seconds
Started Mar 24 01:55:17 PM PDT 24
Finished Mar 24 01:55:19 PM PDT 24
Peak memory 212116 kb
Host smart-e4962011-41a8-4716-aba3-888aabca13c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482254464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2482254464
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3309702793
Short name T342
Test name
Test status
Simulation time 24476513 ps
CPU time 0.93 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:35:26 PM PDT 24
Peak memory 212072 kb
Host smart-e8ad93f0-4594-4736-868a-001c1d654a71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309702793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3309702793
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2763300641
Short name T454
Test name
Test status
Simulation time 108954261 ps
CPU time 0.85 seconds
Started Mar 24 02:35:30 PM PDT 24
Finished Mar 24 02:35:32 PM PDT 24
Peak memory 209972 kb
Host smart-d79a66f4-adf1-4baa-981e-905853950df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763300641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2763300641
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3114299515
Short name T1167
Test name
Test status
Simulation time 20653768 ps
CPU time 0.9 seconds
Started Mar 24 01:55:29 PM PDT 24
Finished Mar 24 01:55:30 PM PDT 24
Peak memory 209924 kb
Host smart-d672b395-68e9-4811-9056-a97cd8d5434e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114299515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3114299515
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2045478916
Short name T316
Test name
Test status
Simulation time 4281757739 ps
CPU time 15.46 seconds
Started Mar 24 01:55:26 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 218768 kb
Host smart-f0d5ed9d-085e-4e5f-8bad-619bb30af225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045478916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2045478916
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.261396840
Short name T1386
Test name
Test status
Simulation time 578004948 ps
CPU time 15.96 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:47 PM PDT 24
Peak memory 226168 kb
Host smart-eca52bb6-e5d4-43d7-bc26-694e0bf4a2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261396840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.261396840
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2072287589
Short name T711
Test name
Test status
Simulation time 1008404776 ps
CPU time 3.74 seconds
Started Mar 24 01:55:26 PM PDT 24
Finished Mar 24 01:55:30 PM PDT 24
Peak memory 209988 kb
Host smart-0908999a-f898-4030-adbc-f32b4f68ec0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072287589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2072287589
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2703943975
Short name T591
Test name
Test status
Simulation time 1707266459 ps
CPU time 5.67 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 210048 kb
Host smart-2e6e30e4-922a-4d1e-9e68-902a8246387c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703943975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2703943975
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1011647996
Short name T221
Test name
Test status
Simulation time 15324657727 ps
CPU time 72.4 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:56:41 PM PDT 24
Peak memory 219432 kb
Host smart-69c25786-a1e5-4a7a-856d-0b254cfd842b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011647996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1011647996
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2522537003
Short name T344
Test name
Test status
Simulation time 3161640103 ps
CPU time 28.68 seconds
Started Mar 24 02:35:30 PM PDT 24
Finished Mar 24 02:36:00 PM PDT 24
Peak memory 219688 kb
Host smart-00749b8e-953b-442f-ab43-e70d8a8c41b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522537003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2522537003
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1289584385
Short name T1534
Test name
Test status
Simulation time 267856151 ps
CPU time 7.94 seconds
Started Mar 24 01:55:35 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 218644 kb
Host smart-b74882bb-e840-4811-971c-0b04a401a5d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289584385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1289584385
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.815812329
Short name T186
Test name
Test status
Simulation time 351191248 ps
CPU time 6.5 seconds
Started Mar 24 02:35:28 PM PDT 24
Finished Mar 24 02:35:35 PM PDT 24
Peak memory 218568 kb
Host smart-804d626e-191a-4bb2-98ae-c517c2fc62c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815812329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.815812329
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1702220261
Short name T1546
Test name
Test status
Simulation time 294092836 ps
CPU time 8.95 seconds
Started Mar 24 02:35:30 PM PDT 24
Finished Mar 24 02:35:40 PM PDT 24
Peak memory 214068 kb
Host smart-b6b67b05-226d-4df0-ab02-45a1d111c755
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702220261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1702220261
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2933552556
Short name T86
Test name
Test status
Simulation time 364514391 ps
CPU time 10.9 seconds
Started Mar 24 01:55:26 PM PDT 24
Finished Mar 24 01:55:37 PM PDT 24
Peak memory 214220 kb
Host smart-70b01f64-ef27-4a4f-b389-2037f9daaa44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933552556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2933552556
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2049128505
Short name T1489
Test name
Test status
Simulation time 23638898562 ps
CPU time 59.4 seconds
Started Mar 24 02:35:30 PM PDT 24
Finished Mar 24 02:36:31 PM PDT 24
Peak memory 284036 kb
Host smart-d67374bc-6b30-460b-86b2-ac612cab210d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049128505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2049128505
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2215765890
Short name T1180
Test name
Test status
Simulation time 1352889543 ps
CPU time 47.17 seconds
Started Mar 24 01:55:26 PM PDT 24
Finished Mar 24 01:56:13 PM PDT 24
Peak memory 284184 kb
Host smart-4bd4003c-1aff-4bab-90d3-7892a339458c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215765890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2215765890
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.777936966
Short name T1151
Test name
Test status
Simulation time 1067332610 ps
CPU time 8.66 seconds
Started Mar 24 01:55:29 PM PDT 24
Finished Mar 24 01:55:38 PM PDT 24
Peak memory 226868 kb
Host smart-920ac482-1734-475a-9b2a-8900e57d0ef0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777936966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.777936966
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.8646972
Short name T1445
Test name
Test status
Simulation time 581043795 ps
CPU time 21.92 seconds
Started Mar 24 02:35:39 PM PDT 24
Finished Mar 24 02:36:01 PM PDT 24
Peak memory 251356 kb
Host smart-63ed9e00-8e42-4a31-8cf0-4d4a1648c3d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8646972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_post_trans.8646972
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2136420164
Short name T533
Test name
Test status
Simulation time 64382123 ps
CPU time 1.52 seconds
Started Mar 24 02:35:34 PM PDT 24
Finished Mar 24 02:35:36 PM PDT 24
Peak memory 221788 kb
Host smart-6c4d1fe8-d40d-4ec7-bb24-6b7105964f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136420164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2136420164
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2534713880
Short name T714
Test name
Test status
Simulation time 72886831 ps
CPU time 3.16 seconds
Started Mar 24 01:55:26 PM PDT 24
Finished Mar 24 01:55:30 PM PDT 24
Peak memory 222484 kb
Host smart-7798d890-96f1-4b52-b124-e134494f44a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534713880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2534713880
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2129067783
Short name T879
Test name
Test status
Simulation time 828693846 ps
CPU time 13.68 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:35:45 PM PDT 24
Peak memory 219564 kb
Host smart-525a8416-28ee-4e70-8bfe-be14c58af222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129067783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2129067783
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2302476535
Short name T1638
Test name
Test status
Simulation time 224556828 ps
CPU time 11.5 seconds
Started Mar 24 01:55:29 PM PDT 24
Finished Mar 24 01:55:40 PM PDT 24
Peak memory 219528 kb
Host smart-cefcb023-a37d-408b-982d-f53b97cfb368
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302476535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2302476535
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1209965546
Short name T359
Test name
Test status
Simulation time 400036362 ps
CPU time 10.74 seconds
Started Mar 24 02:35:33 PM PDT 24
Finished Mar 24 02:35:44 PM PDT 24
Peak memory 218480 kb
Host smart-dd3d3a5c-0be4-46a9-a8a8-fc07e5750880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209965546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1209965546
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3049358437
Short name T289
Test name
Test status
Simulation time 1079412803 ps
CPU time 7.54 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:36 PM PDT 24
Peak memory 218572 kb
Host smart-dc344c7c-f3ed-4086-bc3c-11b980c83968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049358437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3049358437
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3481842876
Short name T1350
Test name
Test status
Simulation time 426643191 ps
CPU time 14.56 seconds
Started Mar 24 02:35:39 PM PDT 24
Finished Mar 24 02:35:54 PM PDT 24
Peak memory 218368 kb
Host smart-6f3e61b5-98bf-4a76-90d8-d967885fa6bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481842876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3481842876
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.986622188
Short name T694
Test name
Test status
Simulation time 531514904 ps
CPU time 8 seconds
Started Mar 24 01:55:27 PM PDT 24
Finished Mar 24 01:55:35 PM PDT 24
Peak memory 218480 kb
Host smart-ba7bc878-a0c0-4c20-b51d-85ec72f9d0f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986622188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.986622188
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.847135217
Short name T896
Test name
Test status
Simulation time 439848192 ps
CPU time 15.66 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:47 PM PDT 24
Peak memory 225636 kb
Host smart-28e3e8fd-2c24-4c3a-9996-490fe00aa332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847135217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.847135217
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1266293260
Short name T392
Test name
Test status
Simulation time 20231151 ps
CPU time 1.48 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:35:26 PM PDT 24
Peak memory 218232 kb
Host smart-2bf9d137-7e98-41ac-83e3-1ea553b5e575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266293260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1266293260
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.143043371
Short name T1426
Test name
Test status
Simulation time 73433955 ps
CPU time 1.24 seconds
Started Mar 24 01:55:25 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 213752 kb
Host smart-a7c60121-9eb4-4b21-a490-1d6ae72b481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143043371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.143043371
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1149692351
Short name T1149
Test name
Test status
Simulation time 557918205 ps
CPU time 27.91 seconds
Started Mar 24 01:55:23 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 251484 kb
Host smart-fc93309b-890a-4108-a17a-3bfdc1e80f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149692351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1149692351
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3268648895
Short name T955
Test name
Test status
Simulation time 2124830003 ps
CPU time 28.02 seconds
Started Mar 24 02:35:26 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 251468 kb
Host smart-5437d5c5-c12c-4b90-83e6-886ed753c7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268648895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3268648895
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2316916176
Short name T993
Test name
Test status
Simulation time 80551595 ps
CPU time 8.01 seconds
Started Mar 24 02:35:23 PM PDT 24
Finished Mar 24 02:35:31 PM PDT 24
Peak memory 251452 kb
Host smart-8835804a-f90f-4c99-8997-5cf6dfd09c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316916176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2316916176
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2552808926
Short name T1035
Test name
Test status
Simulation time 127899153 ps
CPU time 9.64 seconds
Started Mar 24 01:55:29 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 251500 kb
Host smart-4bcf8141-f730-4680-8a85-0e8dba177c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552808926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2552808926
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.604480180
Short name T820
Test name
Test status
Simulation time 6783999235 ps
CPU time 229.33 seconds
Started Mar 24 01:55:26 PM PDT 24
Finished Mar 24 01:59:16 PM PDT 24
Peak memory 284328 kb
Host smart-29e0cbb0-7f82-4454-9f6c-8d84c50bfcc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604480180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.604480180
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.93767655
Short name T1189
Test name
Test status
Simulation time 6681232186 ps
CPU time 78.73 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:36:50 PM PDT 24
Peak memory 251592 kb
Host smart-ab701a34-0f5d-43b2-8eb6-9887270a716a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93767655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.lc_ctrl_stress_all.93767655
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3326174126
Short name T950
Test name
Test status
Simulation time 12306961 ps
CPU time 0.77 seconds
Started Mar 24 02:35:21 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 208920 kb
Host smart-f6f8bbb2-31ff-40dd-a3d9-06445455cfbb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326174126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3326174126
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.963629140
Short name T1488
Test name
Test status
Simulation time 13782543 ps
CPU time 0.95 seconds
Started Mar 24 01:55:24 PM PDT 24
Finished Mar 24 01:55:25 PM PDT 24
Peak memory 212020 kb
Host smart-89700311-d4b4-4ebe-8c21-f54af3dc6bfe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963629140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.963629140
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.204340630
Short name T1123
Test name
Test status
Simulation time 22864180 ps
CPU time 0.92 seconds
Started Mar 24 02:35:43 PM PDT 24
Finished Mar 24 02:35:44 PM PDT 24
Peak memory 209960 kb
Host smart-ee62420e-6144-49c3-9750-7021d2db286a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204340630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.204340630
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.2546783978
Short name T943
Test name
Test status
Simulation time 21764553 ps
CPU time 0.86 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 210048 kb
Host smart-0f3fcd93-1edd-4587-8006-51dd64f470ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546783978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2546783978
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1780607080
Short name T544
Test name
Test status
Simulation time 235964987 ps
CPU time 10.4 seconds
Started Mar 24 01:55:27 PM PDT 24
Finished Mar 24 01:55:37 PM PDT 24
Peak memory 218548 kb
Host smart-907969f4-6555-4a80-807c-504a8d326738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780607080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1780607080
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4245179013
Short name T416
Test name
Test status
Simulation time 1802639793 ps
CPU time 16.92 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:49 PM PDT 24
Peak memory 218508 kb
Host smart-d78301e1-c5eb-4b35-8497-61043aa360d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245179013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4245179013
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1964212254
Short name T27
Test name
Test status
Simulation time 252314077 ps
CPU time 7.05 seconds
Started Mar 24 01:55:31 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 217556 kb
Host smart-12b183f0-4251-41a1-a007-724639364f67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964212254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1964212254
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2257931050
Short name T5
Test name
Test status
Simulation time 1082334062 ps
CPU time 6.01 seconds
Started Mar 24 02:35:32 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 210004 kb
Host smart-064da719-3a3e-4cec-a86d-e6fe1ba5cf63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257931050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2257931050
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1424321042
Short name T1532
Test name
Test status
Simulation time 9346411976 ps
CPU time 53.5 seconds
Started Mar 24 01:55:27 PM PDT 24
Finished Mar 24 01:56:21 PM PDT 24
Peak memory 219520 kb
Host smart-72e04954-7d55-42b8-99ef-a7c198d114c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424321042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1424321042
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.606195631
Short name T538
Test name
Test status
Simulation time 5793654016 ps
CPU time 43.32 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:36:15 PM PDT 24
Peak memory 219148 kb
Host smart-22aa56f8-cd16-4c3d-8ad7-f6d30c8b6f3e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606195631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.606195631
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1163035707
Short name T361
Test name
Test status
Simulation time 3669960409 ps
CPU time 10.19 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 218684 kb
Host smart-9146320e-4f8a-476b-810a-fb6051a46c39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163035707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1163035707
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2463440674
Short name T1286
Test name
Test status
Simulation time 1490217113 ps
CPU time 12.41 seconds
Started Mar 24 01:55:29 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 218560 kb
Host smart-189b0898-3abb-4657-9247-b7dd09427a70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463440674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2463440674
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1584327942
Short name T421
Test name
Test status
Simulation time 639294320 ps
CPU time 3.64 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:35:35 PM PDT 24
Peak memory 213868 kb
Host smart-4ceeadf2-ed13-41d7-9874-6b5773763f76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584327942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1584327942
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.349704137
Short name T68
Test name
Test status
Simulation time 480822025 ps
CPU time 2.24 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:31 PM PDT 24
Peak memory 213360 kb
Host smart-b2374129-da8f-4b80-9473-ba0b5ec73643
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349704137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
349704137
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1536440635
Short name T618
Test name
Test status
Simulation time 12465189417 ps
CPU time 94.26 seconds
Started Mar 24 01:55:30 PM PDT 24
Finished Mar 24 01:57:04 PM PDT 24
Peak memory 281204 kb
Host smart-02262ca3-6951-4c6d-9c54-403b8f59ab18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536440635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1536440635
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.3564599547
Short name T1032
Test name
Test status
Simulation time 1898510714 ps
CPU time 45.59 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:36:17 PM PDT 24
Peak memory 275304 kb
Host smart-d91fbaef-541e-4148-b870-9766a08ea6dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564599547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.3564599547
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.180823103
Short name T978
Test name
Test status
Simulation time 1526868555 ps
CPU time 11.38 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 249868 kb
Host smart-8e4a6731-aa1c-4a73-8071-5a7c0df263b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180823103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.180823103
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2368142122
Short name T821
Test name
Test status
Simulation time 3147036144 ps
CPU time 22.05 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 226940 kb
Host smart-fc634f04-e647-44af-b5dc-79e6d0f51e83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368142122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2368142122
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.141918390
Short name T457
Test name
Test status
Simulation time 53703168 ps
CPU time 2.64 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:31 PM PDT 24
Peak memory 222304 kb
Host smart-3708167e-9fb3-4951-8ee7-6bbd205e9016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141918390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.141918390
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3128603659
Short name T1471
Test name
Test status
Simulation time 25324059 ps
CPU time 2.09 seconds
Started Mar 24 02:35:28 PM PDT 24
Finished Mar 24 02:35:31 PM PDT 24
Peak memory 222316 kb
Host smart-5f91e7da-1d55-4f4a-90e2-043044cb7c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128603659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3128603659
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2377205132
Short name T876
Test name
Test status
Simulation time 567198426 ps
CPU time 15.56 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:48 PM PDT 24
Peak memory 226684 kb
Host smart-a9c74486-7aaa-4382-bfeb-bc57b37d64b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377205132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2377205132
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.499014428
Short name T1008
Test name
Test status
Simulation time 221385752 ps
CPU time 11.51 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:44 PM PDT 24
Peak memory 219516 kb
Host smart-2b4ad52d-0f22-4694-8f69-301d2c04230d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499014428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.499014428
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.193311173
Short name T945
Test name
Test status
Simulation time 528484154 ps
CPU time 11.65 seconds
Started Mar 24 02:35:37 PM PDT 24
Finished Mar 24 02:35:49 PM PDT 24
Peak memory 218624 kb
Host smart-92ae23e6-6586-4ab1-ae76-d3556e001c14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193311173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.193311173
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.3398356608
Short name T400
Test name
Test status
Simulation time 277604020 ps
CPU time 12.42 seconds
Started Mar 24 01:55:31 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 218536 kb
Host smart-d3f1f4d1-552e-4d6d-a44d-d0a0aa80d32d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398356608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.3398356608
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3494204301
Short name T1048
Test name
Test status
Simulation time 739815859 ps
CPU time 10.08 seconds
Started Mar 24 02:35:34 PM PDT 24
Finished Mar 24 02:35:45 PM PDT 24
Peak memory 218648 kb
Host smart-3f336822-ec6a-489c-bc62-cae9ab52f284
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494204301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3494204301
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.598158261
Short name T502
Test name
Test status
Simulation time 1307518174 ps
CPU time 11.82 seconds
Started Mar 24 01:55:31 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 218648 kb
Host smart-3a0effad-55ef-4221-b266-9c6ba888c79c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598158261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.598158261
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1076707746
Short name T437
Test name
Test status
Simulation time 170245884 ps
CPU time 7.35 seconds
Started Mar 24 01:55:27 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 225036 kb
Host smart-6ace82de-6571-46e4-8b56-e2674d9135ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076707746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1076707746
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3150137132
Short name T1259
Test name
Test status
Simulation time 930056823 ps
CPU time 11.4 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:43 PM PDT 24
Peak memory 226640 kb
Host smart-15ce5464-c95c-4337-95a1-b836e61291bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150137132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3150137132
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1179191574
Short name T922
Test name
Test status
Simulation time 938015105 ps
CPU time 4.57 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:33 PM PDT 24
Peak memory 218320 kb
Host smart-3d2e444a-1539-4051-9291-2a1980c75a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179191574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1179191574
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3380084566
Short name T1692
Test name
Test status
Simulation time 96904934 ps
CPU time 1.92 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:35:31 PM PDT 24
Peak memory 214380 kb
Host smart-e19b2547-32bd-4b8e-a0fc-e9748d1812e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380084566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3380084566
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.322713583
Short name T726
Test name
Test status
Simulation time 554995787 ps
CPU time 24.7 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:53 PM PDT 24
Peak memory 247056 kb
Host smart-f428cb07-78dd-44bd-9809-e968652ee070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322713583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.322713583
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.747759247
Short name T422
Test name
Test status
Simulation time 329318476 ps
CPU time 34.94 seconds
Started Mar 24 02:35:30 PM PDT 24
Finished Mar 24 02:36:06 PM PDT 24
Peak memory 251496 kb
Host smart-604dadd1-c414-4193-9dc7-234a75a6a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747759247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.747759247
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1272000407
Short name T822
Test name
Test status
Simulation time 271830925 ps
CPU time 6.3 seconds
Started Mar 24 02:35:29 PM PDT 24
Finished Mar 24 02:35:38 PM PDT 24
Peak memory 250736 kb
Host smart-be03c252-c9b0-4f27-8f2b-5a6f1c6ff17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272000407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1272000407
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.4130439860
Short name T1643
Test name
Test status
Simulation time 411516296 ps
CPU time 5.62 seconds
Started Mar 24 01:55:28 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 222964 kb
Host smart-3f5bf98a-8cc5-4c9c-b9ed-0c6fe952e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130439860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.4130439860
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3234173209
Short name T1258
Test name
Test status
Simulation time 3328996323 ps
CPU time 70.9 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:56:44 PM PDT 24
Peak memory 221824 kb
Host smart-59768131-5b9c-4bef-aa98-f23c64ffecb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234173209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3234173209
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3987166662
Short name T127
Test name
Test status
Simulation time 5624053976 ps
CPU time 212.05 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:39:08 PM PDT 24
Peak memory 278224 kb
Host smart-63123a23-a448-46e3-8905-99e64f8c2ed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987166662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3987166662
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2621443839
Short name T53
Test name
Test status
Simulation time 185479560288 ps
CPU time 764.38 seconds
Started Mar 24 02:35:35 PM PDT 24
Finished Mar 24 02:48:19 PM PDT 24
Peak memory 513860 kb
Host smart-9864d8fe-8964-452f-b3b2-2f909d065de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2621443839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2621443839
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1359051562
Short name T1541
Test name
Test status
Simulation time 60330077 ps
CPU time 1 seconds
Started Mar 24 02:35:31 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 212060 kb
Host smart-641894b9-af2e-4ac8-8fcf-b4dfac805f85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359051562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1359051562
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3842507728
Short name T720
Test name
Test status
Simulation time 68684929 ps
CPU time 0.88 seconds
Started Mar 24 01:55:29 PM PDT 24
Finished Mar 24 01:55:30 PM PDT 24
Peak memory 209284 kb
Host smart-65200173-57a9-4b5d-87bf-944d5161ccec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842507728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3842507728
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1372219556
Short name T1011
Test name
Test status
Simulation time 139163598 ps
CPU time 1.23 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 209996 kb
Host smart-cac3a780-1301-4717-bdab-225dca06b418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372219556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1372219556
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2466672735
Short name T1215
Test name
Test status
Simulation time 14742563 ps
CPU time 1.06 seconds
Started Mar 24 01:55:37 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 209900 kb
Host smart-7651744e-a4c7-4e89-8b62-5e2776ea0fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466672735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2466672735
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.156811783
Short name T1290
Test name
Test status
Simulation time 343220598 ps
CPU time 14.06 seconds
Started Mar 24 02:35:35 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 218584 kb
Host smart-b1ec3ebf-f0ee-421a-a8e1-9e03c38afccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156811783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.156811783
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2874784354
Short name T352
Test name
Test status
Simulation time 334406963 ps
CPU time 11.9 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:44 PM PDT 24
Peak memory 218588 kb
Host smart-69f33309-f262-4d94-8862-9361bf3b63cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874784354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2874784354
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3030094780
Short name T229
Test name
Test status
Simulation time 1653432373 ps
CPU time 5.41 seconds
Started Mar 24 02:35:37 PM PDT 24
Finished Mar 24 02:35:43 PM PDT 24
Peak memory 210016 kb
Host smart-17d26e91-f04f-4f42-a23c-3bbf9b5acb88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030094780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3030094780
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3162879339
Short name T1021
Test name
Test status
Simulation time 2729981490 ps
CPU time 7.93 seconds
Started Mar 24 01:55:33 PM PDT 24
Finished Mar 24 01:55:41 PM PDT 24
Peak memory 217972 kb
Host smart-a847068c-c8e2-4f1f-9b08-28503ecd3d5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162879339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3162879339
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1765935317
Short name T46
Test name
Test status
Simulation time 1981058417 ps
CPU time 58.69 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:56:36 PM PDT 24
Peak memory 218836 kb
Host smart-31b4c0dc-3d5f-4af9-bb73-b8c1899bfaad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765935317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1765935317
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1807043502
Short name T1349
Test name
Test status
Simulation time 5529525867 ps
CPU time 30.9 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:36:07 PM PDT 24
Peak memory 218580 kb
Host smart-81684e9d-791f-45a0-b3e2-0d377a94fbca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807043502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1807043502
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1397141585
Short name T1623
Test name
Test status
Simulation time 1246074383 ps
CPU time 9.49 seconds
Started Mar 24 01:55:33 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 218500 kb
Host smart-5668e894-5eed-444b-902b-f9373cf7f706
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397141585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1397141585
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3055085712
Short name T312
Test name
Test status
Simulation time 3793290879 ps
CPU time 13.47 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 218652 kb
Host smart-a34001ec-b5c1-41ff-b1ed-531094064518
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055085712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3055085712
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1974454497
Short name T81
Test name
Test status
Simulation time 299035377 ps
CPU time 7.66 seconds
Started Mar 24 02:35:37 PM PDT 24
Finished Mar 24 02:35:45 PM PDT 24
Peak memory 213824 kb
Host smart-3dc12fa8-0a82-43dc-8cd4-07546907561e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974454497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1974454497
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.445984831
Short name T4
Test name
Test status
Simulation time 246012335 ps
CPU time 4.05 seconds
Started Mar 24 01:55:33 PM PDT 24
Finished Mar 24 01:55:37 PM PDT 24
Peak memory 213808 kb
Host smart-7b5648cd-58b1-4cda-82f9-f56ffa9d6064
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445984831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
445984831
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2841772138
Short name T783
Test name
Test status
Simulation time 4439041227 ps
CPU time 36.47 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:56:09 PM PDT 24
Peak memory 253604 kb
Host smart-cd281b1b-ea54-45f9-8111-132ea552ad02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841772138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2841772138
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2844774421
Short name T280
Test name
Test status
Simulation time 3035703247 ps
CPU time 57.4 seconds
Started Mar 24 02:35:38 PM PDT 24
Finished Mar 24 02:36:35 PM PDT 24
Peak memory 251504 kb
Host smart-e892faac-84c1-4606-8654-7fbc446d8241
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844774421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2844774421
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2943947476
Short name T98
Test name
Test status
Simulation time 3004748930 ps
CPU time 19.77 seconds
Started Mar 24 02:35:35 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 251268 kb
Host smart-827bc46a-a079-4423-b84a-8f38fa5b79ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943947476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2943947476
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3515939991
Short name T742
Test name
Test status
Simulation time 793994746 ps
CPU time 11.81 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:45 PM PDT 24
Peak memory 250624 kb
Host smart-1c115e26-e465-4693-8eff-95ad32af1ad5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515939991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3515939991
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3190321976
Short name T1268
Test name
Test status
Simulation time 149449692 ps
CPU time 2.18 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 222416 kb
Host smart-c0eb16c9-cd06-4793-b4e4-34450487ecb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190321976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3190321976
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3373444127
Short name T690
Test name
Test status
Simulation time 131966339 ps
CPU time 1.81 seconds
Started Mar 24 02:35:34 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 222040 kb
Host smart-35e41bb9-7b18-41b8-aa56-57e939711214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373444127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3373444127
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1277649965
Short name T447
Test name
Test status
Simulation time 551533609 ps
CPU time 16.69 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:49 PM PDT 24
Peak memory 226664 kb
Host smart-89f0c678-ac63-47b4-aa77-dd6922cae3ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277649965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1277649965
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2709559205
Short name T1270
Test name
Test status
Simulation time 813888762 ps
CPU time 31.41 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:36:07 PM PDT 24
Peak memory 219548 kb
Host smart-3ef465fb-dec8-405f-8f3b-3aabab27fdb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709559205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2709559205
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2915875023
Short name T507
Test name
Test status
Simulation time 205611304 ps
CPU time 7.47 seconds
Started Mar 24 01:55:35 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 218552 kb
Host smart-66728df7-f64c-499f-abdd-fc6d338bc831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915875023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2915875023
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.84285900
Short name T300
Test name
Test status
Simulation time 416142044 ps
CPU time 8.57 seconds
Started Mar 24 02:35:39 PM PDT 24
Finished Mar 24 02:35:48 PM PDT 24
Peak memory 218408 kb
Host smart-5178c491-cf89-4b30-879a-56403f2b2cae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84285900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_dig
est.84285900
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2846844701
Short name T1520
Test name
Test status
Simulation time 371464058 ps
CPU time 10.58 seconds
Started Mar 24 02:35:35 PM PDT 24
Finished Mar 24 02:35:46 PM PDT 24
Peak memory 218588 kb
Host smart-3e9d9268-226d-45ce-9879-c8a6bb53ed02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846844701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2846844701
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3511474244
Short name T913
Test name
Test status
Simulation time 721358759 ps
CPU time 13.56 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 218924 kb
Host smart-3298c700-a663-4c8a-931f-49ce0e2d1f45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511474244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3511474244
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2691831959
Short name T362
Test name
Test status
Simulation time 329780293 ps
CPU time 13.12 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:49 PM PDT 24
Peak memory 225816 kb
Host smart-5bbc37e6-c490-45dc-a8be-0d8c63d8836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691831959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2691831959
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3160158849
Short name T942
Test name
Test status
Simulation time 497326973 ps
CPU time 9.16 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 225372 kb
Host smart-57bcfa3a-5279-45aa-95ee-804683433378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160158849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3160158849
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.4009806516
Short name T409
Test name
Test status
Simulation time 154564916 ps
CPU time 4.34 seconds
Started Mar 24 01:55:31 PM PDT 24
Finished Mar 24 01:55:36 PM PDT 24
Peak memory 214964 kb
Host smart-55c3680c-a7fc-4c1f-b0ec-6789a58f88dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009806516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4009806516
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2333745658
Short name T197
Test name
Test status
Simulation time 243647453 ps
CPU time 30.14 seconds
Started Mar 24 01:55:34 PM PDT 24
Finished Mar 24 01:56:04 PM PDT 24
Peak memory 251476 kb
Host smart-75461f60-8180-4242-9474-f376f3da77f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333745658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2333745658
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2490654630
Short name T1407
Test name
Test status
Simulation time 798850234 ps
CPU time 27.92 seconds
Started Mar 24 02:35:34 PM PDT 24
Finished Mar 24 02:36:02 PM PDT 24
Peak memory 251492 kb
Host smart-c4e334a4-e9be-49e9-b9ba-bca64a4948e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490654630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2490654630
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2224935163
Short name T358
Test name
Test status
Simulation time 273271955 ps
CPU time 7.88 seconds
Started Mar 24 01:55:37 PM PDT 24
Finished Mar 24 01:55:45 PM PDT 24
Peak memory 251732 kb
Host smart-3018c441-521d-47da-abc8-38759d918e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224935163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2224935163
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2610942027
Short name T1408
Test name
Test status
Simulation time 115257996 ps
CPU time 7.38 seconds
Started Mar 24 02:35:45 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 251368 kb
Host smart-50df375c-0d5b-4a5e-ba7d-9fb1d17ea500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610942027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2610942027
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1881710617
Short name T661
Test name
Test status
Simulation time 48131244558 ps
CPU time 474.54 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 02:03:31 PM PDT 24
Peak memory 284328 kb
Host smart-16e80b7c-90e9-4efc-9df4-d80437b20610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881710617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1881710617
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.777891578
Short name T792
Test name
Test status
Simulation time 24616228073 ps
CPU time 290.05 seconds
Started Mar 24 02:35:45 PM PDT 24
Finished Mar 24 02:40:36 PM PDT 24
Peak memory 284232 kb
Host smart-8d7cff61-5e98-4b35-a138-fdaaf16f1135
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777891578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.777891578
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2704385301
Short name T209
Test name
Test status
Simulation time 54680197184 ps
CPU time 1149.92 seconds
Started Mar 24 02:35:39 PM PDT 24
Finished Mar 24 02:54:49 PM PDT 24
Peak memory 333604 kb
Host smart-2b3bbaa0-2160-494c-99c8-b6e5d08a8ff3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2704385301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2704385301
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1335318135
Short name T841
Test name
Test status
Simulation time 62905222 ps
CPU time 0.95 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:00 PM PDT 24
Peak memory 212084 kb
Host smart-086c899e-df1a-48e7-825c-5465fa3200da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335318135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.1335318135
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3045617040
Short name T496
Test name
Test status
Simulation time 58880422 ps
CPU time 0.96 seconds
Started Mar 24 01:55:30 PM PDT 24
Finished Mar 24 01:55:32 PM PDT 24
Peak memory 212128 kb
Host smart-6a77d2ca-cdb6-43cd-a09f-4b795fb6b7d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045617040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3045617040
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.4234446499
Short name T1486
Test name
Test status
Simulation time 22681081 ps
CPU time 1.01 seconds
Started Mar 24 01:55:41 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 209956 kb
Host smart-7e72f165-6d5f-46c5-aa59-bde2cdc37240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234446499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4234446499
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.647327943
Short name T1165
Test name
Test status
Simulation time 18442781 ps
CPU time 1.18 seconds
Started Mar 24 02:35:38 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 209856 kb
Host smart-f8b4f1e2-bc6f-4b81-87ae-fccd2d9c78ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647327943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.647327943
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3177342847
Short name T1620
Test name
Test status
Simulation time 659566853 ps
CPU time 12.14 seconds
Started Mar 24 02:36:00 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 218508 kb
Host smart-c0108f72-4e2d-49e7-964f-4f5d9662de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177342847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3177342847
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.704942693
Short name T1013
Test name
Test status
Simulation time 7216930370 ps
CPU time 17.26 seconds
Started Mar 24 01:55:38 PM PDT 24
Finished Mar 24 01:55:55 PM PDT 24
Peak memory 226732 kb
Host smart-d7b74dad-3c70-483c-b5e9-23a68010f4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704942693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.704942693
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2292039428
Short name T1239
Test name
Test status
Simulation time 669926382 ps
CPU time 14.11 seconds
Started Mar 24 02:35:35 PM PDT 24
Finished Mar 24 02:35:49 PM PDT 24
Peak memory 210040 kb
Host smart-fab4e37d-1d99-4d60-8746-b3dac31c6635
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292039428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2292039428
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3913603502
Short name T1226
Test name
Test status
Simulation time 220367101 ps
CPU time 4.83 seconds
Started Mar 24 01:55:37 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 209936 kb
Host smart-640d0519-4fe9-4e84-bac9-402e02e71642
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913603502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3913603502
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1717513202
Short name T1605
Test name
Test status
Simulation time 11712267647 ps
CPU time 52.38 seconds
Started Mar 24 01:55:38 PM PDT 24
Finished Mar 24 01:56:31 PM PDT 24
Peak memory 219524 kb
Host smart-fd27f1be-d94b-4437-b0f0-35daa3194937
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717513202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1717513202
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3744627363
Short name T594
Test name
Test status
Simulation time 23773506755 ps
CPU time 44.38 seconds
Started Mar 24 02:35:37 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 218588 kb
Host smart-bac52ec7-4a01-4477-8757-f5eb536257f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744627363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3744627363
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3877918404
Short name T406
Test name
Test status
Simulation time 191822777 ps
CPU time 3.61 seconds
Started Mar 24 01:55:38 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 218532 kb
Host smart-49498aa0-d16d-4b70-af82-d94974a1a685
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877918404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3877918404
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.42248442
Short name T764
Test name
Test status
Simulation time 1025905430 ps
CPU time 24.78 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:24 PM PDT 24
Peak memory 218520 kb
Host smart-0c5d0a7e-4799-4b53-9cd5-bb26bb0cb604
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42248442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_
prog_failure.42248442
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3995472718
Short name T997
Test name
Test status
Simulation time 819315034 ps
CPU time 3.02 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:02 PM PDT 24
Peak memory 213084 kb
Host smart-68baa928-6907-4617-8421-a454e5db2d40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995472718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3995472718
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.4135717766
Short name T347
Test name
Test status
Simulation time 335134090 ps
CPU time 2 seconds
Started Mar 24 01:55:37 PM PDT 24
Finished Mar 24 01:55:40 PM PDT 24
Peak memory 213036 kb
Host smart-da7cc17c-eb3d-42ab-9431-cc6e6d9ca7f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135717766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.4135717766
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.574179675
Short name T1106
Test name
Test status
Simulation time 8200275235 ps
CPU time 73.02 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 278344 kb
Host smart-d73c6870-e9fc-415e-965a-2c8da6e0f020
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574179675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.574179675
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.720615710
Short name T840
Test name
Test status
Simulation time 4925173523 ps
CPU time 53.53 seconds
Started Mar 24 02:35:38 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 255592 kb
Host smart-e88784b0-bb44-41eb-8a60-46b10e305a74
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720615710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.720615710
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.4248374599
Short name T1243
Test name
Test status
Simulation time 1133571685 ps
CPU time 11.58 seconds
Started Mar 24 01:55:39 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 251732 kb
Host smart-72f5e42e-4a73-4141-bfc2-5558a28d9c64
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248374599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.4248374599
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.675653099
Short name T894
Test name
Test status
Simulation time 974970131 ps
CPU time 15.74 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:51 PM PDT 24
Peak memory 246864 kb
Host smart-5fddaa49-06d5-461f-9c31-3b6ef04cf92c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675653099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.675653099
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3334144086
Short name T1625
Test name
Test status
Simulation time 95304682 ps
CPU time 3.47 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:55:41 PM PDT 24
Peak memory 218844 kb
Host smart-a91779c4-7b31-4681-89c1-3b8bc46155b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334144086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3334144086
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.559080698
Short name T1683
Test name
Test status
Simulation time 45302494 ps
CPU time 2.21 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:38 PM PDT 24
Peak memory 222212 kb
Host smart-6f1267e0-a275-43b7-98bc-42aca40cd434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559080698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.559080698
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2718868513
Short name T475
Test name
Test status
Simulation time 385924760 ps
CPU time 8.55 seconds
Started Mar 24 02:35:37 PM PDT 24
Finished Mar 24 02:35:46 PM PDT 24
Peak memory 219524 kb
Host smart-5779a2d0-3607-4d3a-bb81-e83615530618
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718868513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2718868513
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3367584309
Short name T1555
Test name
Test status
Simulation time 355901642 ps
CPU time 12.28 seconds
Started Mar 24 01:55:38 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 219500 kb
Host smart-dab16df5-889f-4ea3-847a-7b005a46ce99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367584309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3367584309
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1236190627
Short name T1586
Test name
Test status
Simulation time 771608708 ps
CPU time 13.09 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 218504 kb
Host smart-ce200f5f-45fd-4031-8d3b-a0062d30922f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236190627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1236190627
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.454371046
Short name T748
Test name
Test status
Simulation time 402329733 ps
CPU time 12.8 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:55:49 PM PDT 24
Peak memory 218572 kb
Host smart-1f531be9-afc1-47bc-a9d5-ce082ae24565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454371046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.454371046
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.2079233118
Short name T305
Test name
Test status
Simulation time 751836689 ps
CPU time 7.89 seconds
Started Mar 24 02:35:37 PM PDT 24
Finished Mar 24 02:35:45 PM PDT 24
Peak memory 218568 kb
Host smart-d5bf02a7-a53d-49eb-aa13-56be8a498c0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079233118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
2079233118
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.9881790
Short name T1393
Test name
Test status
Simulation time 1544080199 ps
CPU time 9.44 seconds
Started Mar 24 01:55:39 PM PDT 24
Finished Mar 24 01:55:49 PM PDT 24
Peak memory 218624 kb
Host smart-5c878419-c399-4b13-98f6-dfe682134448
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9881790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.9881790
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1474690834
Short name T707
Test name
Test status
Simulation time 369217909 ps
CPU time 13.06 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:49 PM PDT 24
Peak memory 226660 kb
Host smart-d4b1f2a8-17b2-487c-b34a-b47fe02c9a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474690834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1474690834
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2742708336
Short name T493
Test name
Test status
Simulation time 534402052 ps
CPU time 10.83 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 226656 kb
Host smart-7481b757-8429-473a-9c30-7e4f4059e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742708336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2742708336
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2044637030
Short name T284
Test name
Test status
Simulation time 19956838 ps
CPU time 1.29 seconds
Started Mar 24 01:55:38 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 213624 kb
Host smart-ff496524-5d25-435e-8be1-f6f26e423fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044637030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2044637030
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3312922288
Short name T304
Test name
Test status
Simulation time 253722978 ps
CPU time 3.12 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 218396 kb
Host smart-6078a5d3-d019-460b-93f4-656ee74bc5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312922288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3312922288
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2299373890
Short name T226
Test name
Test status
Simulation time 3334552313 ps
CPU time 33.48 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:56:11 PM PDT 24
Peak memory 248004 kb
Host smart-4d92ad96-13f1-4323-8e59-c888765c85ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299373890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2299373890
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2730746494
Short name T728
Test name
Test status
Simulation time 819316017 ps
CPU time 25.91 seconds
Started Mar 24 02:35:45 PM PDT 24
Finished Mar 24 02:36:11 PM PDT 24
Peak memory 251384 kb
Host smart-c073b337-e2cd-4c3e-adae-2aea11a5e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730746494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2730746494
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1937351316
Short name T1428
Test name
Test status
Simulation time 78819068 ps
CPU time 4.1 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:02 PM PDT 24
Peak memory 222884 kb
Host smart-9c45242a-665f-4db5-abe7-7f79c0a484be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937351316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1937351316
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4069565668
Short name T579
Test name
Test status
Simulation time 112027830 ps
CPU time 5.32 seconds
Started Mar 24 01:55:44 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 226900 kb
Host smart-a95cffd0-ba5b-4b5c-b8be-84b41b8c0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069565668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4069565668
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1697419412
Short name T1603
Test name
Test status
Simulation time 63665358183 ps
CPU time 319.42 seconds
Started Mar 24 02:35:44 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 267940 kb
Host smart-f212a71f-76e8-4ef2-9fe3-a67d5eb3c465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697419412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1697419412
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4131900363
Short name T1656
Test name
Test status
Simulation time 14881487324 ps
CPU time 142.05 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:57:58 PM PDT 24
Peak memory 276640 kb
Host smart-839be808-db51-472e-aeca-964d5fdc69c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131900363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4131900363
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2418949674
Short name T1398
Test name
Test status
Simulation time 13478946 ps
CPU time 0.99 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:55:37 PM PDT 24
Peak memory 211916 kb
Host smart-4619acff-1a91-407d-9d11-6c6b4931394a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418949674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2418949674
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3080451739
Short name T854
Test name
Test status
Simulation time 50011829 ps
CPU time 1.2 seconds
Started Mar 24 02:35:36 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 212040 kb
Host smart-c7948622-163f-44b5-9cce-daec1e4f9065
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080451739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3080451739
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2118122472
Short name T874
Test name
Test status
Simulation time 62863071 ps
CPU time 1.05 seconds
Started Mar 24 01:55:44 PM PDT 24
Finished Mar 24 01:55:45 PM PDT 24
Peak memory 209964 kb
Host smart-42492a98-a708-4eaa-9f7f-c72d0f09001e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118122472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2118122472
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2632796621
Short name T755
Test name
Test status
Simulation time 18930874 ps
CPU time 1.18 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 209968 kb
Host smart-d93e32f4-adee-43dc-9bed-fb7c9cec53a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632796621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2632796621
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3242710189
Short name T889
Test name
Test status
Simulation time 855891543 ps
CPU time 12.01 seconds
Started Mar 24 01:55:44 PM PDT 24
Finished Mar 24 01:55:56 PM PDT 24
Peak memory 218536 kb
Host smart-b2faf949-45f9-4fd1-85ac-98d0a111e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242710189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3242710189
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3752124056
Short name T1432
Test name
Test status
Simulation time 256735722 ps
CPU time 9.46 seconds
Started Mar 24 02:35:41 PM PDT 24
Finished Mar 24 02:35:51 PM PDT 24
Peak memory 218544 kb
Host smart-d3c60cdd-f938-4aa9-963c-2e8242a6a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752124056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3752124056
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1524008467
Short name T1621
Test name
Test status
Simulation time 6985282858 ps
CPU time 13.16 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:55:56 PM PDT 24
Peak memory 217948 kb
Host smart-061b310f-089b-4145-b9c1-e05f7414c1ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524008467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1524008467
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1894641784
Short name T7
Test name
Test status
Simulation time 8178503290 ps
CPU time 7.29 seconds
Started Mar 24 02:35:45 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 210076 kb
Host smart-4bd79ddb-105b-4911-9621-c8791fc171b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894641784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1894641784
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2851537288
Short name T1598
Test name
Test status
Simulation time 15186001024 ps
CPU time 34.85 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:56:18 PM PDT 24
Peak memory 219112 kb
Host smart-55522ee6-a997-46d7-bc3c-3e19ef17d7f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851537288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2851537288
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.399247121
Short name T338
Test name
Test status
Simulation time 1484927216 ps
CPU time 30.72 seconds
Started Mar 24 02:35:41 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 218484 kb
Host smart-3573f99f-7dd0-49bd-895c-315f9a63b838
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399247121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.399247121
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1349027563
Short name T224
Test name
Test status
Simulation time 2295970467 ps
CPU time 16.14 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 218688 kb
Host smart-f2f60a5a-01f0-4d3d-9922-c9ac6e7b6f28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349027563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1349027563
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2875455793
Short name T333
Test name
Test status
Simulation time 776902434 ps
CPU time 11.62 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:36:04 PM PDT 24
Peak memory 218564 kb
Host smart-1b71c24d-2bf4-4986-83d6-060cfc9380fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875455793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2875455793
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1908747303
Short name T429
Test name
Test status
Simulation time 578349682 ps
CPU time 13.81 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 214304 kb
Host smart-31bef710-4e0f-4ec1-b18d-8efc1e3ba8bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908747303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1908747303
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4223221315
Short name T1433
Test name
Test status
Simulation time 615535561 ps
CPU time 4.86 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:35:58 PM PDT 24
Peak memory 213948 kb
Host smart-6979dbb8-55aa-404f-809f-66be0663cb33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223221315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4223221315
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3331058023
Short name T961
Test name
Test status
Simulation time 5622124408 ps
CPU time 61.09 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 254008 kb
Host smart-d8e144c1-278f-4595-9cc9-0fcce2baf1ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331058023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3331058023
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3653374209
Short name T1313
Test name
Test status
Simulation time 1246332494 ps
CPU time 53.3 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:56:37 PM PDT 24
Peak memory 267820 kb
Host smart-9c7c84fd-39fa-4df4-84b6-a959f8bedfe0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653374209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3653374209
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3431758270
Short name T747
Test name
Test status
Simulation time 461977157 ps
CPU time 15.95 seconds
Started Mar 24 02:35:41 PM PDT 24
Finished Mar 24 02:35:57 PM PDT 24
Peak memory 223456 kb
Host smart-8ee19f6d-bc9a-4bb1-8aca-c3acf8dfcfe1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431758270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3431758270
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.729491032
Short name T1075
Test name
Test status
Simulation time 356903678 ps
CPU time 17.38 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:56:08 PM PDT 24
Peak memory 251448 kb
Host smart-5080d256-fc50-4517-a86b-6bf0296116ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729491032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.729491032
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1120121053
Short name T1496
Test name
Test status
Simulation time 581969777 ps
CPU time 3.58 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 222792 kb
Host smart-af3dc878-91a1-4204-a0df-363d261230c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120121053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1120121053
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1966395219
Short name T1420
Test name
Test status
Simulation time 159204413 ps
CPU time 1.99 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 222288 kb
Host smart-2698dcd0-43c9-4fa7-b90a-5639df0ca951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966395219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1966395219
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3175275328
Short name T1260
Test name
Test status
Simulation time 2022432817 ps
CPU time 15.77 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:11 PM PDT 24
Peak memory 219520 kb
Host smart-22fc8015-cd2e-43e2-80da-1c87c5bad294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175275328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3175275328
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3313294221
Short name T1647
Test name
Test status
Simulation time 1577143107 ps
CPU time 18.55 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:56:02 PM PDT 24
Peak memory 219188 kb
Host smart-f9e2bb6c-dc40-4cb5-a1d7-222a930c4800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313294221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3313294221
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1968754890
Short name T1588
Test name
Test status
Simulation time 863494687 ps
CPU time 9.57 seconds
Started Mar 24 01:55:41 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 218596 kb
Host smart-5fb938a0-2f42-4a28-b13a-7bf13a217b05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968754890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1968754890
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.383300521
Short name T1448
Test name
Test status
Simulation time 747316888 ps
CPU time 9.1 seconds
Started Mar 24 02:35:42 PM PDT 24
Finished Mar 24 02:35:52 PM PDT 24
Peak memory 218588 kb
Host smart-658bb3cb-ff84-4bb6-a674-9d5218ee4fa9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383300521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.383300521
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1270490507
Short name T230
Test name
Test status
Simulation time 365871985 ps
CPU time 13.21 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 218648 kb
Host smart-2e2bdfc3-9f1c-4828-8962-6a892c99bbf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270490507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1270490507
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2748401926
Short name T1438
Test name
Test status
Simulation time 347828023 ps
CPU time 9.62 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 218556 kb
Host smart-d11bb24f-44c4-44e2-bc01-91146ea6b295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748401926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2748401926
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.147268206
Short name T397
Test name
Test status
Simulation time 1365661600 ps
CPU time 13.15 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:55:59 PM PDT 24
Peak memory 225928 kb
Host smart-6f8ca2d6-fe44-4091-9a92-17d65775c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147268206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.147268206
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4201568714
Short name T848
Test name
Test status
Simulation time 1724828486 ps
CPU time 15.41 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 225692 kb
Host smart-e6ee5cf6-e011-491c-b5aa-bbe5011645a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201568714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4201568714
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3006573450
Short name T1325
Test name
Test status
Simulation time 69461595 ps
CPU time 1.25 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 213792 kb
Host smart-9515afad-4c91-4c71-b50c-a255780dd95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006573450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3006573450
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.588860542
Short name T569
Test name
Test status
Simulation time 27871935 ps
CPU time 2.16 seconds
Started Mar 24 01:55:36 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 214676 kb
Host smart-86abbfe3-104a-43dc-afb7-99cdb857f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588860542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.588860542
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2139666730
Short name T1404
Test name
Test status
Simulation time 1317505737 ps
CPU time 21.34 seconds
Started Mar 24 01:55:39 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 251496 kb
Host smart-5494a614-39f8-4fb7-becf-b3146bc6c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139666730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2139666730
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3421139112
Short name T934
Test name
Test status
Simulation time 609355139 ps
CPU time 18.31 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:59 PM PDT 24
Peak memory 251528 kb
Host smart-033dadad-62c5-4db7-9976-48e89c235eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421139112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3421139112
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.312580897
Short name T994
Test name
Test status
Simulation time 219241315 ps
CPU time 6.73 seconds
Started Mar 24 02:35:41 PM PDT 24
Finished Mar 24 02:35:48 PM PDT 24
Peak memory 250936 kb
Host smart-c1cffdfe-c612-4791-94c0-c8731928b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312580897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.312580897
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3929612417
Short name T1061
Test name
Test status
Simulation time 116581057 ps
CPU time 2.98 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:55:46 PM PDT 24
Peak memory 222812 kb
Host smart-89dc6656-e70f-440c-88ed-f781c98e1db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929612417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3929612417
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1494883866
Short name T1182
Test name
Test status
Simulation time 1261546923 ps
CPU time 41.57 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 251188 kb
Host smart-02b594f6-6bdf-4e82-a12c-5239c73632c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494883866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1494883866
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.2992436996
Short name T1261
Test name
Test status
Simulation time 11404051534 ps
CPU time 124.7 seconds
Started Mar 24 01:55:42 PM PDT 24
Finished Mar 24 01:57:47 PM PDT 24
Peak memory 284228 kb
Host smart-c62a744f-df89-4e32-b954-5bbda23581ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992436996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.2992436996
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1347148475
Short name T1401
Test name
Test status
Simulation time 26857788099 ps
CPU time 350.54 seconds
Started Mar 24 01:55:45 PM PDT 24
Finished Mar 24 02:01:36 PM PDT 24
Peak memory 319652 kb
Host smart-7296d118-a20c-4b15-85a0-447ba9aef04f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1347148475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1347148475
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2168623566
Short name T23
Test name
Test status
Simulation time 30619007 ps
CPU time 0.96 seconds
Started Mar 24 01:55:38 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 212100 kb
Host smart-63c15a1e-d45e-4a6c-9289-c4956c41d1d0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168623566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2168623566
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.76662763
Short name T1549
Test name
Test status
Simulation time 14085198 ps
CPU time 0.98 seconds
Started Mar 24 02:35:41 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 209148 kb
Host smart-78e1a701-f728-4894-8e00-eabf7e4aee07
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76662763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_volatile_unlock_smoke.76662763
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3901993636
Short name T298
Test name
Test status
Simulation time 12835108 ps
CPU time 0.83 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:55:53 PM PDT 24
Peak memory 209460 kb
Host smart-65e1cb5e-9a2a-4e0c-a2ac-bca686403362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901993636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3901993636
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.659288991
Short name T33
Test name
Test status
Simulation time 63504871 ps
CPU time 0.93 seconds
Started Mar 24 02:35:44 PM PDT 24
Finished Mar 24 02:35:46 PM PDT 24
Peak memory 209972 kb
Host smart-71b18d47-ca22-4aaa-9d02-77f90238eef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659288991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.659288991
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1691384918
Short name T963
Test name
Test status
Simulation time 822752055 ps
CPU time 11.33 seconds
Started Mar 24 02:35:43 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 218716 kb
Host smart-b47d17ec-4705-4867-86a8-8ba920743e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691384918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1691384918
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3440013135
Short name T3
Test name
Test status
Simulation time 362218379 ps
CPU time 9.96 seconds
Started Mar 24 01:55:41 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 218520 kb
Host smart-27982682-4559-41b6-8908-dc27eb7d95fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440013135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3440013135
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2269331389
Short name T1233
Test name
Test status
Simulation time 337888533 ps
CPU time 9.62 seconds
Started Mar 24 02:35:43 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 210104 kb
Host smart-0cd44df4-c408-4ffe-afcf-610e0f9479a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269331389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2269331389
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2289323121
Short name T1070
Test name
Test status
Simulation time 1346530567 ps
CPU time 9.49 seconds
Started Mar 24 01:55:44 PM PDT 24
Finished Mar 24 01:55:53 PM PDT 24
Peak memory 210100 kb
Host smart-4e4d516b-8a26-4399-9628-4a716fddcf84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289323121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2289323121
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2061067740
Short name T911
Test name
Test status
Simulation time 7679762399 ps
CPU time 41.65 seconds
Started Mar 24 02:35:45 PM PDT 24
Finished Mar 24 02:36:27 PM PDT 24
Peak memory 218656 kb
Host smart-fac1c1ff-5431-44ae-beb9-ac4a818b3a8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061067740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2061067740
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.428561481
Short name T411
Test name
Test status
Simulation time 6843809149 ps
CPU time 49.23 seconds
Started Mar 24 01:55:47 PM PDT 24
Finished Mar 24 01:56:36 PM PDT 24
Peak memory 218516 kb
Host smart-e319fd9f-0ced-4d24-a8d3-dbb00b1ce3e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428561481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.428561481
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1571959079
Short name T1127
Test name
Test status
Simulation time 66203359 ps
CPU time 2.63 seconds
Started Mar 24 02:35:42 PM PDT 24
Finished Mar 24 02:35:46 PM PDT 24
Peak memory 218472 kb
Host smart-825c5d70-971f-458c-bc1f-6ffac2db2a3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571959079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1571959079
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3381861925
Short name T1504
Test name
Test status
Simulation time 163471093 ps
CPU time 4.88 seconds
Started Mar 24 01:55:42 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 218516 kb
Host smart-bdf08ccd-6d11-4fda-aa38-d0ddaa031076
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381861925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3381861925
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.15151795
Short name T423
Test name
Test status
Simulation time 2612685467 ps
CPU time 7.88 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 214560 kb
Host smart-0e67d63f-ce0c-4dfa-9c51-707c85adf6e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.15151795
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3126707884
Short name T983
Test name
Test status
Simulation time 356785222 ps
CPU time 1.69 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 213112 kb
Host smart-eaa98c33-b052-46f8-b2e1-47747c6b8643
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126707884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3126707884
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2494250005
Short name T1543
Test name
Test status
Simulation time 1522165116 ps
CPU time 46.65 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 269312 kb
Host smart-916424f9-f912-400d-a381-1752e246a16f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494250005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2494250005
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.4259461164
Short name T531
Test name
Test status
Simulation time 12980958050 ps
CPU time 93.43 seconds
Started Mar 24 01:55:41 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 267912 kb
Host smart-c0d0951e-f4e5-4201-bf2c-bd6fbb898ab9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259461164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.4259461164
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2157095364
Short name T1581
Test name
Test status
Simulation time 1363903951 ps
CPU time 15.67 seconds
Started Mar 24 02:35:43 PM PDT 24
Finished Mar 24 02:35:59 PM PDT 24
Peak memory 251384 kb
Host smart-4405f0b0-14f5-404b-921c-79b219a77cf1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157095364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2157095364
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.7737511
Short name T856
Test name
Test status
Simulation time 1249250797 ps
CPU time 10.68 seconds
Started Mar 24 01:55:45 PM PDT 24
Finished Mar 24 01:55:55 PM PDT 24
Peak memory 243252 kb
Host smart-6ac611c9-ff49-495c-9129-1c4a1b2b2d36
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7737511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_post_trans.7737511
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2350349398
Short name T377
Test name
Test status
Simulation time 137378981 ps
CPU time 1.48 seconds
Started Mar 24 01:55:44 PM PDT 24
Finished Mar 24 01:55:46 PM PDT 24
Peak memory 221752 kb
Host smart-0eef6ccd-7f88-482b-aca1-aa75fe248a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350349398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2350349398
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3955607016
Short name T628
Test name
Test status
Simulation time 50300054 ps
CPU time 2.27 seconds
Started Mar 24 02:35:39 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 218724 kb
Host smart-b80bcc04-494d-49e4-9c7e-ea4e32fb2de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955607016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3955607016
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2916598362
Short name T1376
Test name
Test status
Simulation time 918886318 ps
CPU time 10.38 seconds
Started Mar 24 01:55:42 PM PDT 24
Finished Mar 24 01:55:53 PM PDT 24
Peak memory 218652 kb
Host smart-9a5bacbf-14ed-454a-9617-76883bda2add
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916598362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2916598362
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3644116897
Short name T1245
Test name
Test status
Simulation time 1812691090 ps
CPU time 11.73 seconds
Started Mar 24 02:35:43 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 218500 kb
Host smart-5519d205-9aef-4055-a2fa-0947d4f84806
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644116897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3644116897
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2069818458
Short name T314
Test name
Test status
Simulation time 1646704022 ps
CPU time 11.74 seconds
Started Mar 24 01:55:45 PM PDT 24
Finished Mar 24 01:55:57 PM PDT 24
Peak memory 218604 kb
Host smart-23918aab-4102-4315-b7ff-d47881f25c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069818458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2069818458
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.90997706
Short name T438
Test name
Test status
Simulation time 242676740 ps
CPU time 8.24 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 218348 kb
Host smart-6eb213de-bac4-4249-9e42-c934742965a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90997706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_dig
est.90997706
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3408446206
Short name T1332
Test name
Test status
Simulation time 529936742 ps
CPU time 12.94 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:55:59 PM PDT 24
Peak memory 218532 kb
Host smart-68d115fd-c31e-4fcf-ae6e-9596f9b135aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408446206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3408446206
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4253973885
Short name T190
Test name
Test status
Simulation time 412979564 ps
CPU time 9.04 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 218600 kb
Host smart-0fd705f1-0fd0-45b1-9f55-e66558359747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253973885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4253973885
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.270253548
Short name T408
Test name
Test status
Simulation time 369870801 ps
CPU time 13.43 seconds
Started Mar 24 02:35:42 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 226140 kb
Host smart-78d18b66-4119-4376-b5de-57644e47255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270253548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.270253548
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3139311115
Short name T588
Test name
Test status
Simulation time 523732726 ps
CPU time 12.03 seconds
Started Mar 24 01:55:44 PM PDT 24
Finished Mar 24 01:55:56 PM PDT 24
Peak memory 226676 kb
Host smart-df6b99de-7f7e-4aa1-9de5-fab4683322a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139311115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3139311115
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.2526858392
Short name T1231
Test name
Test status
Simulation time 52148275 ps
CPU time 3.1 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:43 PM PDT 24
Peak memory 214580 kb
Host smart-8329be46-1362-4651-af9b-72652d513f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526858392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2526858392
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.4188975265
Short name T103
Test name
Test status
Simulation time 67031067 ps
CPU time 1.39 seconds
Started Mar 24 01:55:43 PM PDT 24
Finished Mar 24 01:55:44 PM PDT 24
Peak memory 218408 kb
Host smart-53083b12-41c1-4479-969e-180ba912e287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188975265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.4188975265
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.3498918559
Short name T1528
Test name
Test status
Simulation time 583578437 ps
CPU time 22.25 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:36:15 PM PDT 24
Peak memory 251516 kb
Host smart-02998a84-a85c-4c37-9694-8183f3f2d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498918559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3498918559
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.4133816740
Short name T698
Test name
Test status
Simulation time 253146695 ps
CPU time 26.02 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 246084 kb
Host smart-235b61f1-afa3-49cc-bb0a-95711668383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133816740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.4133816740
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2751279798
Short name T988
Test name
Test status
Simulation time 55854614 ps
CPU time 6.21 seconds
Started Mar 24 01:55:45 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 247544 kb
Host smart-6f1edc49-aa5b-4cf6-b59c-76fdd996afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751279798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2751279798
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3372050084
Short name T1300
Test name
Test status
Simulation time 254399245 ps
CPU time 7.17 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:47 PM PDT 24
Peak memory 250936 kb
Host smart-7b95b303-2075-496c-8fab-ce39baaa21fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372050084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3372050084
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1675689719
Short name T332
Test name
Test status
Simulation time 4524609556 ps
CPU time 113.78 seconds
Started Mar 24 01:55:47 PM PDT 24
Finished Mar 24 01:57:41 PM PDT 24
Peak memory 269248 kb
Host smart-b341d736-b42b-44d8-9788-2889b7e0b07a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675689719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1675689719
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1695763201
Short name T295
Test name
Test status
Simulation time 29897568057 ps
CPU time 96.34 seconds
Started Mar 24 02:35:44 PM PDT 24
Finished Mar 24 02:37:21 PM PDT 24
Peak memory 267992 kb
Host smart-9d9ca2f5-baa9-419c-ae4d-80d112b06766
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695763201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1695763201
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1111577366
Short name T524
Test name
Test status
Simulation time 97840607054 ps
CPU time 468.83 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:43:36 PM PDT 24
Peak memory 293020 kb
Host smart-909e8d21-d9a9-4928-8376-ad5d11ed9d39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1111577366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1111577366
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.116271237
Short name T1652
Test name
Test status
Simulation time 60836669 ps
CPU time 0.95 seconds
Started Mar 24 02:35:40 PM PDT 24
Finished Mar 24 02:35:41 PM PDT 24
Peak memory 213012 kb
Host smart-0e8b1552-597e-416a-945f-14f6635072e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116271237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.116271237
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3855795462
Short name T22
Test name
Test status
Simulation time 10974428 ps
CPU time 0.89 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 208464 kb
Host smart-45fd6121-7b39-4d09-a59d-16c777343774
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855795462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3855795462
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4202796940
Short name T71
Test name
Test status
Simulation time 72545279 ps
CPU time 1.21 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:35:48 PM PDT 24
Peak memory 210016 kb
Host smart-85e2892d-1f0f-4095-82ab-993bbe35b345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202796940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4202796940
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.523625574
Short name T1249
Test name
Test status
Simulation time 28103143 ps
CPU time 1.37 seconds
Started Mar 24 01:55:48 PM PDT 24
Finished Mar 24 01:55:51 PM PDT 24
Peak memory 210044 kb
Host smart-8253c57c-84c3-43b7-92b0-eba1bfe0b0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523625574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.523625574
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3023609280
Short name T969
Test name
Test status
Simulation time 224644478 ps
CPU time 8.43 seconds
Started Mar 24 01:55:47 PM PDT 24
Finished Mar 24 01:55:55 PM PDT 24
Peak memory 226664 kb
Host smart-23884eed-5fa5-4bb0-a85f-cc4be5977b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023609280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3023609280
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3398261906
Short name T1704
Test name
Test status
Simulation time 283279525 ps
CPU time 12.95 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:36:01 PM PDT 24
Peak memory 218464 kb
Host smart-360d0feb-4d7c-41a6-92bf-802beee8a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398261906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3398261906
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3301755922
Short name T857
Test name
Test status
Simulation time 637826569 ps
CPU time 15.13 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:56:05 PM PDT 24
Peak memory 210036 kb
Host smart-5f2fd982-dcb7-48a9-8bb5-ff5c4b5e171e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301755922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3301755922
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3322768956
Short name T1688
Test name
Test status
Simulation time 262157894 ps
CPU time 7.79 seconds
Started Mar 24 02:35:50 PM PDT 24
Finished Mar 24 02:35:58 PM PDT 24
Peak memory 210024 kb
Host smart-14706cc7-0fe2-4a42-80dd-0bf7aa7b90ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322768956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3322768956
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3142668642
Short name T1654
Test name
Test status
Simulation time 3380486273 ps
CPU time 50.44 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:36:39 PM PDT 24
Peak memory 219752 kb
Host smart-a1569e98-9806-4316-a1bb-ee8b79809cb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142668642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3142668642
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3510316358
Short name T811
Test name
Test status
Simulation time 2708656378 ps
CPU time 74.07 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:57:01 PM PDT 24
Peak memory 220564 kb
Host smart-e6c89358-dcf7-4e3a-aa47-f8fef0f4f8bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510316358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3510316358
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2206499357
Short name T459
Test name
Test status
Simulation time 2320147086 ps
CPU time 6.83 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 218540 kb
Host smart-f8efb219-3b65-4327-95c6-e3c9032e2f69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206499357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2206499357
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3922732726
Short name T1568
Test name
Test status
Simulation time 14968867691 ps
CPU time 19.95 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 218556 kb
Host smart-bc85c903-bc7d-4a8c-ae2a-215784dc643b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922732726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3922732726
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.141038230
Short name T837
Test name
Test status
Simulation time 1853949272 ps
CPU time 5.86 seconds
Started Mar 24 02:35:49 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 213836 kb
Host smart-a52cf402-7fe1-4acf-86f2-eb71c77ef204
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141038230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
141038230
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1483994115
Short name T1467
Test name
Test status
Simulation time 1091464496 ps
CPU time 8.39 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 214200 kb
Host smart-6d368f51-c5d3-4bd2-b72a-5d5fa17528f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483994115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1483994115
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1997202414
Short name T952
Test name
Test status
Simulation time 985275151 ps
CPU time 50.59 seconds
Started Mar 24 01:55:47 PM PDT 24
Finished Mar 24 01:56:38 PM PDT 24
Peak memory 251996 kb
Host smart-0f50c0d1-5dc9-41ef-9a66-3922ddd37e8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997202414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1997202414
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2528583649
Short name T534
Test name
Test status
Simulation time 5946575263 ps
CPU time 97.55 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 281964 kb
Host smart-5bb59fb6-1381-44c2-b178-c09b36825716
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528583649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2528583649
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1234157556
Short name T466
Test name
Test status
Simulation time 800328586 ps
CPU time 8.73 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:35:57 PM PDT 24
Peak memory 223544 kb
Host smart-3218a954-3888-4cde-9baf-e17bdee8c056
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234157556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1234157556
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.526574678
Short name T1281
Test name
Test status
Simulation time 657132414 ps
CPU time 14.67 seconds
Started Mar 24 01:55:49 PM PDT 24
Finished Mar 24 01:56:04 PM PDT 24
Peak memory 251364 kb
Host smart-5bcb5696-b242-4eaf-8579-8f53783fd55b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526574678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.526574678
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2340108213
Short name T739
Test name
Test status
Simulation time 320170928 ps
CPU time 2.5 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:55:49 PM PDT 24
Peak memory 222380 kb
Host smart-e7aa2aa7-71b6-46b6-9b96-9c8a274916ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340108213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2340108213
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3796189440
Short name T468
Test name
Test status
Simulation time 36510252 ps
CPU time 2.53 seconds
Started Mar 24 02:35:50 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 222600 kb
Host smart-2b091562-4fc0-4413-ad9c-2963446b13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796189440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3796189440
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1830456124
Short name T1639
Test name
Test status
Simulation time 843355980 ps
CPU time 19.01 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:56:09 PM PDT 24
Peak memory 218724 kb
Host smart-4048b9c0-25cb-470e-835c-c2df5b2003de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830456124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1830456124
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3933046165
Short name T1159
Test name
Test status
Simulation time 604476362 ps
CPU time 14.85 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:36:02 PM PDT 24
Peak memory 218576 kb
Host smart-45cc220f-c7fc-42ab-9843-660060b50d9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933046165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3933046165
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2216775662
Short name T865
Test name
Test status
Simulation time 1697529371 ps
CPU time 12.7 seconds
Started Mar 24 02:35:52 PM PDT 24
Finished Mar 24 02:36:05 PM PDT 24
Peak memory 218624 kb
Host smart-e154cb0a-b664-44ce-8447-088fdef0e8ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216775662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2216775662
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.357278906
Short name T844
Test name
Test status
Simulation time 2269077685 ps
CPU time 13.79 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 218648 kb
Host smart-4bd91dc6-7828-46a9-bc47-5c61134bf694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357278906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_di
gest.357278906
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2490370136
Short name T1685
Test name
Test status
Simulation time 485666791 ps
CPU time 10.16 seconds
Started Mar 24 01:55:48 PM PDT 24
Finished Mar 24 01:55:58 PM PDT 24
Peak memory 218632 kb
Host smart-5ce874d4-e806-4629-8f19-f9cb089701d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490370136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2490370136
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.27309898
Short name T1234
Test name
Test status
Simulation time 1227129397 ps
CPU time 10.27 seconds
Started Mar 24 02:35:49 PM PDT 24
Finished Mar 24 02:36:00 PM PDT 24
Peak memory 218656 kb
Host smart-e27915bb-308b-4faa-a37a-e840c2e9e08f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.27309898
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1059745696
Short name T1156
Test name
Test status
Simulation time 472772518 ps
CPU time 10.85 seconds
Started Mar 24 02:35:49 PM PDT 24
Finished Mar 24 02:35:59 PM PDT 24
Peak memory 226676 kb
Host smart-02337871-a4b7-4aab-a30c-88172d937bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059745696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1059745696
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2064252503
Short name T1153
Test name
Test status
Simulation time 58814297 ps
CPU time 1.12 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 213676 kb
Host smart-571db711-0727-45ef-aef1-46045bb7ac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064252503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2064252503
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4178266117
Short name T1425
Test name
Test status
Simulation time 200620806 ps
CPU time 2.28 seconds
Started Mar 24 02:35:42 PM PDT 24
Finished Mar 24 02:35:44 PM PDT 24
Peak memory 214612 kb
Host smart-ff73ca4f-e209-4a07-860d-b93cdf4e51e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178266117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4178266117
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1442146977
Short name T1490
Test name
Test status
Simulation time 1458066569 ps
CPU time 25.21 seconds
Started Mar 24 01:55:51 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 251376 kb
Host smart-74440ac0-edae-4a7a-8b72-f31f35a75c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442146977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1442146977
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.810155263
Short name T786
Test name
Test status
Simulation time 1140236560 ps
CPU time 22.6 seconds
Started Mar 24 02:35:44 PM PDT 24
Finished Mar 24 02:36:08 PM PDT 24
Peak memory 251536 kb
Host smart-632f969d-af51-4885-899d-8a7417e2a08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810155263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.810155263
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2280842595
Short name T90
Test name
Test status
Simulation time 85726012 ps
CPU time 6.77 seconds
Started Mar 24 01:55:48 PM PDT 24
Finished Mar 24 01:55:55 PM PDT 24
Peak memory 243316 kb
Host smart-e1e9eea1-6b40-4dd5-9ddf-c45b0ea13962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280842595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2280842595
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4193820592
Short name T369
Test name
Test status
Simulation time 95037398 ps
CPU time 7.81 seconds
Started Mar 24 02:35:43 PM PDT 24
Finished Mar 24 02:35:51 PM PDT 24
Peak memory 251368 kb
Host smart-e32b949c-518e-47cc-b587-e95d116818b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193820592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4193820592
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2922008881
Short name T850
Test name
Test status
Simulation time 12155972144 ps
CPU time 89.98 seconds
Started Mar 24 01:55:45 PM PDT 24
Finished Mar 24 01:57:16 PM PDT 24
Peak memory 284196 kb
Host smart-f99f4f42-8eb0-401e-9ccd-d7e4b5503975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922008881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2922008881
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.996382559
Short name T740
Test name
Test status
Simulation time 41685146367 ps
CPU time 597.75 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:45:45 PM PDT 24
Peak memory 251348 kb
Host smart-9cbb695f-203d-408a-b63e-f2252a75f6e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996382559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.996382559
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3054184467
Short name T64
Test name
Test status
Simulation time 31978650117 ps
CPU time 496.83 seconds
Started Mar 24 01:55:48 PM PDT 24
Finished Mar 24 02:04:05 PM PDT 24
Peak memory 284540 kb
Host smart-b61c6115-1f2a-4fc7-881d-e8d762370332
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3054184467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3054184467
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1738138797
Short name T712
Test name
Test status
Simulation time 52042502 ps
CPU time 0.84 seconds
Started Mar 24 01:55:48 PM PDT 24
Finished Mar 24 01:55:49 PM PDT 24
Peak memory 209236 kb
Host smart-ad129b9a-be6a-4ef0-b005-8ebcc5e8ec34
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738138797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1738138797
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3834788645
Short name T539
Test name
Test status
Simulation time 12599536 ps
CPU time 0.98 seconds
Started Mar 24 02:35:44 PM PDT 24
Finished Mar 24 02:35:46 PM PDT 24
Peak memory 209108 kb
Host smart-2ccc78b9-608c-4833-842d-a49f89784164
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834788645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3834788645
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1455695413
Short name T469
Test name
Test status
Simulation time 62354960 ps
CPU time 0.95 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 209960 kb
Host smart-96de8d9f-c8d5-4fda-81d1-65f1e05e1a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455695413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1455695413
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2945716822
Short name T627
Test name
Test status
Simulation time 31931252 ps
CPU time 1.12 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:55:53 PM PDT 24
Peak memory 209972 kb
Host smart-91df1912-d8c2-4440-8089-1fba9b75f42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945716822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2945716822
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3187382462
Short name T231
Test name
Test status
Simulation time 834903845 ps
CPU time 15.87 seconds
Started Mar 24 02:35:52 PM PDT 24
Finished Mar 24 02:36:08 PM PDT 24
Peak memory 218560 kb
Host smart-e8923081-b9ab-4866-aaf5-50f7e2a37141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187382462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3187382462
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.404900136
Short name T393
Test name
Test status
Simulation time 826430888 ps
CPU time 16.39 seconds
Started Mar 24 01:55:50 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 218556 kb
Host smart-dec25699-af7d-47cc-9cc7-30d4930a6227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404900136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.404900136
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1988994343
Short name T1323
Test name
Test status
Simulation time 887458792 ps
CPU time 4.94 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:35:58 PM PDT 24
Peak memory 210016 kb
Host smart-50838ebb-8880-4c1b-b4af-95884ea0fdb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988994343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1988994343
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3969544410
Short name T705
Test name
Test status
Simulation time 1266857575 ps
CPU time 2.69 seconds
Started Mar 24 01:55:54 PM PDT 24
Finished Mar 24 01:55:57 PM PDT 24
Peak memory 217352 kb
Host smart-7bcad5b2-9cc4-40f0-9f3d-68238a27db47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969544410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3969544410
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.246251960
Short name T1665
Test name
Test status
Simulation time 17481075630 ps
CPU time 120.01 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:57:52 PM PDT 24
Peak memory 220272 kb
Host smart-9a6581e2-837f-4527-a0ed-85cc106bf53d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246251960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_er
rors.246251960
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3235398018
Short name T972
Test name
Test status
Simulation time 28095950730 ps
CPU time 50.77 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 220036 kb
Host smart-0d2c1ede-d6c4-42bc-8f8c-965dd96a0a8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235398018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3235398018
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3931783947
Short name T1176
Test name
Test status
Simulation time 1128560164 ps
CPU time 9.37 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:36:04 PM PDT 24
Peak memory 218520 kb
Host smart-e5968d69-b024-4272-8b43-54a5791e2ec6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931783947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3931783947
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.920264186
Short name T20
Test name
Test status
Simulation time 1364512605 ps
CPU time 17.99 seconds
Started Mar 24 01:55:53 PM PDT 24
Finished Mar 24 01:56:11 PM PDT 24
Peak memory 218412 kb
Host smart-f248845c-e6b1-4f1e-b539-a7550ad23878
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920264186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag
_prog_failure.920264186
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1502877186
Short name T807
Test name
Test status
Simulation time 2113814200 ps
CPU time 6.86 seconds
Started Mar 24 01:55:51 PM PDT 24
Finished Mar 24 01:55:58 PM PDT 24
Peak memory 214020 kb
Host smart-55be86c3-2d3a-48f8-9cfa-d62849f704fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502877186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1502877186
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2086390488
Short name T76
Test name
Test status
Simulation time 503218311 ps
CPU time 1.96 seconds
Started Mar 24 02:35:47 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 213424 kb
Host smart-6e2638f4-6bf4-4f9c-9d63-a532c0c23a30
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086390488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2086390488
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1588116398
Short name T702
Test name
Test status
Simulation time 10777820003 ps
CPU time 55.12 seconds
Started Mar 24 01:55:56 PM PDT 24
Finished Mar 24 01:56:51 PM PDT 24
Peak memory 267900 kb
Host smart-d8d85864-9820-4216-a485-eb018f440b53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588116398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1588116398
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4275748913
Short name T1235
Test name
Test status
Simulation time 2220863668 ps
CPU time 54.62 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:50 PM PDT 24
Peak memory 267928 kb
Host smart-750ab44b-25a4-4789-b8a8-3aa6cc4478cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275748913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4275748913
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2723973121
Short name T1493
Test name
Test status
Simulation time 674730323 ps
CPU time 10.13 seconds
Started Mar 24 01:55:53 PM PDT 24
Finished Mar 24 01:56:03 PM PDT 24
Peak memory 226880 kb
Host smart-eadca6cf-8f90-4da0-a4c0-baff76ec5489
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723973121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2723973121
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.821638626
Short name T319
Test name
Test status
Simulation time 686764186 ps
CPU time 22.46 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:36:16 PM PDT 24
Peak memory 248972 kb
Host smart-e354f29c-75ac-4452-bdad-44076087e0ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821638626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.821638626
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1602522697
Short name T1423
Test name
Test status
Simulation time 22846830 ps
CPU time 2.04 seconds
Started Mar 24 01:55:47 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 222108 kb
Host smart-ccea12b1-eb69-4c14-a6fd-f2ef94f3a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602522697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1602522697
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1848421757
Short name T860
Test name
Test status
Simulation time 46329566 ps
CPU time 2.4 seconds
Started Mar 24 02:35:51 PM PDT 24
Finished Mar 24 02:35:54 PM PDT 24
Peak memory 218668 kb
Host smart-2088b307-7052-4bcb-ba35-3a2c8df01962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848421757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1848421757
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2590270730
Short name T1569
Test name
Test status
Simulation time 856221759 ps
CPU time 9.08 seconds
Started Mar 24 02:35:53 PM PDT 24
Finished Mar 24 02:36:03 PM PDT 24
Peak memory 218600 kb
Host smart-135573e7-7f73-4ff3-8e88-d23d1eb33fad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590270730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2590270730
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3906721906
Short name T441
Test name
Test status
Simulation time 857930275 ps
CPU time 15.23 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:13 PM PDT 24
Peak memory 218480 kb
Host smart-c0555999-e87a-4096-baf5-6fdd0914dd86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906721906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3906721906
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1794765788
Short name T519
Test name
Test status
Simulation time 2332204513 ps
CPU time 24.02 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:21 PM PDT 24
Peak memory 218628 kb
Host smart-23c9841a-b9b2-4e32-9bcc-d3328342732f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794765788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1794765788
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1935953727
Short name T13
Test name
Test status
Simulation time 193938085 ps
CPU time 9.62 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:04 PM PDT 24
Peak memory 218552 kb
Host smart-4f5a612b-29e4-4488-a753-3ce7e7d5883d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935953727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1935953727
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1154789819
Short name T1687
Test name
Test status
Simulation time 337947450 ps
CPU time 12.04 seconds
Started Mar 24 01:55:54 PM PDT 24
Finished Mar 24 01:56:06 PM PDT 24
Peak memory 218556 kb
Host smart-3142d0f0-cbd8-478a-96a3-bb95fb631926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154789819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1154789819
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3580145711
Short name T1320
Test name
Test status
Simulation time 876423258 ps
CPU time 6.67 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:36:01 PM PDT 24
Peak memory 218620 kb
Host smart-073f4faf-b73f-4557-b717-9bdd2a829e10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580145711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3580145711
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.195069434
Short name T1415
Test name
Test status
Simulation time 333898625 ps
CPU time 9.94 seconds
Started Mar 24 02:35:51 PM PDT 24
Finished Mar 24 02:36:01 PM PDT 24
Peak memory 226684 kb
Host smart-02b88594-f3f8-416b-b965-c2c4acddbfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195069434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.195069434
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3962577438
Short name T1454
Test name
Test status
Simulation time 270195347 ps
CPU time 9.86 seconds
Started Mar 24 01:55:53 PM PDT 24
Finished Mar 24 01:56:03 PM PDT 24
Peak memory 224820 kb
Host smart-58dc7d99-16fe-4916-a331-49aae068733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962577438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3962577438
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2329512266
Short name T1132
Test name
Test status
Simulation time 879578443 ps
CPU time 6.52 seconds
Started Mar 24 01:55:48 PM PDT 24
Finished Mar 24 01:55:54 PM PDT 24
Peak memory 218212 kb
Host smart-d7c062be-c4b1-4e22-8ca3-f049eb15c2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329512266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2329512266
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2338070404
Short name T84
Test name
Test status
Simulation time 42945267 ps
CPU time 1.22 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 213780 kb
Host smart-46a2dcbf-fa8d-4458-b51a-e81a987a8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338070404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2338070404
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1051448477
Short name T36
Test name
Test status
Simulation time 220922190 ps
CPU time 24.75 seconds
Started Mar 24 02:35:49 PM PDT 24
Finished Mar 24 02:36:14 PM PDT 24
Peak memory 251432 kb
Host smart-77d153f0-14e4-493c-945a-e2bca5a542fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051448477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1051448477
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.505631462
Short name T577
Test name
Test status
Simulation time 383392908 ps
CPU time 34.44 seconds
Started Mar 24 01:55:49 PM PDT 24
Finished Mar 24 01:56:24 PM PDT 24
Peak memory 251480 kb
Host smart-c97d0663-7430-4cbe-bdce-bfae510dabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505631462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.505631462
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1589599261
Short name T631
Test name
Test status
Simulation time 293546873 ps
CPU time 9.36 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:56:02 PM PDT 24
Peak memory 251160 kb
Host smart-6a94467a-cfb7-40cc-8f72-3032978790e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589599261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1589599261
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2375255159
Short name T1357
Test name
Test status
Simulation time 387408834 ps
CPU time 7.8 seconds
Started Mar 24 02:35:48 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 251464 kb
Host smart-76e1a73c-5056-4b57-bafb-4bc0f9b76657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375255159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2375255159
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1578154276
Short name T384
Test name
Test status
Simulation time 6887546707 ps
CPU time 28.09 seconds
Started Mar 24 01:55:51 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 227136 kb
Host smart-62a96804-619e-43ee-88b0-2ef53abef91f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578154276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1578154276
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.622893494
Short name T1653
Test name
Test status
Simulation time 10176712998 ps
CPU time 182.21 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:38:58 PM PDT 24
Peak memory 226736 kb
Host smart-b82cc999-dd62-4239-86ae-57a968d18f07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622893494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.622893494
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.2095953739
Short name T1045
Test name
Test status
Simulation time 39498643177 ps
CPU time 377.54 seconds
Started Mar 24 01:55:54 PM PDT 24
Finished Mar 24 02:02:12 PM PDT 24
Peak memory 273780 kb
Host smart-0e824ca8-54d5-4169-9a84-bf0224d58b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2095953739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.2095953739
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.131149873
Short name T374
Test name
Test status
Simulation time 115074649 ps
CPU time 0.74 seconds
Started Mar 24 02:35:52 PM PDT 24
Finished Mar 24 02:35:53 PM PDT 24
Peak memory 209068 kb
Host smart-49198e85-b91f-4e87-909e-90eabe7e0f96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131149873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.131149873
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3732993134
Short name T1682
Test name
Test status
Simulation time 163800345 ps
CPU time 0.95 seconds
Started Mar 24 01:55:46 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 212064 kb
Host smart-b85b19d2-e2c3-43ed-8a05-56cc6959f5c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732993134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3732993134
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.176125334
Short name T1143
Test name
Test status
Simulation time 31784385 ps
CPU time 1.04 seconds
Started Mar 24 02:36:01 PM PDT 24
Finished Mar 24 02:36:02 PM PDT 24
Peak memory 209968 kb
Host smart-0912a3c9-b5c2-4d4a-b260-a96d2e66512f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176125334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.176125334
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.429815422
Short name T662
Test name
Test status
Simulation time 20055320 ps
CPU time 0.93 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:55:58 PM PDT 24
Peak memory 209960 kb
Host smart-32e4fc10-0675-4eb2-938c-2a59a5e6d093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429815422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.429815422
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1815752378
Short name T1019
Test name
Test status
Simulation time 1178633313 ps
CPU time 9.03 seconds
Started Mar 24 01:55:51 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 218528 kb
Host smart-e5e5bc22-7e58-4986-9a47-31c9e97a1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815752378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1815752378
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.822618825
Short name T1430
Test name
Test status
Simulation time 492063202 ps
CPU time 13.1 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:08 PM PDT 24
Peak memory 218560 kb
Host smart-dc598131-c594-4536-b46e-a6f1bf95085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822618825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.822618825
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3363642234
Short name T214
Test name
Test status
Simulation time 948128684 ps
CPU time 3.35 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:02 PM PDT 24
Peak memory 209992 kb
Host smart-035f3a27-aaac-4fbe-a135-614a58ee3fbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363642234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3363642234
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.430838546
Short name T29
Test name
Test status
Simulation time 331539347 ps
CPU time 9.36 seconds
Started Mar 24 01:55:56 PM PDT 24
Finished Mar 24 01:56:05 PM PDT 24
Peak memory 217376 kb
Host smart-490d9eb4-ac2f-49c5-ae97-336ddfa7a9b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430838546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.430838546
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3135775555
Short name T1519
Test name
Test status
Simulation time 4705914373 ps
CPU time 19.81 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:22 PM PDT 24
Peak memory 219536 kb
Host smart-2aa3d331-dee2-4b12-9cd6-1f5d71a5c1b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135775555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3135775555
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3675284780
Short name T1080
Test name
Test status
Simulation time 3508795157 ps
CPU time 48.48 seconds
Started Mar 24 02:36:00 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 219536 kb
Host smart-445cf0db-313c-4034-b7dd-fc3b7294cd9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675284780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3675284780
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1122165551
Short name T1371
Test name
Test status
Simulation time 255440993 ps
CPU time 7.59 seconds
Started Mar 24 01:55:56 PM PDT 24
Finished Mar 24 01:56:04 PM PDT 24
Peak memory 218476 kb
Host smart-4e28e398-51ee-4911-9f8f-5d4a63d5681d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122165551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1122165551
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.423179972
Short name T1150
Test name
Test status
Simulation time 165345153 ps
CPU time 5.63 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:05 PM PDT 24
Peak memory 218544 kb
Host smart-e1c27ff0-e5a4-4177-8ceb-d9c6ad124c2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423179972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.423179972
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1272940816
Short name T862
Test name
Test status
Simulation time 16041824604 ps
CPU time 20.02 seconds
Started Mar 24 01:55:58 PM PDT 24
Finished Mar 24 01:56:18 PM PDT 24
Peak memory 214912 kb
Host smart-46f3f63d-2244-4809-9668-ec2179c93f76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272940816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1272940816
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.440577146
Short name T505
Test name
Test status
Simulation time 824448247 ps
CPU time 3.16 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:35:58 PM PDT 24
Peak memory 213756 kb
Host smart-a164c122-13e5-46b9-b0b1-71f9b7f20d6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440577146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
440577146
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.204166291
Short name T18
Test name
Test status
Simulation time 1770083781 ps
CPU time 75.9 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 268296 kb
Host smart-64d3b436-03b2-4e5a-afbd-83194f990668
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204166291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.204166291
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3437357334
Short name T1060
Test name
Test status
Simulation time 2137990783 ps
CPU time 79.95 seconds
Started Mar 24 01:55:56 PM PDT 24
Finished Mar 24 01:57:17 PM PDT 24
Peak memory 280052 kb
Host smart-431842a5-d920-441d-9778-1d858e35d296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437357334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3437357334
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2227651156
Short name T1479
Test name
Test status
Simulation time 497453648 ps
CPU time 18.28 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 247100 kb
Host smart-6ebdad2c-d181-44bd-94e1-6780d05189b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227651156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2227651156
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.568518843
Short name T721
Test name
Test status
Simulation time 797785202 ps
CPU time 12.27 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:36:07 PM PDT 24
Peak memory 226868 kb
Host smart-4d43a329-bbb1-4bb2-a4d8-b6220b7614cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568518843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.568518843
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2225159002
Short name T827
Test name
Test status
Simulation time 73716134 ps
CPU time 2.04 seconds
Started Mar 24 02:35:56 PM PDT 24
Finished Mar 24 02:35:58 PM PDT 24
Peak memory 218464 kb
Host smart-fe0452ce-ba86-463b-a49d-18fc9c340668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225159002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2225159002
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3642799864
Short name T413
Test name
Test status
Simulation time 366244238 ps
CPU time 3.3 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:55:55 PM PDT 24
Peak memory 222712 kb
Host smart-d3f9d68e-1d56-4691-aa14-cbcb9294fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642799864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3642799864
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1393803135
Short name T388
Test name
Test status
Simulation time 1202731808 ps
CPU time 11.06 seconds
Started Mar 24 01:55:55 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 218588 kb
Host smart-f7e43a11-4378-4d7b-badb-920c4cc6d02c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393803135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1393803135
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3286020470
Short name T1476
Test name
Test status
Simulation time 444039916 ps
CPU time 18.61 seconds
Started Mar 24 02:36:01 PM PDT 24
Finished Mar 24 02:36:20 PM PDT 24
Peak memory 219548 kb
Host smart-2cc3ba06-d71b-4c6e-a9d7-f5524df8a48e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286020470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3286020470
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2282295052
Short name T1572
Test name
Test status
Simulation time 1856846254 ps
CPU time 20.65 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:19 PM PDT 24
Peak memory 218532 kb
Host smart-3e9ef30d-8040-4d11-a028-c0d757f21eff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282295052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2282295052
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.4128325357
Short name T632
Test name
Test status
Simulation time 2023122498 ps
CPU time 11.98 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:09 PM PDT 24
Peak memory 218468 kb
Host smart-0647356c-6f36-4e86-bfc4-2b4b0c389e67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128325357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.4128325357
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2040898258
Short name T570
Test name
Test status
Simulation time 346928148 ps
CPU time 12 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:11 PM PDT 24
Peak memory 218552 kb
Host smart-aebbf5f1-11de-4814-b72e-3535f4a407e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040898258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2040898258
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2434895800
Short name T1257
Test name
Test status
Simulation time 377591453 ps
CPU time 9.5 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:12 PM PDT 24
Peak memory 218560 kb
Host smart-ec676241-68cb-42ca-abc9-3691a910fe75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434895800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2434895800
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1333176237
Short name T695
Test name
Test status
Simulation time 1188667717 ps
CPU time 9.15 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:06 PM PDT 24
Peak memory 225428 kb
Host smart-5792cdfb-19c5-4e2b-9651-dcb81fad9d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333176237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1333176237
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3875162704
Short name T1518
Test name
Test status
Simulation time 3655291435 ps
CPU time 9.48 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:04 PM PDT 24
Peak memory 226036 kb
Host smart-6cf4ffae-84b1-4500-8032-451e42aaebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875162704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3875162704
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1164429366
Short name T1303
Test name
Test status
Simulation time 19212290 ps
CPU time 1.04 seconds
Started Mar 24 02:35:56 PM PDT 24
Finished Mar 24 02:35:57 PM PDT 24
Peak memory 218336 kb
Host smart-aed113ec-a573-42ae-ab1b-1a52d907451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164429366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1164429366
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1645753809
Short name T1175
Test name
Test status
Simulation time 76659009 ps
CPU time 2.63 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:55:54 PM PDT 24
Peak memory 218272 kb
Host smart-7cb688fd-b41c-4b27-8ca3-109fe2deab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645753809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1645753809
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1364380719
Short name T610
Test name
Test status
Simulation time 240895981 ps
CPU time 27.15 seconds
Started Mar 24 02:35:55 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 251436 kb
Host smart-2cd594be-3c19-429e-922c-28094762b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364380719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1364380719
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2623042300
Short name T456
Test name
Test status
Simulation time 401211382 ps
CPU time 22.45 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:56:15 PM PDT 24
Peak memory 251380 kb
Host smart-02761dd7-e6a6-4dd0-8039-8fa86a143178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623042300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2623042300
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2771152929
Short name T1695
Test name
Test status
Simulation time 151782953 ps
CPU time 6.79 seconds
Started Mar 24 01:55:52 PM PDT 24
Finished Mar 24 01:55:59 PM PDT 24
Peak memory 247480 kb
Host smart-9ff280a4-9443-4594-8ccc-b9f4d900ba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771152929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2771152929
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.337336917
Short name T882
Test name
Test status
Simulation time 78804402 ps
CPU time 10.35 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:08 PM PDT 24
Peak memory 251492 kb
Host smart-11a503c6-a72f-43d8-a492-1ff8783466fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337336917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.337336917
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.606543711
Short name T679
Test name
Test status
Simulation time 8085075594 ps
CPU time 68.62 seconds
Started Mar 24 01:55:56 PM PDT 24
Finished Mar 24 01:57:05 PM PDT 24
Peak memory 251552 kb
Host smart-f04d9b3d-5d3f-4116-b9dd-001070261626
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606543711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.606543711
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.618903972
Short name T1457
Test name
Test status
Simulation time 5488731238 ps
CPU time 44.55 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:43 PM PDT 24
Peak memory 251552 kb
Host smart-fef0ab70-4374-4439-bb14-e2f00c02fc3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618903972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.618903972
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.186389975
Short name T1001
Test name
Test status
Simulation time 23531946857 ps
CPU time 362.15 seconds
Started Mar 24 01:55:59 PM PDT 24
Finished Mar 24 02:02:01 PM PDT 24
Peak memory 333612 kb
Host smart-fae316b1-c333-4fcf-b233-40894c48c6ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=186389975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.186389975
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2191018234
Short name T350
Test name
Test status
Simulation time 35977984 ps
CPU time 0.77 seconds
Started Mar 24 02:35:54 PM PDT 24
Finished Mar 24 02:35:55 PM PDT 24
Peak memory 209256 kb
Host smart-5040e4ef-6091-44bc-a0be-07001ac14937
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191018234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2191018234
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3329078522
Short name T69
Test name
Test status
Simulation time 30714487 ps
CPU time 0.92 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:55:59 PM PDT 24
Peak memory 212912 kb
Host smart-9a9f1685-b42b-46a5-a56c-947ed925a9d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329078522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3329078522
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3033577813
Short name T124
Test name
Test status
Simulation time 14625116 ps
CPU time 1.02 seconds
Started Mar 24 02:34:51 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 209984 kb
Host smart-922d1979-befd-4aa1-a097-9998dbd4b6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033577813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3033577813
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.887241956
Short name T470
Test name
Test status
Simulation time 29588662 ps
CPU time 1.06 seconds
Started Mar 24 01:54:49 PM PDT 24
Finished Mar 24 01:54:50 PM PDT 24
Peak memory 209980 kb
Host smart-6e51fa4d-061c-4393-975f-3597efdb5b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887241956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.887241956
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2375759582
Short name T944
Test name
Test status
Simulation time 22470922 ps
CPU time 0.99 seconds
Started Mar 24 01:54:41 PM PDT 24
Finished Mar 24 01:54:42 PM PDT 24
Peak memory 210012 kb
Host smart-b1ca36a4-2f55-4fd0-86f4-c2babf15f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375759582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2375759582
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.635422296
Short name T323
Test name
Test status
Simulation time 12999217 ps
CPU time 0.84 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:53 PM PDT 24
Peak memory 209720 kb
Host smart-a290c89d-b90a-4f59-87ce-03ddf6ecac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635422296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.635422296
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1028537192
Short name T838
Test name
Test status
Simulation time 856590798 ps
CPU time 10.81 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:03 PM PDT 24
Peak memory 218540 kb
Host smart-b049ce2c-9526-4b38-a307-ca9283f47dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028537192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1028537192
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.997191821
Short name T345
Test name
Test status
Simulation time 1805470074 ps
CPU time 15.07 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:55:05 PM PDT 24
Peak memory 226640 kb
Host smart-5326049d-22a6-4c81-ace1-d98e24b677b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997191821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.997191821
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.4023449181
Short name T1115
Test name
Test status
Simulation time 740754488 ps
CPU time 7.13 seconds
Started Mar 24 02:34:51 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 217556 kb
Host smart-40b77970-d620-43a5-bcfa-8395f1f6f19d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023449181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4023449181
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.612811501
Short name T30
Test name
Test status
Simulation time 368320984 ps
CPU time 4.97 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 209996 kb
Host smart-f0126148-4342-429c-9600-f6a5ed63cc1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612811501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.612811501
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1947484327
Short name T91
Test name
Test status
Simulation time 2820512754 ps
CPU time 44.15 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 218504 kb
Host smart-3b4bc0de-f0cf-4754-a8c4-fc712ce3a33e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947484327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1947484327
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.931185999
Short name T395
Test name
Test status
Simulation time 10223197080 ps
CPU time 39.01 seconds
Started Mar 24 01:54:43 PM PDT 24
Finished Mar 24 01:55:23 PM PDT 24
Peak memory 219512 kb
Host smart-36171dd3-e848-4d70-a38e-a348fe116f2a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931185999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.931185999
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1235086992
Short name T1615
Test name
Test status
Simulation time 585846768 ps
CPU time 4.77 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:34:58 PM PDT 24
Peak memory 217580 kb
Host smart-393bfeaf-f9a8-4261-a4ed-f6c3940e5182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235086992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
235086992
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1679119812
Short name T1340
Test name
Test status
Simulation time 1012503218 ps
CPU time 3.53 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:54:47 PM PDT 24
Peak memory 218260 kb
Host smart-bd6129bf-fe50-494d-a858-3a36b196d327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679119812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
679119812
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3081040526
Short name T351
Test name
Test status
Simulation time 413898021 ps
CPU time 7.41 seconds
Started Mar 24 02:34:48 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 218476 kb
Host smart-c19c4b3b-7f85-4c6c-ae4c-914eeb0317c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081040526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3081040526
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3141981822
Short name T962
Test name
Test status
Simulation time 806760880 ps
CPU time 21.96 seconds
Started Mar 24 01:54:49 PM PDT 24
Finished Mar 24 01:55:11 PM PDT 24
Peak memory 218560 kb
Host smart-5a8fa618-60e2-47c1-8510-fe2ec0699710
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141981822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3141981822
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1544120662
Short name T1238
Test name
Test status
Simulation time 10969469881 ps
CPU time 22.13 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:55:10 PM PDT 24
Peak memory 214360 kb
Host smart-ff0fdc54-d669-4b47-8ba1-23b00251c8fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544120662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1544120662
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2906979990
Short name T722
Test name
Test status
Simulation time 8462148716 ps
CPU time 16.48 seconds
Started Mar 24 02:34:48 PM PDT 24
Finished Mar 24 02:35:08 PM PDT 24
Peak memory 214376 kb
Host smart-14961eab-9034-40f8-9880-fa71ba30b801
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906979990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2906979990
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2692588512
Short name T512
Test name
Test status
Simulation time 449501640 ps
CPU time 6.76 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:58 PM PDT 24
Peak memory 214204 kb
Host smart-5ff22734-000d-4278-b99b-61d8b3121ebd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692588512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2692588512
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4051184948
Short name T1267
Test name
Test status
Simulation time 2618592066 ps
CPU time 4.35 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:54:55 PM PDT 24
Peak memory 214352 kb
Host smart-d7c4001e-15f6-4ef8-a9cf-7a2d544879e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051184948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
4051184948
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2158647316
Short name T604
Test name
Test status
Simulation time 5448386857 ps
CPU time 49.87 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:42 PM PDT 24
Peak memory 284248 kb
Host smart-a13a1a89-9f3f-4e55-9692-ea3717f955fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158647316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2158647316
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.241698732
Short name T1025
Test name
Test status
Simulation time 1563586597 ps
CPU time 70.11 seconds
Started Mar 24 01:54:39 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 276372 kb
Host smart-3d7cf148-ff1b-41e5-b3b3-f32b92098a95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241698732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.241698732
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1861170343
Short name T418
Test name
Test status
Simulation time 2416869780 ps
CPU time 14.78 seconds
Started Mar 24 02:34:48 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 251468 kb
Host smart-6470f384-3082-44da-8317-343e2b8aa792
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861170343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1861170343
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2000200610
Short name T872
Test name
Test status
Simulation time 5558313597 ps
CPU time 16.61 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:55:05 PM PDT 24
Peak memory 244308 kb
Host smart-ea81149f-c50b-4dde-add4-5fec0c7e9070
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000200610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2000200610
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1040727839
Short name T843
Test name
Test status
Simulation time 53304922 ps
CPU time 2.05 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 222124 kb
Host smart-4177e137-7e10-446d-bfda-4918c154ef2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040727839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1040727839
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2072717923
Short name T1668
Test name
Test status
Simulation time 139495348 ps
CPU time 3.09 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:54:54 PM PDT 24
Peak memory 218600 kb
Host smart-33ad1b6e-b9a4-4725-9121-48a9c9c8237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072717923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2072717923
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1594128045
Short name T766
Test name
Test status
Simulation time 737708653 ps
CPU time 5.88 seconds
Started Mar 24 02:34:47 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 218464 kb
Host smart-91031f6b-ce45-47e6-98dd-7c777d77eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594128045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1594128045
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2939643863
Short name T1116
Test name
Test status
Simulation time 424628060 ps
CPU time 23.61 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:55:06 PM PDT 24
Peak memory 218296 kb
Host smart-c3524838-2de4-425a-a3f4-1649b1db9a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939643863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2939643863
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.247759583
Short name T115
Test name
Test status
Simulation time 791731959 ps
CPU time 40.09 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 282360 kb
Host smart-d679aed3-2930-4793-b7c5-4d7f0ba743f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247759583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.247759583
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2992493910
Short name T58
Test name
Test status
Simulation time 1025038490 ps
CPU time 39.06 seconds
Started Mar 24 01:54:47 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 268772 kb
Host smart-9a348ff0-05d7-4051-9873-4a008cd3161a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992493910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2992493910
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1958485234
Short name T1449
Test name
Test status
Simulation time 2500396996 ps
CPU time 18.62 seconds
Started Mar 24 01:54:40 PM PDT 24
Finished Mar 24 01:54:59 PM PDT 24
Peak memory 219604 kb
Host smart-adda1d32-5e6d-4537-a236-034b2dd72288
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958485234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1958485234
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.718438636
Short name T1606
Test name
Test status
Simulation time 479248201 ps
CPU time 14.87 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:08 PM PDT 24
Peak memory 218644 kb
Host smart-305ad5c7-3bee-4345-a562-390f81c762ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718438636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.718438636
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3659714947
Short name T665
Test name
Test status
Simulation time 231952194 ps
CPU time 8.48 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:35:01 PM PDT 24
Peak memory 218588 kb
Host smart-de17cf8c-8c08-4656-9e11-e9ea49f6f40b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659714947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3659714947
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.638791627
Short name T1662
Test name
Test status
Simulation time 792530625 ps
CPU time 7.39 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:54:58 PM PDT 24
Peak memory 218532 kb
Host smart-6171528b-d9ae-46f8-a84a-4c7fb5f8a462
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638791627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.638791627
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2335831332
Short name T598
Test name
Test status
Simulation time 896783437 ps
CPU time 7.23 seconds
Started Mar 24 02:34:48 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 218524 kb
Host smart-41e7a590-6055-4089-b84f-c9d241aa0779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335831332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
335831332
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.818331522
Short name T1103
Test name
Test status
Simulation time 1573985866 ps
CPU time 9.95 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 218508 kb
Host smart-21f2e510-db52-4b3f-a5ca-5a79194ba0b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818331522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.818331522
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2258532356
Short name T1649
Test name
Test status
Simulation time 2834758116 ps
CPU time 13.3 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:05 PM PDT 24
Peak memory 226300 kb
Host smart-6d11b99b-36e2-411f-92e6-1c9c6ded74e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258532356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2258532356
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3487333688
Short name T547
Test name
Test status
Simulation time 255123785 ps
CPU time 11.41 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:54:54 PM PDT 24
Peak memory 226896 kb
Host smart-4465de88-e884-403c-8c22-c630f888c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487333688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3487333688
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2682749003
Short name T658
Test name
Test status
Simulation time 64410272 ps
CPU time 3.1 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:55 PM PDT 24
Peak memory 214760 kb
Host smart-e57d35e3-3983-45c3-ac9d-524da3a5761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682749003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2682749003
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.655210347
Short name T1142
Test name
Test status
Simulation time 35798715 ps
CPU time 1.31 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 213920 kb
Host smart-5b5a9b60-5792-4eab-b042-ce3a9dc637f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655210347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.655210347
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2183406439
Short name T228
Test name
Test status
Simulation time 1374276582 ps
CPU time 26.33 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 251456 kb
Host smart-99662a9a-b974-49cd-b8dc-64273f8cfce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183406439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2183406439
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3969832418
Short name T1179
Test name
Test status
Simulation time 344116368 ps
CPU time 32.9 seconds
Started Mar 24 01:54:42 PM PDT 24
Finished Mar 24 01:55:15 PM PDT 24
Peak memory 251284 kb
Host smart-653124da-3b49-4092-aeab-19518923006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969832418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3969832418
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2919083745
Short name T1108
Test name
Test status
Simulation time 223136003 ps
CPU time 2.94 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 222732 kb
Host smart-46bf624d-5e84-4516-889e-e7e550c2aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919083745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2919083745
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.962584752
Short name T1079
Test name
Test status
Simulation time 501356170 ps
CPU time 9.14 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:55:01 PM PDT 24
Peak memory 251464 kb
Host smart-ec9d210f-886a-46f3-a8b6-b73fc86b092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962584752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.962584752
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.3291823436
Short name T791
Test name
Test status
Simulation time 21203334859 ps
CPU time 195.22 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 268616 kb
Host smart-63282e65-f71a-4f85-b34d-e125a17ede9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291823436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.3291823436
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4111475183
Short name T835
Test name
Test status
Simulation time 50511329973 ps
CPU time 168.64 seconds
Started Mar 24 01:54:47 PM PDT 24
Finished Mar 24 01:57:36 PM PDT 24
Peak memory 251552 kb
Host smart-04521582-af09-4725-9074-26af7c7cf062
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111475183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.4111475183
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1176753933
Short name T1204
Test name
Test status
Simulation time 30252053 ps
CPU time 0.98 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 212012 kb
Host smart-b01c85c1-6dd9-4f42-a1b0-c5acc661cfad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176753933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1176753933
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.556251995
Short name T465
Test name
Test status
Simulation time 85364038 ps
CPU time 0.91 seconds
Started Mar 24 02:34:51 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 212112 kb
Host smart-1ab0211a-7220-45fc-888e-387cc3fb7e0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556251995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_volatile_unlock_smoke.556251995
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1281782261
Short name T858
Test name
Test status
Simulation time 24793885 ps
CPU time 0.97 seconds
Started Mar 24 02:36:05 PM PDT 24
Finished Mar 24 02:36:06 PM PDT 24
Peak memory 209904 kb
Host smart-84fed82a-096b-4f3b-aace-d527e0f17b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281782261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1281782261
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3675406937
Short name T1192
Test name
Test status
Simulation time 13698047 ps
CPU time 0.84 seconds
Started Mar 24 01:56:03 PM PDT 24
Finished Mar 24 01:56:05 PM PDT 24
Peak memory 209812 kb
Host smart-53448658-a4d9-4330-ae15-6f42b4225443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675406937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3675406937
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3118796974
Short name T354
Test name
Test status
Simulation time 413008768 ps
CPU time 8.04 seconds
Started Mar 24 02:36:02 PM PDT 24
Finished Mar 24 02:36:10 PM PDT 24
Peak memory 218624 kb
Host smart-77ea84bf-f09d-4f4b-b7c7-d618714617db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118796974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3118796974
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.4103188643
Short name T430
Test name
Test status
Simulation time 500954812 ps
CPU time 9.22 seconds
Started Mar 24 01:56:03 PM PDT 24
Finished Mar 24 01:56:13 PM PDT 24
Peak memory 218592 kb
Host smart-190b4e5c-6bd4-4417-96e2-57cf3f37a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103188643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.4103188643
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2982476150
Short name T1124
Test name
Test status
Simulation time 783968073 ps
CPU time 2.61 seconds
Started Mar 24 02:36:02 PM PDT 24
Finished Mar 24 02:36:05 PM PDT 24
Peak memory 217376 kb
Host smart-4dc889c2-b27c-4870-85b7-d0df393407bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982476150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2982476150
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.49825613
Short name T629
Test name
Test status
Simulation time 867236199 ps
CPU time 6.31 seconds
Started Mar 24 01:56:02 PM PDT 24
Finished Mar 24 01:56:10 PM PDT 24
Peak memory 210252 kb
Host smart-897d817a-dae9-4548-b66d-be602121293a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49825613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.49825613
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.69823228
Short name T814
Test name
Test status
Simulation time 133760794 ps
CPU time 1.75 seconds
Started Mar 24 01:56:07 PM PDT 24
Finished Mar 24 01:56:09 PM PDT 24
Peak memory 218612 kb
Host smart-4b90b1e8-88de-4073-972b-a282555a5a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69823228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.69823228
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.910320796
Short name T336
Test name
Test status
Simulation time 59178020 ps
CPU time 3.17 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:01 PM PDT 24
Peak memory 218588 kb
Host smart-8c57b0db-0fe7-498c-a5aa-b1044ffe9791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910320796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.910320796
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1629557712
Short name T1042
Test name
Test status
Simulation time 1215331085 ps
CPU time 12.27 seconds
Started Mar 24 02:36:01 PM PDT 24
Finished Mar 24 02:36:13 PM PDT 24
Peak memory 219140 kb
Host smart-707aebb9-5815-418b-8223-af3abb8d5457
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629557712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1629557712
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.4147638421
Short name T587
Test name
Test status
Simulation time 378955273 ps
CPU time 10.38 seconds
Started Mar 24 01:56:04 PM PDT 24
Finished Mar 24 01:56:15 PM PDT 24
Peak memory 219488 kb
Host smart-e1c4ae04-95b3-40f8-8d5d-85d8a7ceca23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147638421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.4147638421
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2106757149
Short name T282
Test name
Test status
Simulation time 332483194 ps
CPU time 10.56 seconds
Started Mar 24 01:56:02 PM PDT 24
Finished Mar 24 01:56:15 PM PDT 24
Peak memory 218656 kb
Host smart-c3af6f21-b0ee-446d-a086-52ea112977d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106757149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2106757149
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3317092952
Short name T576
Test name
Test status
Simulation time 1055331938 ps
CPU time 12.71 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:10 PM PDT 24
Peak memory 218580 kb
Host smart-6cfe6c84-3677-47ee-bd8c-2536130d0b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317092952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3317092952
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1579492862
Short name T869
Test name
Test status
Simulation time 1067119984 ps
CPU time 10.19 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 218632 kb
Host smart-1da21c34-a1d0-4d9d-a3b3-334efaea33f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579492862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1579492862
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.518600669
Short name T383
Test name
Test status
Simulation time 704312715 ps
CPU time 15 seconds
Started Mar 24 02:35:59 PM PDT 24
Finished Mar 24 02:36:15 PM PDT 24
Peak memory 218668 kb
Host smart-b23417e1-6ffd-47c0-a611-1210687e6eeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518600669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.518600669
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2087080161
Short name T274
Test name
Test status
Simulation time 561509643 ps
CPU time 9.48 seconds
Started Mar 24 02:36:01 PM PDT 24
Finished Mar 24 02:36:11 PM PDT 24
Peak memory 225472 kb
Host smart-46f4808b-f5b7-4a29-a12d-3845c3afd29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087080161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2087080161
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3315287754
Short name T1049
Test name
Test status
Simulation time 602921124 ps
CPU time 7.28 seconds
Started Mar 24 01:55:59 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 224536 kb
Host smart-3d3768fd-2e04-477f-ae59-262aaa4c0a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315287754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3315287754
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1815345014
Short name T1385
Test name
Test status
Simulation time 13729935 ps
CPU time 1.18 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:36:00 PM PDT 24
Peak memory 213296 kb
Host smart-00cbacad-1aea-40db-add1-cb63e430a636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815345014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1815345014
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.223223283
Short name T446
Test name
Test status
Simulation time 50873188 ps
CPU time 2.56 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:00 PM PDT 24
Peak memory 214736 kb
Host smart-0f620cf3-caf9-48ca-b306-be6ce13834d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223223283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.223223283
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1904573877
Short name T897
Test name
Test status
Simulation time 275860576 ps
CPU time 27.35 seconds
Started Mar 24 02:35:57 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 251476 kb
Host smart-123bd798-5ab1-487f-a5d2-09e3c7d9a77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904573877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1904573877
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2786106019
Short name T673
Test name
Test status
Simulation time 952578813 ps
CPU time 20.48 seconds
Started Mar 24 01:55:57 PM PDT 24
Finished Mar 24 01:56:18 PM PDT 24
Peak memory 251248 kb
Host smart-ec4e1a18-dffc-4d78-a7f8-f15cb862f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786106019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2786106019
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4037978189
Short name T825
Test name
Test status
Simulation time 431096986 ps
CPU time 7.54 seconds
Started Mar 24 02:36:03 PM PDT 24
Finished Mar 24 02:36:10 PM PDT 24
Peak memory 251552 kb
Host smart-61bfb22c-de78-4458-8afc-a30e463e5a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037978189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4037978189
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.4191998636
Short name T1402
Test name
Test status
Simulation time 62893323 ps
CPU time 6.6 seconds
Started Mar 24 01:56:03 PM PDT 24
Finished Mar 24 01:56:10 PM PDT 24
Peak memory 249156 kb
Host smart-606f7b2a-f7d6-4c3e-864d-d4bf00652c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191998636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.4191998636
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.247953439
Short name T89
Test name
Test status
Simulation time 11032665827 ps
CPU time 126.39 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:38:04 PM PDT 24
Peak memory 277036 kb
Host smart-c9d1c0a6-e08c-464a-892a-b07084782937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247953439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.247953439
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3555236672
Short name T1318
Test name
Test status
Simulation time 1365800576 ps
CPU time 43.92 seconds
Started Mar 24 01:56:03 PM PDT 24
Finished Mar 24 01:56:48 PM PDT 24
Peak memory 251416 kb
Host smart-3f1ba531-b825-43b9-a196-a1972fecd193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555236672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3555236672
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2152722472
Short name T299
Test name
Test status
Simulation time 22867647 ps
CPU time 0.81 seconds
Started Mar 24 02:35:58 PM PDT 24
Finished Mar 24 02:35:59 PM PDT 24
Peak memory 209000 kb
Host smart-084bec75-eb77-4395-a023-f5cb743958b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152722472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2152722472
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.840820784
Short name T1592
Test name
Test status
Simulation time 39543015 ps
CPU time 1.39 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:04 PM PDT 24
Peak memory 213052 kb
Host smart-ad3cb97a-7e10-4d3b-8ef0-be51b53716ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840820784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.840820784
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1760241117
Short name T339
Test name
Test status
Simulation time 75268985 ps
CPU time 0.97 seconds
Started Mar 24 02:36:04 PM PDT 24
Finished Mar 24 02:36:05 PM PDT 24
Peak memory 209876 kb
Host smart-b18487a3-26ae-4730-9d05-bbdf6136b7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760241117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1760241117
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3285272833
Short name T1220
Test name
Test status
Simulation time 195769306 ps
CPU time 1.03 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:06 PM PDT 24
Peak memory 209968 kb
Host smart-866f58a2-ca23-49b5-bd31-4f1b275b7419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285272833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3285272833
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1193747716
Short name T1608
Test name
Test status
Simulation time 688618876 ps
CPU time 16.81 seconds
Started Mar 24 02:36:03 PM PDT 24
Finished Mar 24 02:36:20 PM PDT 24
Peak memory 226636 kb
Host smart-fb1f2061-a5b5-4381-85e7-86d131cf748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193747716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1193747716
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1812964887
Short name T1023
Test name
Test status
Simulation time 2862283822 ps
CPU time 8.39 seconds
Started Mar 24 01:56:02 PM PDT 24
Finished Mar 24 01:56:13 PM PDT 24
Peak memory 210060 kb
Host smart-c6bf8294-8908-4135-9909-ae89e1b1d293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812964887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1812964887
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3370957421
Short name T431
Test name
Test status
Simulation time 12282914579 ps
CPU time 14.07 seconds
Started Mar 24 02:36:06 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 210108 kb
Host smart-d91b1924-da58-4dc6-a054-f691025e51a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370957421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3370957421
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2287096550
Short name T1327
Test name
Test status
Simulation time 71716895 ps
CPU time 3.87 seconds
Started Mar 24 02:36:02 PM PDT 24
Finished Mar 24 02:36:06 PM PDT 24
Peak memory 222672 kb
Host smart-2b12d1f3-d3a3-46fd-8b96-dc7f7d1ea381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287096550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2287096550
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.503472810
Short name T551
Test name
Test status
Simulation time 31561679 ps
CPU time 2.29 seconds
Started Mar 24 01:56:06 PM PDT 24
Finished Mar 24 01:56:10 PM PDT 24
Peak memory 222368 kb
Host smart-bc5a992d-cfcf-4279-8ab3-421b8965b258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503472810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.503472810
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1052597475
Short name T1698
Test name
Test status
Simulation time 1323584899 ps
CPU time 16.22 seconds
Started Mar 24 02:36:04 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 226652 kb
Host smart-94b7cd9d-b1e6-45c8-87af-77b9e6c1b788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052597475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1052597475
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.456100907
Short name T1126
Test name
Test status
Simulation time 650262027 ps
CPU time 11.35 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:14 PM PDT 24
Peak memory 226640 kb
Host smart-5e13cb76-5069-4fa5-9310-d86e0ab03dcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456100907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.456100907
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1408120848
Short name T584
Test name
Test status
Simulation time 890227627 ps
CPU time 9.99 seconds
Started Mar 24 01:56:02 PM PDT 24
Finished Mar 24 01:56:14 PM PDT 24
Peak memory 218532 kb
Host smart-b3b290eb-fa64-4999-8aa6-18c69924e30c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408120848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1408120848
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2459102456
Short name T526
Test name
Test status
Simulation time 1426861956 ps
CPU time 17.18 seconds
Started Mar 24 02:36:07 PM PDT 24
Finished Mar 24 02:36:24 PM PDT 24
Peak memory 218564 kb
Host smart-9b573dde-fe33-4bdb-b28f-5f5465b86042
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459102456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2459102456
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3774122946
Short name T622
Test name
Test status
Simulation time 229258878 ps
CPU time 9.7 seconds
Started Mar 24 01:56:02 PM PDT 24
Finished Mar 24 01:56:14 PM PDT 24
Peak memory 218576 kb
Host smart-cc804ff1-6eec-4e0c-9c68-674738b85087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774122946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3774122946
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4201318344
Short name T1304
Test name
Test status
Simulation time 251933112 ps
CPU time 10.05 seconds
Started Mar 24 02:36:02 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 218552 kb
Host smart-243251b4-17d8-4dbf-a526-e599ace9a7d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201318344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4201318344
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3872086966
Short name T745
Test name
Test status
Simulation time 540467525 ps
CPU time 10.34 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:11 PM PDT 24
Peak memory 226680 kb
Host smart-1b58275d-dd27-4d8e-b6dd-b3fdb50519a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872086966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3872086966
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.497434863
Short name T1410
Test name
Test status
Simulation time 1541480587 ps
CPU time 9.75 seconds
Started Mar 24 02:36:06 PM PDT 24
Finished Mar 24 02:36:15 PM PDT 24
Peak memory 226656 kb
Host smart-927f6d44-6aa7-4bac-aeaf-f8c79ec32265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497434863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.497434863
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1323982864
Short name T824
Test name
Test status
Simulation time 28776203 ps
CPU time 1.46 seconds
Started Mar 24 02:36:02 PM PDT 24
Finished Mar 24 02:36:03 PM PDT 24
Peak memory 213720 kb
Host smart-51126796-4ef2-4474-9e5f-96a06c93bcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323982864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1323982864
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.31878676
Short name T1689
Test name
Test status
Simulation time 207999734 ps
CPU time 3.35 seconds
Started Mar 24 01:56:02 PM PDT 24
Finished Mar 24 01:56:08 PM PDT 24
Peak memory 218348 kb
Host smart-ba1b9899-4d32-4bd6-97d3-817cb09c40a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31878676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.31878676
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1336978285
Short name T311
Test name
Test status
Simulation time 279299264 ps
CPU time 33.25 seconds
Started Mar 24 02:36:04 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 251496 kb
Host smart-6d0bbf55-da7d-436b-9ed6-2acac82e82f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336978285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1336978285
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2391337329
Short name T743
Test name
Test status
Simulation time 617511966 ps
CPU time 35.77 seconds
Started Mar 24 01:56:04 PM PDT 24
Finished Mar 24 01:56:41 PM PDT 24
Peak memory 251548 kb
Host smart-ba7cb9f1-7a27-4b8a-af90-4cf586d048b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391337329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2391337329
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2399793909
Short name T367
Test name
Test status
Simulation time 665520028 ps
CPU time 8.17 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:11 PM PDT 24
Peak memory 251488 kb
Host smart-6b78a8fa-969f-4203-86f0-11d2b27bfc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399793909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2399793909
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2792368808
Short name T699
Test name
Test status
Simulation time 148189201 ps
CPU time 7.69 seconds
Started Mar 24 02:36:05 PM PDT 24
Finished Mar 24 02:36:13 PM PDT 24
Peak memory 247224 kb
Host smart-0ac622f0-47c3-4729-b433-d0a0b226410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792368808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2792368808
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2693284612
Short name T1283
Test name
Test status
Simulation time 24706412311 ps
CPU time 223.71 seconds
Started Mar 24 01:56:04 PM PDT 24
Finished Mar 24 01:59:49 PM PDT 24
Peak memory 251528 kb
Host smart-1f39e1fa-ec9a-4e01-8f58-11b41728c2d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693284612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2693284612
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.71798838
Short name T885
Test name
Test status
Simulation time 10111154881 ps
CPU time 131.4 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 277184 kb
Host smart-f5e51c12-f4ff-462d-907a-f6b632ff2438
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71798838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.lc_ctrl_stress_all.71798838
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1217288643
Short name T485
Test name
Test status
Simulation time 12805156 ps
CPU time 0.84 seconds
Started Mar 24 01:56:01 PM PDT 24
Finished Mar 24 01:56:02 PM PDT 24
Peak memory 209036 kb
Host smart-45d12c9c-1d9a-4865-8676-64131d28a0db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217288643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1217288643
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2282144416
Short name T1326
Test name
Test status
Simulation time 29532697 ps
CPU time 0.77 seconds
Started Mar 24 02:36:03 PM PDT 24
Finished Mar 24 02:36:03 PM PDT 24
Peak memory 208908 kb
Host smart-47df204e-d539-47a6-8e07-62afcf877633
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282144416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.2282144416
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2798947886
Short name T93
Test name
Test status
Simulation time 22442121 ps
CPU time 1.09 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:14 PM PDT 24
Peak memory 209976 kb
Host smart-e7b5aff2-813e-4373-a7e7-51b45f84726d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798947886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2798947886
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.888210491
Short name T1397
Test name
Test status
Simulation time 11802137 ps
CPU time 0.89 seconds
Started Mar 24 02:36:07 PM PDT 24
Finished Mar 24 02:36:08 PM PDT 24
Peak memory 209740 kb
Host smart-750b2bea-7a15-44a3-9529-de0e4986acd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888210491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.888210491
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2149647205
Short name T297
Test name
Test status
Simulation time 309609444 ps
CPU time 12.03 seconds
Started Mar 24 02:36:05 PM PDT 24
Finished Mar 24 02:36:17 PM PDT 24
Peak memory 218680 kb
Host smart-9df495b2-deda-469e-b57a-799f8cf78463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149647205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2149647205
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2556391328
Short name T1542
Test name
Test status
Simulation time 5799645214 ps
CPU time 13.61 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:20 PM PDT 24
Peak memory 218912 kb
Host smart-a8441f30-ebd3-476a-9c68-814dc4999edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556391328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2556391328
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3066189399
Short name T829
Test name
Test status
Simulation time 109172107 ps
CPU time 2.07 seconds
Started Mar 24 01:56:06 PM PDT 24
Finished Mar 24 01:56:09 PM PDT 24
Peak memory 210020 kb
Host smart-467db8ec-109c-41fd-815d-435761165226
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066189399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3066189399
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3129306509
Short name T1567
Test name
Test status
Simulation time 1598961397 ps
CPU time 6.04 seconds
Started Mar 24 02:36:09 PM PDT 24
Finished Mar 24 02:36:15 PM PDT 24
Peak memory 217840 kb
Host smart-42eaff88-9f2f-4aa7-b6e5-5c097a92c574
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129306509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3129306509
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2391953617
Short name T554
Test name
Test status
Simulation time 120663697 ps
CPU time 3.73 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:10 PM PDT 24
Peak memory 222732 kb
Host smart-ba183402-6f0d-42e7-abec-abd0dc745d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391953617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2391953617
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3479966537
Short name T1277
Test name
Test status
Simulation time 28025444 ps
CPU time 1.71 seconds
Started Mar 24 02:36:04 PM PDT 24
Finished Mar 24 02:36:06 PM PDT 24
Peak memory 218652 kb
Host smart-590e2f5d-cab2-40bb-b57b-eb9a4e624cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479966537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3479966537
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1846265264
Short name T1171
Test name
Test status
Simulation time 409102987 ps
CPU time 16.21 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:22 PM PDT 24
Peak memory 219512 kb
Host smart-50335ee9-270f-4e46-916c-4d2e47113f1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846265264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1846265264
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1944817303
Short name T1128
Test name
Test status
Simulation time 390309170 ps
CPU time 8.49 seconds
Started Mar 24 02:36:09 PM PDT 24
Finished Mar 24 02:36:18 PM PDT 24
Peak memory 218660 kb
Host smart-1c9b6886-c30e-419d-a5f9-b582aec15128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944817303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1944817303
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.703518964
Short name T1663
Test name
Test status
Simulation time 2659872287 ps
CPU time 17.62 seconds
Started Mar 24 01:56:07 PM PDT 24
Finished Mar 24 01:56:25 PM PDT 24
Peak memory 218628 kb
Host smart-f6cdb002-660e-4ccb-8c18-9ea1f4894c19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703518964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.703518964
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.808022235
Short name T529
Test name
Test status
Simulation time 375433372 ps
CPU time 12.08 seconds
Started Mar 24 02:36:11 PM PDT 24
Finished Mar 24 02:36:24 PM PDT 24
Peak memory 218556 kb
Host smart-c22cb9eb-46aa-4aa4-82c8-84f7aaef8a98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808022235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.808022235
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3266957485
Short name T1465
Test name
Test status
Simulation time 258713241 ps
CPU time 7.08 seconds
Started Mar 24 01:56:07 PM PDT 24
Finished Mar 24 01:56:15 PM PDT 24
Peak memory 218540 kb
Host smart-06180596-6797-43de-83a8-0870584619c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266957485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3266957485
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.713668619
Short name T708
Test name
Test status
Simulation time 365249321 ps
CPU time 9.11 seconds
Started Mar 24 02:36:10 PM PDT 24
Finished Mar 24 02:36:20 PM PDT 24
Peak memory 218652 kb
Host smart-319b5f2e-6246-4017-afb7-7e22ccb7156e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713668619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.713668619
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.132322598
Short name T1352
Test name
Test status
Simulation time 1037100602 ps
CPU time 8.59 seconds
Started Mar 24 02:36:03 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 226672 kb
Host smart-78baae3e-d05c-48b8-92b6-4bd04021dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132322598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.132322598
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.4287103188
Short name T1674
Test name
Test status
Simulation time 639223627 ps
CPU time 8.68 seconds
Started Mar 24 01:56:06 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 225656 kb
Host smart-9b98917b-faa1-4622-9836-07d1e1a13955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287103188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4287103188
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.272649086
Short name T603
Test name
Test status
Simulation time 635120359 ps
CPU time 3.19 seconds
Started Mar 24 02:36:04 PM PDT 24
Finished Mar 24 02:36:07 PM PDT 24
Peak memory 214820 kb
Host smart-33c6c8dc-44d8-4210-a582-de106f8a621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272649086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.272649086
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4053380086
Short name T82
Test name
Test status
Simulation time 269729675 ps
CPU time 1.98 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 214168 kb
Host smart-b0be5046-5c42-40ab-8365-c2a60e69cb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053380086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4053380086
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.1360522401
Short name T757
Test name
Test status
Simulation time 384640685 ps
CPU time 32.26 seconds
Started Mar 24 02:36:05 PM PDT 24
Finished Mar 24 02:36:38 PM PDT 24
Peak memory 251608 kb
Host smart-270f1c54-f808-44a5-96e9-29fc92229f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360522401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1360522401
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3195183598
Short name T504
Test name
Test status
Simulation time 342333521 ps
CPU time 34.24 seconds
Started Mar 24 01:56:06 PM PDT 24
Finished Mar 24 01:56:41 PM PDT 24
Peak memory 251412 kb
Host smart-60d3b93a-62d6-4ddf-9fac-130ddd3ed825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195183598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3195183598
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1464437520
Short name T1660
Test name
Test status
Simulation time 125743363 ps
CPU time 6.46 seconds
Started Mar 24 02:36:02 PM PDT 24
Finished Mar 24 02:36:09 PM PDT 24
Peak memory 250904 kb
Host smart-34ba12e6-8c4a-4391-82d0-a01de91be3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464437520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1464437520
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1786015926
Short name T736
Test name
Test status
Simulation time 399208791 ps
CPU time 3.68 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:10 PM PDT 24
Peak memory 223080 kb
Host smart-18d6395c-511f-4d74-a870-58de40238ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786015926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1786015926
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2868732529
Short name T990
Test name
Test status
Simulation time 12763594082 ps
CPU time 272.41 seconds
Started Mar 24 02:36:07 PM PDT 24
Finished Mar 24 02:40:40 PM PDT 24
Peak memory 226740 kb
Host smart-baf4d912-b49e-41cb-a1fe-c3d0dd4bc8d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868732529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2868732529
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3161112745
Short name T1302
Test name
Test status
Simulation time 4212191104 ps
CPU time 53.3 seconds
Started Mar 24 01:56:12 PM PDT 24
Finished Mar 24 01:57:05 PM PDT 24
Peak memory 251572 kb
Host smart-7cd2bddf-dda1-4b9f-b0b8-ea936aebbd1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161112745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3161112745
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1420039731
Short name T95
Test name
Test status
Simulation time 33076712161 ps
CPU time 630 seconds
Started Mar 24 02:36:10 PM PDT 24
Finished Mar 24 02:46:40 PM PDT 24
Peak memory 563004 kb
Host smart-690f0a66-ee83-4203-8f2b-a1b5e2b9c69a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1420039731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1420039731
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.155337945
Short name T382
Test name
Test status
Simulation time 15567674 ps
CPU time 0.96 seconds
Started Mar 24 02:36:06 PM PDT 24
Finished Mar 24 02:36:07 PM PDT 24
Peak memory 209248 kb
Host smart-c4ca7dfd-23c2-4f60-a32e-30f24721f6e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155337945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.155337945
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2498683707
Short name T1458
Test name
Test status
Simulation time 17039967 ps
CPU time 0.78 seconds
Started Mar 24 01:56:05 PM PDT 24
Finished Mar 24 01:56:07 PM PDT 24
Peak memory 209104 kb
Host smart-37223a8a-1ad0-47cc-8867-18c8c5534316
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498683707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2498683707
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3733199415
Short name T1298
Test name
Test status
Simulation time 27772153 ps
CPU time 0.9 seconds
Started Mar 24 01:56:14 PM PDT 24
Finished Mar 24 01:56:15 PM PDT 24
Peak memory 209984 kb
Host smart-57de2dee-79a0-41f9-80ee-d038f7586376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733199415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3733199415
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4289647775
Short name T1591
Test name
Test status
Simulation time 18377114 ps
CPU time 0.94 seconds
Started Mar 24 02:36:12 PM PDT 24
Finished Mar 24 02:36:13 PM PDT 24
Peak memory 209964 kb
Host smart-9c805544-7d4c-4b64-bf86-25ef8a676567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289647775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4289647775
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3417895725
Short name T1474
Test name
Test status
Simulation time 297487464 ps
CPU time 13.07 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 218604 kb
Host smart-b69c16bc-83f7-451c-90c9-f676a46d26ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417895725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3417895725
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.648857791
Short name T760
Test name
Test status
Simulation time 3493986490 ps
CPU time 13.23 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 219628 kb
Host smart-61aa9376-d99a-4786-942d-c902f4903e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648857791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.648857791
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.733351569
Short name T235
Test name
Test status
Simulation time 189318299 ps
CPU time 2.57 seconds
Started Mar 24 02:36:07 PM PDT 24
Finished Mar 24 02:36:10 PM PDT 24
Peak memory 210048 kb
Host smart-3f8352fd-3677-4fc1-9423-b651cff760a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733351569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.733351569
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.919661819
Short name T106
Test name
Test status
Simulation time 92874437 ps
CPU time 2 seconds
Started Mar 24 01:56:14 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 210032 kb
Host smart-12dc44c5-5fd6-4952-9ceb-dde2ad0b5eae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919661819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.919661819
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2054567917
Short name T624
Test name
Test status
Simulation time 85536052 ps
CPU time 1.54 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:36:09 PM PDT 24
Peak memory 221764 kb
Host smart-1a79c1cb-c2f5-48bd-b27a-87854350a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054567917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2054567917
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3364398102
Short name T1344
Test name
Test status
Simulation time 133759517 ps
CPU time 2.75 seconds
Started Mar 24 01:56:14 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 222308 kb
Host smart-df6374b2-0625-45ce-8607-1653193cc96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364398102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3364398102
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1098402133
Short name T1593
Test name
Test status
Simulation time 599896654 ps
CPU time 10.56 seconds
Started Mar 24 02:36:10 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 219536 kb
Host smart-34abc4c8-0f37-479a-bdee-24e4d7f09208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098402133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1098402133
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1600673877
Short name T734
Test name
Test status
Simulation time 436633496 ps
CPU time 18.79 seconds
Started Mar 24 01:56:10 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 219524 kb
Host smart-6b007cc6-cc81-44f6-a42f-ad6a53cc4208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600673877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1600673877
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1761571259
Short name T185
Test name
Test status
Simulation time 661397910 ps
CPU time 8.49 seconds
Started Mar 24 02:36:09 PM PDT 24
Finished Mar 24 02:36:18 PM PDT 24
Peak memory 218564 kb
Host smart-b9795079-6821-4ed0-9dec-a005f3319f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761571259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1761571259
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.747922573
Short name T1077
Test name
Test status
Simulation time 884048205 ps
CPU time 8.93 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 218204 kb
Host smart-3f9226c5-8d8b-4ec1-bdde-4c8db58a7bb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747922573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.747922573
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1100993698
Short name T949
Test name
Test status
Simulation time 902271010 ps
CPU time 9.26 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:36:17 PM PDT 24
Peak memory 218484 kb
Host smart-52fc1399-fde4-498c-a87a-84f95691f6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100993698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1100993698
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3060245976
Short name T451
Test name
Test status
Simulation time 192840810 ps
CPU time 7.35 seconds
Started Mar 24 01:56:11 PM PDT 24
Finished Mar 24 01:56:18 PM PDT 24
Peak memory 218632 kb
Host smart-4bcf6264-71a5-4bf6-96ab-7e6df273ef3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060245976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3060245976
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.222807040
Short name T482
Test name
Test status
Simulation time 4967299187 ps
CPU time 8.69 seconds
Started Mar 24 01:56:11 PM PDT 24
Finished Mar 24 01:56:20 PM PDT 24
Peak memory 226116 kb
Host smart-2b78967d-114b-47f8-aa47-b658740c8b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222807040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.222807040
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3548210687
Short name T275
Test name
Test status
Simulation time 5405469156 ps
CPU time 9.08 seconds
Started Mar 24 02:36:10 PM PDT 24
Finished Mar 24 02:36:19 PM PDT 24
Peak memory 226732 kb
Host smart-107c3381-43bb-4cfb-ab77-c087f1c51e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548210687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3548210687
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.190178983
Short name T486
Test name
Test status
Simulation time 33735471 ps
CPU time 1.7 seconds
Started Mar 24 01:56:10 PM PDT 24
Finished Mar 24 01:56:12 PM PDT 24
Peak memory 214120 kb
Host smart-89ed417a-7a6b-48e3-96e9-02cde8d4cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190178983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.190178983
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.4034091874
Short name T503
Test name
Test status
Simulation time 130001562 ps
CPU time 2.39 seconds
Started Mar 24 02:36:09 PM PDT 24
Finished Mar 24 02:36:11 PM PDT 24
Peak memory 218292 kb
Host smart-accb1100-4ef3-4aa6-959d-0b51e9b5dabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034091874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.4034091874
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.157288866
Short name T1522
Test name
Test status
Simulation time 4280350887 ps
CPU time 16.31 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 251552 kb
Host smart-7151abfa-a4c1-408a-a6fd-71f847ab936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157288866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.157288866
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2198982354
Short name T871
Test name
Test status
Simulation time 1792542722 ps
CPU time 29.84 seconds
Started Mar 24 01:56:14 PM PDT 24
Finished Mar 24 01:56:44 PM PDT 24
Peak memory 251528 kb
Host smart-3b04863b-ff2f-458c-a463-60ea8092f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198982354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2198982354
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2000126250
Short name T1629
Test name
Test status
Simulation time 272632254 ps
CPU time 7.22 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:20 PM PDT 24
Peak memory 251512 kb
Host smart-ee7fa99d-0979-480d-ad6b-714f8876cbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000126250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2000126250
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2599791015
Short name T833
Test name
Test status
Simulation time 76965878 ps
CPU time 4.06 seconds
Started Mar 24 02:36:08 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 226916 kb
Host smart-73298354-2281-478e-86b9-6af1ba43ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599791015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2599791015
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.2381571588
Short name T1409
Test name
Test status
Simulation time 2137715318 ps
CPU time 40.02 seconds
Started Mar 24 01:56:12 PM PDT 24
Finished Mar 24 01:56:52 PM PDT 24
Peak memory 226684 kb
Host smart-6f866a76-b74a-4a42-939f-b85d958d12df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381571588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.2381571588
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2340528186
Short name T933
Test name
Test status
Simulation time 55363518366 ps
CPU time 527.89 seconds
Started Mar 24 01:56:11 PM PDT 24
Finished Mar 24 02:04:59 PM PDT 24
Peak memory 349940 kb
Host smart-37ebdf28-375c-4ef7-a4aa-2c780a183318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2340528186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2340528186
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3888387998
Short name T1162
Test name
Test status
Simulation time 119684801491 ps
CPU time 354.79 seconds
Started Mar 24 02:36:07 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 284372 kb
Host smart-a0d99cba-a3cb-4bb9-9d4e-8b4cc7f44843
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3888387998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3888387998
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2804422142
Short name T1561
Test name
Test status
Simulation time 11898060 ps
CPU time 0.8 seconds
Started Mar 24 02:36:11 PM PDT 24
Finished Mar 24 02:36:12 PM PDT 24
Peak memory 209024 kb
Host smart-aa7565bd-d703-481f-a332-1d5fa94daa96
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804422142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2804422142
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3367677616
Short name T1607
Test name
Test status
Simulation time 25222922 ps
CPU time 0.92 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:14 PM PDT 24
Peak memory 212024 kb
Host smart-3a79b25d-0f1f-4970-b868-a6cafe278f8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367677616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3367677616
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1099369991
Short name T77
Test name
Test status
Simulation time 54804722 ps
CPU time 1.19 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 209924 kb
Host smart-7fb072e6-c0b1-484d-98f5-b074fafcbc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099369991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1099369991
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.387308969
Short name T938
Test name
Test status
Simulation time 16066440 ps
CPU time 0.87 seconds
Started Mar 24 02:36:18 PM PDT 24
Finished Mar 24 02:36:19 PM PDT 24
Peak memory 209976 kb
Host smart-21569976-c71b-40a9-b422-2f91cc12b77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387308969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.387308969
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2493457092
Short name T733
Test name
Test status
Simulation time 193601474 ps
CPU time 10.79 seconds
Started Mar 24 02:36:15 PM PDT 24
Finished Mar 24 02:36:26 PM PDT 24
Peak memory 218640 kb
Host smart-b4e6503a-d6d3-4747-96fa-636c6f82db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493457092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2493457092
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3568515818
Short name T122
Test name
Test status
Simulation time 1617244606 ps
CPU time 19.91 seconds
Started Mar 24 01:56:10 PM PDT 24
Finished Mar 24 01:56:30 PM PDT 24
Peak memory 218564 kb
Host smart-8cc0dc37-089e-4c04-aa1f-d2470d6160b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568515818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3568515818
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1172034290
Short name T1308
Test name
Test status
Simulation time 215993070 ps
CPU time 1.33 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 210032 kb
Host smart-f85b32db-f7e8-4c4c-bcb3-b2082d764160
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172034290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1172034290
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.531565564
Short name T1040
Test name
Test status
Simulation time 300435834 ps
CPU time 2.72 seconds
Started Mar 24 02:36:13 PM PDT 24
Finished Mar 24 02:36:16 PM PDT 24
Peak memory 217364 kb
Host smart-0eff611f-c1d2-4368-aeef-0498e41322fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531565564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.531565564
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1758192662
Short name T891
Test name
Test status
Simulation time 191899956 ps
CPU time 3.15 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 218620 kb
Host smart-4ab07778-0abb-47e4-a63d-454c34c2d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758192662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1758192662
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3722477524
Short name T1342
Test name
Test status
Simulation time 27251821 ps
CPU time 2.23 seconds
Started Mar 24 02:36:17 PM PDT 24
Finished Mar 24 02:36:20 PM PDT 24
Peak memory 222268 kb
Host smart-43f6ebbc-ceba-4013-be58-f41676fe4ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722477524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3722477524
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1333342856
Short name T1038
Test name
Test status
Simulation time 891977270 ps
CPU time 9.61 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:27 PM PDT 24
Peak memory 218844 kb
Host smart-49498045-5b61-4bbd-b047-9db29e1540c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333342856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1333342856
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2801756656
Short name T1550
Test name
Test status
Simulation time 651055614 ps
CPU time 14.25 seconds
Started Mar 24 02:36:17 PM PDT 24
Finished Mar 24 02:36:31 PM PDT 24
Peak memory 219492 kb
Host smart-b0f69c6a-aa5f-4a3d-9946-59cd776935f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801756656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2801756656
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.3444307698
Short name T227
Test name
Test status
Simulation time 225828966 ps
CPU time 10.53 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 218652 kb
Host smart-df34720d-a1c0-4844-9207-2b70144e7d32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444307698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.3444307698
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.443609088
Short name T1339
Test name
Test status
Simulation time 273582457 ps
CPU time 12.44 seconds
Started Mar 24 02:36:12 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 218648 kb
Host smart-813caba2-f345-4a49-b9e4-ab3110de54c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443609088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.443609088
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.202105643
Short name T288
Test name
Test status
Simulation time 893858084 ps
CPU time 8.79 seconds
Started Mar 24 02:36:13 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 218588 kb
Host smart-888ebdbc-b966-4b30-83e4-eb536df10df4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202105643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.202105643
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.523044328
Short name T1675
Test name
Test status
Simulation time 1557465311 ps
CPU time 10.46 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:28 PM PDT 24
Peak memory 218532 kb
Host smart-70e8314b-0cbf-42ab-810b-396e95f25e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523044328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.523044328
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2554642917
Short name T552
Test name
Test status
Simulation time 287642058 ps
CPU time 7.45 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:28 PM PDT 24
Peak memory 225404 kb
Host smart-ecc7cf81-297e-4abf-ac39-19aa996bbfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554642917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2554642917
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3682247532
Short name T926
Test name
Test status
Simulation time 437201749 ps
CPU time 11.28 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:28 PM PDT 24
Peak memory 225984 kb
Host smart-46653a72-fe84-4212-8810-4881442936eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682247532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3682247532
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1704436335
Short name T461
Test name
Test status
Simulation time 82381751 ps
CPU time 1.72 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:15 PM PDT 24
Peak memory 214296 kb
Host smart-60fc6462-9813-4a5d-a94d-4e62e1429921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704436335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1704436335
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2821643428
Short name T543
Test name
Test status
Simulation time 91781468 ps
CPU time 1.55 seconds
Started Mar 24 02:36:19 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 213312 kb
Host smart-a4b86f86-505a-47df-b645-29c6459191a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821643428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2821643428
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1548965618
Short name T1178
Test name
Test status
Simulation time 597044750 ps
CPU time 19.42 seconds
Started Mar 24 02:36:13 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 251496 kb
Host smart-ef33a2cb-ac26-4614-ad40-842034d9e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548965618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1548965618
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2702728026
Short name T550
Test name
Test status
Simulation time 1028919855 ps
CPU time 31.14 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:44 PM PDT 24
Peak memory 251728 kb
Host smart-8833cf56-07bc-4ef8-bd7a-e60d58648494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702728026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2702728026
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3315473790
Short name T1516
Test name
Test status
Simulation time 56961323 ps
CPU time 9.07 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:22 PM PDT 24
Peak memory 251480 kb
Host smart-174cf373-86c0-49f4-8946-53ec93662f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315473790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3315473790
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3454199321
Short name T1358
Test name
Test status
Simulation time 418677270 ps
CPU time 3.59 seconds
Started Mar 24 02:36:17 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 222820 kb
Host smart-04bf9bbb-d83e-4055-be75-3b8d085fa1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454199321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3454199321
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1865059266
Short name T1083
Test name
Test status
Simulation time 7675234357 ps
CPU time 142.71 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:58:41 PM PDT 24
Peak memory 284276 kb
Host smart-c26afea8-1196-46db-95f2-c031021cf880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865059266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1865059266
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.2522722532
Short name T540
Test name
Test status
Simulation time 35712452080 ps
CPU time 119.01 seconds
Started Mar 24 02:36:14 PM PDT 24
Finished Mar 24 02:38:13 PM PDT 24
Peak memory 225208 kb
Host smart-dbabc20e-3354-490c-8684-db582ef035ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522722532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.2522722532
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.354637504
Short name T1292
Test name
Test status
Simulation time 19636880 ps
CPU time 0.77 seconds
Started Mar 24 02:36:14 PM PDT 24
Finished Mar 24 02:36:15 PM PDT 24
Peak memory 209076 kb
Host smart-eea41ed7-aa61-4c3a-97b5-cdefaea54aae
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354637504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.354637504
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3900027549
Short name T442
Test name
Test status
Simulation time 15381486 ps
CPU time 1.21 seconds
Started Mar 24 01:56:13 PM PDT 24
Finished Mar 24 01:56:14 PM PDT 24
Peak memory 212120 kb
Host smart-99c935d0-7512-4dca-b314-2bbc9f20b4ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900027549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3900027549
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1081757751
Short name T836
Test name
Test status
Simulation time 55087417 ps
CPU time 0.87 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 209952 kb
Host smart-3d9d3fb8-0a2b-4d39-bf93-64da5d019e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081757751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1081757751
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2029234474
Short name T1216
Test name
Test status
Simulation time 21442260 ps
CPU time 0.78 seconds
Started Mar 24 02:36:26 PM PDT 24
Finished Mar 24 02:36:27 PM PDT 24
Peak memory 209752 kb
Host smart-de765e3d-b21a-4705-b261-f837d3fd5fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029234474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2029234474
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1837039271
Short name T189
Test name
Test status
Simulation time 280827950 ps
CPU time 14.51 seconds
Started Mar 24 02:36:14 PM PDT 24
Finished Mar 24 02:36:29 PM PDT 24
Peak memory 218608 kb
Host smart-46b8fc5d-cc6f-4431-b3d9-2b6fa0e6f850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837039271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1837039271
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2110621595
Short name T1334
Test name
Test status
Simulation time 208186721 ps
CPU time 9.82 seconds
Started Mar 24 01:56:20 PM PDT 24
Finished Mar 24 01:56:30 PM PDT 24
Peak memory 218512 kb
Host smart-b8a437b9-34f3-4aea-938f-b30e4df58d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110621595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2110621595
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1175717512
Short name T732
Test name
Test status
Simulation time 1535762226 ps
CPU time 11 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:28 PM PDT 24
Peak memory 217856 kb
Host smart-13e15672-af91-492d-a03f-996efc4b0966
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175717512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1175717512
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.4111483733
Short name T28
Test name
Test status
Simulation time 3065100802 ps
CPU time 5.17 seconds
Started Mar 24 02:36:25 PM PDT 24
Finished Mar 24 02:36:31 PM PDT 24
Peak memory 210136 kb
Host smart-c1314fea-7fcf-4e68-9222-0153893580b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111483733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4111483733
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1118056937
Short name T1514
Test name
Test status
Simulation time 412627015 ps
CPU time 3.86 seconds
Started Mar 24 02:36:13 PM PDT 24
Finished Mar 24 02:36:17 PM PDT 24
Peak memory 222416 kb
Host smart-d913d0d1-c445-4ee9-99f2-6302409a9c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118056937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1118056937
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3051031285
Short name T626
Test name
Test status
Simulation time 66377237 ps
CPU time 2.14 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 218596 kb
Host smart-9e9d8ba3-26de-48f3-bdf2-e12836a14c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051031285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3051031285
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.16362976
Short name T1554
Test name
Test status
Simulation time 899722720 ps
CPU time 14.34 seconds
Started Mar 24 01:56:16 PM PDT 24
Finished Mar 24 01:56:31 PM PDT 24
Peak memory 219500 kb
Host smart-e610397b-fc8f-4594-b4be-23224607273f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16362976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.16362976
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2700017386
Short name T1690
Test name
Test status
Simulation time 264804849 ps
CPU time 13.17 seconds
Started Mar 24 02:36:21 PM PDT 24
Finished Mar 24 02:36:34 PM PDT 24
Peak memory 219756 kb
Host smart-8e0e3723-e1cd-4fb9-a565-89c9e0dacc55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700017386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2700017386
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1291502766
Short name T107
Test name
Test status
Simulation time 1570620491 ps
CPU time 12.08 seconds
Started Mar 24 01:56:20 PM PDT 24
Finished Mar 24 01:56:32 PM PDT 24
Peak memory 218508 kb
Host smart-b39e1c73-ccbb-4828-ae21-1b5745333860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291502766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1291502766
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1747673162
Short name T881
Test name
Test status
Simulation time 2744773827 ps
CPU time 11.28 seconds
Started Mar 24 02:36:15 PM PDT 24
Finished Mar 24 02:36:27 PM PDT 24
Peak memory 218476 kb
Host smart-2fadf8d5-fce7-4f67-8294-a8c86be7c2f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747673162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1747673162
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1837316138
Short name T322
Test name
Test status
Simulation time 2011774524 ps
CPU time 11.27 seconds
Started Mar 24 02:36:12 PM PDT 24
Finished Mar 24 02:36:23 PM PDT 24
Peak memory 218568 kb
Host smart-28658840-7ada-4405-93e9-30fa31a57e7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837316138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1837316138
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1930966998
Short name T839
Test name
Test status
Simulation time 973847774 ps
CPU time 6.98 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:24 PM PDT 24
Peak memory 218472 kb
Host smart-e9827d07-1605-4bb0-bd70-2a6e85728f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930966998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1930966998
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.33996649
Short name T1276
Test name
Test status
Simulation time 1301495462 ps
CPU time 10.58 seconds
Started Mar 24 02:36:15 PM PDT 24
Finished Mar 24 02:36:26 PM PDT 24
Peak memory 225480 kb
Host smart-0da2866f-2c21-4956-8358-b695f763fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33996649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.33996649
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.784800652
Short name T1297
Test name
Test status
Simulation time 385086322 ps
CPU time 9.89 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:27 PM PDT 24
Peak memory 225136 kb
Host smart-559f432d-3773-405a-882d-00a12497e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784800652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.784800652
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2125176310
Short name T63
Test name
Test status
Simulation time 37185007 ps
CPU time 2.35 seconds
Started Mar 24 01:56:16 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 214756 kb
Host smart-5bb32a62-4fd4-4d39-9899-88ebf23114f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125176310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2125176310
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.311061204
Short name T1285
Test name
Test status
Simulation time 45027507 ps
CPU time 3.1 seconds
Started Mar 24 02:36:17 PM PDT 24
Finished Mar 24 02:36:21 PM PDT 24
Peak memory 215160 kb
Host smart-8105a036-e5c6-4fb4-a17e-db3d42e4e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311061204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.311061204
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.281437702
Short name T108
Test name
Test status
Simulation time 1898403160 ps
CPU time 20.04 seconds
Started Mar 24 02:36:18 PM PDT 24
Finished Mar 24 02:36:38 PM PDT 24
Peak memory 246316 kb
Host smart-439b0cb5-47ce-424b-b64f-cac5ebe6779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281437702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.281437702
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.789591181
Short name T1705
Test name
Test status
Simulation time 290078958 ps
CPU time 26.66 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:45 PM PDT 24
Peak memory 251524 kb
Host smart-592361e0-ad14-4121-943c-2e184b12a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789591181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.789591181
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.220114487
Short name T549
Test name
Test status
Simulation time 95023316 ps
CPU time 8.77 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 251280 kb
Host smart-841cab99-347e-4dea-b1a1-246d1be02020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220114487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.220114487
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2435820973
Short name T641
Test name
Test status
Simulation time 131941038 ps
CPU time 7.96 seconds
Started Mar 24 02:36:18 PM PDT 24
Finished Mar 24 02:36:26 PM PDT 24
Peak memory 251448 kb
Host smart-01e366bb-70c5-496f-a772-3f3789293524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435820973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2435820973
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3246198469
Short name T877
Test name
Test status
Simulation time 4373077610 ps
CPU time 163.42 seconds
Started Mar 24 02:36:22 PM PDT 24
Finished Mar 24 02:39:05 PM PDT 24
Peak memory 284320 kb
Host smart-dfb92169-2411-4152-a723-54daa1ec19cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246198469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3246198469
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3483425846
Short name T794
Test name
Test status
Simulation time 16724524501 ps
CPU time 103.78 seconds
Started Mar 24 01:56:21 PM PDT 24
Finished Mar 24 01:58:05 PM PDT 24
Peak memory 251468 kb
Host smart-c2f077bf-e0ec-4d43-9605-62fad95e2d18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483425846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3483425846
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.132682684
Short name T1699
Test name
Test status
Simulation time 81016765 ps
CPU time 0.92 seconds
Started Mar 24 01:56:19 PM PDT 24
Finished Mar 24 01:56:20 PM PDT 24
Peak memory 209260 kb
Host smart-2f655807-507e-48a6-8ebf-cbf816dd2235
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132682684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.132682684
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3737765086
Short name T1645
Test name
Test status
Simulation time 23349722 ps
CPU time 1.33 seconds
Started Mar 24 02:36:16 PM PDT 24
Finished Mar 24 02:36:18 PM PDT 24
Peak memory 213068 kb
Host smart-55cfef23-5302-4eee-bafc-2df81b4ff036
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737765086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3737765086
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4201301321
Short name T1118
Test name
Test status
Simulation time 60993915 ps
CPU time 1.08 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 209980 kb
Host smart-ed6ee3f0-768e-4bc0-9327-3869b2b97e03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201301321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4201301321
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.722926545
Short name T1664
Test name
Test status
Simulation time 19611268 ps
CPU time 1.18 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 209964 kb
Host smart-d37cb484-0b3c-4d79-8336-4e9c115f6acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722926545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.722926545
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1565841212
Short name T478
Test name
Test status
Simulation time 1541645532 ps
CPU time 10.7 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 218568 kb
Host smart-63e8bbe9-e7a2-48b1-82ef-9e8c23267381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565841212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1565841212
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1896972256
Short name T308
Test name
Test status
Simulation time 1579604353 ps
CPU time 11.98 seconds
Started Mar 24 02:36:23 PM PDT 24
Finished Mar 24 02:36:35 PM PDT 24
Peak memory 218588 kb
Host smart-8652eaf4-b779-46e7-97ba-9b7ee6411399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896972256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1896972256
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1205786708
Short name T1301
Test name
Test status
Simulation time 7220038927 ps
CPU time 4.5 seconds
Started Mar 24 01:56:16 PM PDT 24
Finished Mar 24 01:56:21 PM PDT 24
Peak memory 210112 kb
Host smart-35e73d73-9bc0-4caa-bcc4-2aabe7011b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205786708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1205786708
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1360822956
Short name T1090
Test name
Test status
Simulation time 161708346 ps
CPU time 3.34 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:23 PM PDT 24
Peak memory 217368 kb
Host smart-ccd02e48-98fa-4d7e-8ffc-488829615b68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360822956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1360822956
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3486310702
Short name T1693
Test name
Test status
Simulation time 84952909 ps
CPU time 2.67 seconds
Started Mar 24 02:36:23 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 222528 kb
Host smart-7b6c9c8e-a3e2-4036-b649-b7dc5dd655eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486310702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3486310702
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3708211115
Short name T1186
Test name
Test status
Simulation time 68254451 ps
CPU time 3.89 seconds
Started Mar 24 01:56:19 PM PDT 24
Finished Mar 24 01:56:23 PM PDT 24
Peak memory 222268 kb
Host smart-64a01c81-7a7e-41f8-9bc5-e5c27922a244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708211115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3708211115
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2177577836
Short name T1336
Test name
Test status
Simulation time 441401012 ps
CPU time 10.77 seconds
Started Mar 24 02:36:23 PM PDT 24
Finished Mar 24 02:36:33 PM PDT 24
Peak memory 219520 kb
Host smart-9a044f65-7f6a-4f29-86ac-1e74576b2348
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177577836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2177577836
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3752947537
Short name T1553
Test name
Test status
Simulation time 510892288 ps
CPU time 14.51 seconds
Started Mar 24 01:56:21 PM PDT 24
Finished Mar 24 01:56:36 PM PDT 24
Peak memory 218700 kb
Host smart-ec18e731-9d13-42bc-b825-e309093ba400
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752947537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3752947537
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1722446291
Short name T575
Test name
Test status
Simulation time 1102559664 ps
CPU time 18.73 seconds
Started Mar 24 01:56:20 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 218476 kb
Host smart-a5517230-a736-41ad-893a-dd7b4c43861a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722446291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1722446291
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3967693366
Short name T1219
Test name
Test status
Simulation time 195539368 ps
CPU time 9.89 seconds
Started Mar 24 02:36:19 PM PDT 24
Finished Mar 24 02:36:29 PM PDT 24
Peak memory 218548 kb
Host smart-27d293e3-8b05-4296-a3b3-23ae54c56c3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967693366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3967693366
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3824958851
Short name T782
Test name
Test status
Simulation time 3531996098 ps
CPU time 9.96 seconds
Started Mar 24 02:36:21 PM PDT 24
Finished Mar 24 02:36:31 PM PDT 24
Peak memory 218616 kb
Host smart-4ea213b1-41bb-4459-9990-e5e813f386f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824958851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3824958851
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.4105607170
Short name T849
Test name
Test status
Simulation time 1954807136 ps
CPU time 18.37 seconds
Started Mar 24 01:56:20 PM PDT 24
Finished Mar 24 01:56:38 PM PDT 24
Peak memory 218560 kb
Host smart-f5c7b319-763d-4aeb-9e16-b11a78f8eba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105607170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
4105607170
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4076162445
Short name T1599
Test name
Test status
Simulation time 203281334 ps
CPU time 6.4 seconds
Started Mar 24 01:56:18 PM PDT 24
Finished Mar 24 01:56:25 PM PDT 24
Peak memory 225240 kb
Host smart-2a417868-5017-47d3-9f52-011482f0c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076162445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4076162445
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.719280491
Short name T982
Test name
Test status
Simulation time 216177475 ps
CPU time 6.4 seconds
Started Mar 24 02:36:21 PM PDT 24
Finished Mar 24 02:36:28 PM PDT 24
Peak memory 224452 kb
Host smart-37c9903d-fff5-46a3-8e8b-6251d86393dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719280491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.719280491
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.125825244
Short name T1484
Test name
Test status
Simulation time 88020592 ps
CPU time 2.34 seconds
Started Mar 24 01:56:26 PM PDT 24
Finished Mar 24 01:56:28 PM PDT 24
Peak memory 214380 kb
Host smart-b049d01f-0ac7-48fa-b341-0d10de815868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125825244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.125825244
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.4130053887
Short name T1464
Test name
Test status
Simulation time 43901528 ps
CPU time 2.57 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:23 PM PDT 24
Peak memory 214164 kb
Host smart-b232dc85-a6d8-4e31-83f0-4acbe05da3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130053887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.4130053887
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1543792874
Short name T464
Test name
Test status
Simulation time 375565487 ps
CPU time 24.41 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 251692 kb
Host smart-375a895e-b388-48cb-8a1f-0f41f8de40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543792874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1543792874
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2121376869
Short name T387
Test name
Test status
Simulation time 2144381524 ps
CPU time 23.28 seconds
Started Mar 24 01:56:26 PM PDT 24
Finished Mar 24 01:56:49 PM PDT 24
Peak memory 251360 kb
Host smart-b97baf83-6c15-4d1f-b829-f813588c9704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121376869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2121376869
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1782290217
Short name T1014
Test name
Test status
Simulation time 762299369 ps
CPU time 6.52 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:27 PM PDT 24
Peak memory 251376 kb
Host smart-38bd68b7-098c-4815-96e1-813324be18b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782290217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1782290217
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.607772486
Short name T873
Test name
Test status
Simulation time 104893052 ps
CPU time 6.16 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:23 PM PDT 24
Peak memory 246928 kb
Host smart-3daf699a-5ce1-4ecc-a623-b32a92457a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607772486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.607772486
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1617052398
Short name T785
Test name
Test status
Simulation time 5726746860 ps
CPU time 112.39 seconds
Started Mar 24 01:56:16 PM PDT 24
Finished Mar 24 01:58:08 PM PDT 24
Peak memory 269824 kb
Host smart-f575fbe2-fa9e-4bf7-a614-a5c754c2d613
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617052398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1617052398
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2534018507
Short name T1424
Test name
Test status
Simulation time 2968306685 ps
CPU time 66.28 seconds
Started Mar 24 02:36:21 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 229080 kb
Host smart-52de692e-1acc-4eac-aea1-ac8526292159
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534018507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2534018507
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2029412459
Short name T200
Test name
Test status
Simulation time 37610766 ps
CPU time 1 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 212012 kb
Host smart-b82ca3c3-7ba3-4bef-8197-65206827f058
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029412459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2029412459
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.724970261
Short name T1078
Test name
Test status
Simulation time 141707037 ps
CPU time 0.87 seconds
Started Mar 24 01:56:17 PM PDT 24
Finished Mar 24 01:56:18 PM PDT 24
Peak memory 211980 kb
Host smart-212654e5-6fc4-4b29-8105-adaa6f6c01ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724970261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.724970261
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2934929661
Short name T1509
Test name
Test status
Simulation time 18221967 ps
CPU time 0.93 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 209976 kb
Host smart-9f9de323-3a90-4b90-a25c-dec6ff02f035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934929661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2934929661
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4236214470
Short name T317
Test name
Test status
Simulation time 28777468 ps
CPU time 1.06 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:24 PM PDT 24
Peak memory 210252 kb
Host smart-17388cac-225e-40c9-b294-093686681823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236214470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4236214470
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1209292199
Short name T1657
Test name
Test status
Simulation time 1072557432 ps
CPU time 12.58 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:35 PM PDT 24
Peak memory 226636 kb
Host smart-7ca909b2-b997-4c4b-bd6f-107785318537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209292199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1209292199
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1860246632
Short name T405
Test name
Test status
Simulation time 601109686 ps
CPU time 10.26 seconds
Started Mar 24 02:36:22 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 218604 kb
Host smart-e684d3d7-5e4d-4849-a4c2-e239d1754280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860246632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1860246632
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2013594906
Short name T1637
Test name
Test status
Simulation time 311383011 ps
CPU time 2.73 seconds
Started Mar 24 02:36:21 PM PDT 24
Finished Mar 24 02:36:24 PM PDT 24
Peak memory 210012 kb
Host smart-47d5518a-270b-4d8c-9c17-3b08a901a350
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013594906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2013594906
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.900734880
Short name T828
Test name
Test status
Simulation time 2373382570 ps
CPU time 25.82 seconds
Started Mar 24 01:56:24 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 218028 kb
Host smart-a9fbfff0-11a0-45a2-8851-8450b76f15a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900734880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.900734880
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2632482544
Short name T1678
Test name
Test status
Simulation time 43158294 ps
CPU time 2.29 seconds
Started Mar 24 01:56:24 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 222404 kb
Host smart-74c2a432-ca7d-4a39-ab15-f6a20cdd5d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632482544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2632482544
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.698526147
Short name T692
Test name
Test status
Simulation time 50139768 ps
CPU time 1.9 seconds
Started Mar 24 02:36:20 PM PDT 24
Finished Mar 24 02:36:23 PM PDT 24
Peak memory 221788 kb
Host smart-a74f98ab-ef55-4f1e-ae52-d2a4fad5d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698526147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.698526147
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1244050439
Short name T1197
Test name
Test status
Simulation time 887893353 ps
CPU time 11.2 seconds
Started Mar 24 02:36:19 PM PDT 24
Finished Mar 24 02:36:31 PM PDT 24
Peak memory 219428 kb
Host smart-c50608bb-8479-4d2b-b2c3-3ff0270aba17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244050439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1244050439
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.297962682
Short name T1628
Test name
Test status
Simulation time 829467321 ps
CPU time 11.42 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:33 PM PDT 24
Peak memory 219520 kb
Host smart-69223e36-860b-4775-b817-fb737cd29250
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297962682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.297962682
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2194235040
Short name T1287
Test name
Test status
Simulation time 1909755036 ps
CPU time 10.27 seconds
Started Mar 24 01:56:21 PM PDT 24
Finished Mar 24 01:56:31 PM PDT 24
Peak memory 218664 kb
Host smart-b8681c4b-f0fa-4fa3-a754-f9099925304a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194235040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2194235040
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3456216503
Short name T1537
Test name
Test status
Simulation time 266159426 ps
CPU time 8.38 seconds
Started Mar 24 02:36:22 PM PDT 24
Finished Mar 24 02:36:30 PM PDT 24
Peak memory 218588 kb
Host smart-0424c59a-1ffb-4b78-a543-8eb13abb425d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456216503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3456216503
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.367964571
Short name T635
Test name
Test status
Simulation time 7354232223 ps
CPU time 11.38 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:34 PM PDT 24
Peak memory 218644 kb
Host smart-0b78af99-de31-4e10-bf56-f13d475b839a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367964571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.367964571
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.4148514873
Short name T1394
Test name
Test status
Simulation time 15188973416 ps
CPU time 25.52 seconds
Started Mar 24 02:36:19 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 218664 kb
Host smart-d0dee126-be70-4fb5-bcc2-ab030f49b9c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148514873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
4148514873
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1623161842
Short name T1046
Test name
Test status
Simulation time 1348225642 ps
CPU time 10.38 seconds
Started Mar 24 02:36:23 PM PDT 24
Finished Mar 24 02:36:34 PM PDT 24
Peak memory 225352 kb
Host smart-74d6e1e0-e76a-4b0e-b929-744659557dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623161842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1623161842
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4021005544
Short name T273
Test name
Test status
Simulation time 274666407 ps
CPU time 10.76 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:32 PM PDT 24
Peak memory 226672 kb
Host smart-5845196c-c95a-4a94-a76e-4b7ffa8f71b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021005544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4021005544
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1575193389
Short name T749
Test name
Test status
Simulation time 36203013 ps
CPU time 2.65 seconds
Started Mar 24 02:36:22 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 214796 kb
Host smart-82ec438f-629c-4704-b016-5b6a5a8e3cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575193389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1575193389
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.201294432
Short name T83
Test name
Test status
Simulation time 33802107 ps
CPU time 2.29 seconds
Started Mar 24 01:56:19 PM PDT 24
Finished Mar 24 01:56:21 PM PDT 24
Peak memory 214428 kb
Host smart-d49d9fe9-beeb-4a85-97db-bf8466712028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201294432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.201294432
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3593395082
Short name T1224
Test name
Test status
Simulation time 525369088 ps
CPU time 31.77 seconds
Started Mar 24 02:36:22 PM PDT 24
Finished Mar 24 02:36:54 PM PDT 24
Peak memory 251512 kb
Host smart-2435f260-bb86-400f-8869-b77dbe20149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593395082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3593395082
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3721808859
Short name T759
Test name
Test status
Simulation time 505158350 ps
CPU time 30.11 seconds
Started Mar 24 01:56:19 PM PDT 24
Finished Mar 24 01:56:49 PM PDT 24
Peak memory 251384 kb
Host smart-408ada3c-305a-42e0-8e16-e4a2cf3e1707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721808859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3721808859
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.612251274
Short name T370
Test name
Test status
Simulation time 106664235 ps
CPU time 9.33 seconds
Started Mar 24 02:36:21 PM PDT 24
Finished Mar 24 02:36:30 PM PDT 24
Peak memory 251496 kb
Host smart-8cbd0ff4-e5b5-4694-84a6-650ecf60155a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612251274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.612251274
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.779667016
Short name T216
Test name
Test status
Simulation time 83386678 ps
CPU time 2.97 seconds
Started Mar 24 01:56:21 PM PDT 24
Finished Mar 24 01:56:25 PM PDT 24
Peak memory 222444 kb
Host smart-5d5be033-1d5c-47e4-8d21-006b23d94e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779667016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.779667016
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2033186169
Short name T96
Test name
Test status
Simulation time 793279878 ps
CPU time 50.64 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:37:15 PM PDT 24
Peak memory 251460 kb
Host smart-56d1e61f-b79b-4681-8307-f89534e6f5d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033186169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2033186169
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.711027218
Short name T48
Test name
Test status
Simulation time 3019936090 ps
CPU time 57.96 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:57:20 PM PDT 24
Peak memory 251668 kb
Host smart-995574e6-7acb-4a9d-a511-2171640c8c22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711027218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.711027218
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.403275772
Short name T193
Test name
Test status
Simulation time 46055860455 ps
CPU time 300.51 seconds
Started Mar 24 01:56:23 PM PDT 24
Finished Mar 24 02:01:24 PM PDT 24
Peak memory 284428 kb
Host smart-eaf27471-1341-433c-8785-b9e8887258ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=403275772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.403275772
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2294230615
Short name T1618
Test name
Test status
Simulation time 20353435 ps
CPU time 0.96 seconds
Started Mar 24 01:56:19 PM PDT 24
Finished Mar 24 01:56:20 PM PDT 24
Peak memory 209052 kb
Host smart-8e2fe921-f1d1-4f84-bd44-35cc6b9c06ff
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294230615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2294230615
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2477926585
Short name T479
Test name
Test status
Simulation time 13782937 ps
CPU time 0.97 seconds
Started Mar 24 02:36:22 PM PDT 24
Finished Mar 24 02:36:24 PM PDT 24
Peak memory 209096 kb
Host smart-8e156170-4851-4ac0-a60e-d3caaed27199
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477926585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2477926585
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1366185854
Short name T834
Test name
Test status
Simulation time 17579184 ps
CPU time 1.15 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:56:31 PM PDT 24
Peak memory 209956 kb
Host smart-c6ef4345-d27c-4a83-b51b-b3b28abb0ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366185854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1366185854
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.4042167777
Short name T1655
Test name
Test status
Simulation time 17627320 ps
CPU time 0.87 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:36:25 PM PDT 24
Peak memory 209968 kb
Host smart-4c097a16-eae6-4700-bf20-2d6fafa54b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042167777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4042167777
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2699162422
Short name T1209
Test name
Test status
Simulation time 402894610 ps
CPU time 10.22 seconds
Started Mar 24 01:56:24 PM PDT 24
Finished Mar 24 01:56:34 PM PDT 24
Peak memory 218520 kb
Host smart-348dafd0-4600-4f95-bfb9-41c7aae48623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699162422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2699162422
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3050530249
Short name T281
Test name
Test status
Simulation time 1679356693 ps
CPU time 17.4 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 218500 kb
Host smart-cbe4aa38-75ff-4b3b-9f62-e3c990820c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050530249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3050530249
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1528623781
Short name T1418
Test name
Test status
Simulation time 272931395 ps
CPU time 1.69 seconds
Started Mar 24 01:56:24 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 210020 kb
Host smart-f8cd3ffb-cbb1-40d4-9683-a63b0b96e5f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528623781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1528623781
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3261250033
Short name T1092
Test name
Test status
Simulation time 577519090 ps
CPU time 6.15 seconds
Started Mar 24 02:36:29 PM PDT 24
Finished Mar 24 02:36:36 PM PDT 24
Peak memory 210020 kb
Host smart-1d97fcc5-4300-4efc-9d5f-e96f8300a96f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261250033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3261250033
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1007017955
Short name T1299
Test name
Test status
Simulation time 96820419 ps
CPU time 3.48 seconds
Started Mar 24 01:56:23 PM PDT 24
Finished Mar 24 01:56:27 PM PDT 24
Peak memory 218636 kb
Host smart-7362d8cf-7ee1-44de-9d76-1c9549682458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007017955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1007017955
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1557025620
Short name T1221
Test name
Test status
Simulation time 123510751 ps
CPU time 3.7 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:36:28 PM PDT 24
Peak memory 218496 kb
Host smart-cc85383e-999a-4566-97c7-cfe68d2f0f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557025620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1557025620
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1981826480
Short name T615
Test name
Test status
Simulation time 1071963701 ps
CPU time 13.54 seconds
Started Mar 24 01:56:25 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 219788 kb
Host smart-cefadf56-c2de-4a17-9295-d8a7c2f8ac48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981826480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1981826480
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.234000756
Short name T1574
Test name
Test status
Simulation time 748360787 ps
CPU time 19.34 seconds
Started Mar 24 02:36:25 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 219576 kb
Host smart-3cad779c-6c25-431a-aa5a-579bcc90782f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234000756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.234000756
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1740625289
Short name T916
Test name
Test status
Simulation time 788576100 ps
CPU time 14.19 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:36:38 PM PDT 24
Peak memory 218636 kb
Host smart-980e258b-5783-4492-9f45-58e2448886cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740625289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1740625289
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3191162122
Short name T380
Test name
Test status
Simulation time 2161822419 ps
CPU time 14.16 seconds
Started Mar 24 01:56:21 PM PDT 24
Finished Mar 24 01:56:35 PM PDT 24
Peak memory 218640 kb
Host smart-218aa66d-7306-4e37-8ed1-d31986e26147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191162122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3191162122
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2026368971
Short name T1480
Test name
Test status
Simulation time 507234101 ps
CPU time 8.05 seconds
Started Mar 24 01:56:24 PM PDT 24
Finished Mar 24 01:56:32 PM PDT 24
Peak memory 218648 kb
Host smart-7fea0913-b874-4d61-96fa-6d52976c4ce8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026368971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2026368971
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2113151642
Short name T649
Test name
Test status
Simulation time 328043428 ps
CPU time 8.81 seconds
Started Mar 24 02:36:25 PM PDT 24
Finished Mar 24 02:36:33 PM PDT 24
Peak memory 218536 kb
Host smart-b9afb25c-1a19-41f2-9c94-56c86cdfdeeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113151642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2113151642
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1677126936
Short name T1634
Test name
Test status
Simulation time 516468590 ps
CPU time 10.63 seconds
Started Mar 24 02:36:23 PM PDT 24
Finished Mar 24 02:36:34 PM PDT 24
Peak memory 225452 kb
Host smart-2c4d1c49-d024-420c-baa0-12ef48afb202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677126936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1677126936
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3888376361
Short name T1330
Test name
Test status
Simulation time 798493614 ps
CPU time 9.85 seconds
Started Mar 24 01:56:23 PM PDT 24
Finished Mar 24 01:56:33 PM PDT 24
Peak memory 226664 kb
Host smart-bbe7ef94-2bd9-4681-a3be-350517837de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888376361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3888376361
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2992022491
Short name T1636
Test name
Test status
Simulation time 38503317 ps
CPU time 2.57 seconds
Started Mar 24 02:36:25 PM PDT 24
Finished Mar 24 02:36:28 PM PDT 24
Peak memory 214964 kb
Host smart-aee8f7e5-5a48-4bd0-b669-ce94471c65d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992022491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2992022491
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4291144288
Short name T8
Test name
Test status
Simulation time 73622880 ps
CPU time 2.86 seconds
Started Mar 24 01:56:23 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 218280 kb
Host smart-4d82d74f-baee-4d3d-955d-583c14804fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291144288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4291144288
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.1651307712
Short name T313
Test name
Test status
Simulation time 1309975147 ps
CPU time 16.82 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 251492 kb
Host smart-23e51ff4-3705-4ed6-83fe-b1af94bb1d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651307712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1651307712
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.269350757
Short name T292
Test name
Test status
Simulation time 709640238 ps
CPU time 41.98 seconds
Started Mar 24 02:36:27 PM PDT 24
Finished Mar 24 02:37:09 PM PDT 24
Peak memory 246796 kb
Host smart-af98c7df-f252-4b73-b3f5-56c3cf740323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269350757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.269350757
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3912356977
Short name T923
Test name
Test status
Simulation time 173373442 ps
CPU time 11.83 seconds
Started Mar 24 02:36:24 PM PDT 24
Finished Mar 24 02:36:36 PM PDT 24
Peak memory 251576 kb
Host smart-c23e2a82-9aac-4b63-9f1f-45f348c71813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912356977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3912356977
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4183169669
Short name T390
Test name
Test status
Simulation time 64466141 ps
CPU time 7.26 seconds
Started Mar 24 01:56:24 PM PDT 24
Finished Mar 24 01:56:32 PM PDT 24
Peak memory 251052 kb
Host smart-f5a5da47-3225-4bbd-aed9-d8db517018f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183169669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4183169669
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.236414105
Short name T1437
Test name
Test status
Simulation time 13738987881 ps
CPU time 183.64 seconds
Started Mar 24 02:36:27 PM PDT 24
Finished Mar 24 02:39:31 PM PDT 24
Peak memory 278824 kb
Host smart-a3841a64-042a-4843-88a9-b4a5488e79d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236414105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.236414105
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.4094772657
Short name T1240
Test name
Test status
Simulation time 4091745547 ps
CPU time 72.39 seconds
Started Mar 24 01:56:28 PM PDT 24
Finished Mar 24 01:57:41 PM PDT 24
Peak memory 251580 kb
Host smart-b3c6b05c-c6cd-4c7a-b09d-ea887596a8ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094772657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.4094772657
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.459093457
Short name T213
Test name
Test status
Simulation time 754219062632 ps
CPU time 801.05 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 02:09:49 PM PDT 24
Peak memory 333576 kb
Host smart-a3f42474-be05-4627-83ab-06d88bf2b63a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=459093457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.459093457
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3109697988
Short name T787
Test name
Test status
Simulation time 13641100 ps
CPU time 0.78 seconds
Started Mar 24 02:36:23 PM PDT 24
Finished Mar 24 02:36:24 PM PDT 24
Peak memory 209188 kb
Host smart-2c0b6246-2365-4463-b0f8-4231190dbfa6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109697988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3109697988
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3356786796
Short name T941
Test name
Test status
Simulation time 136558019 ps
CPU time 1.09 seconds
Started Mar 24 01:56:22 PM PDT 24
Finished Mar 24 01:56:23 PM PDT 24
Peak memory 213256 kb
Host smart-42445e80-4f72-4049-8a18-595b9f0aba3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356786796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3356786796
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2017430472
Short name T1030
Test name
Test status
Simulation time 49945420 ps
CPU time 0.91 seconds
Started Mar 24 01:56:28 PM PDT 24
Finished Mar 24 01:56:30 PM PDT 24
Peak memory 209968 kb
Host smart-9ad3caec-95dc-4c10-9048-fa20217a091b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017430472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2017430472
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2706579670
Short name T842
Test name
Test status
Simulation time 23322357 ps
CPU time 0.98 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 209984 kb
Host smart-cea3a675-587e-43c9-a1a9-9d8f009c62e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706579670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2706579670
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1898537576
Short name T727
Test name
Test status
Simulation time 1328463731 ps
CPU time 11.87 seconds
Started Mar 24 02:36:33 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 226584 kb
Host smart-efe61810-b7a5-4771-aba4-68a3289c0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898537576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1898537576
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3121191645
Short name T691
Test name
Test status
Simulation time 373706165 ps
CPU time 9.77 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 226636 kb
Host smart-f2ec344f-6d8a-4ce8-a05e-a51e314056f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121191645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3121191645
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1222701386
Short name T593
Test name
Test status
Simulation time 1779285011 ps
CPU time 3.62 seconds
Started Mar 24 02:36:33 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 209940 kb
Host smart-6b189e0e-74da-4508-afa2-7c723f937841
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222701386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1222701386
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1061767821
Short name T325
Test name
Test status
Simulation time 176348029 ps
CPU time 2.63 seconds
Started Mar 24 02:36:27 PM PDT 24
Finished Mar 24 02:36:30 PM PDT 24
Peak memory 218632 kb
Host smart-2836c62e-45f4-45e6-b886-a603dd3c2cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061767821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1061767821
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2745341723
Short name T1431
Test name
Test status
Simulation time 266606796 ps
CPU time 3.57 seconds
Started Mar 24 01:56:30 PM PDT 24
Finished Mar 24 01:56:33 PM PDT 24
Peak memory 222368 kb
Host smart-13c688b1-8a8d-444d-93f6-f4263bf7e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745341723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2745341723
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.130912219
Short name T1125
Test name
Test status
Simulation time 1094200563 ps
CPU time 11.41 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 219480 kb
Host smart-98f7f2c1-6984-4336-aab9-a1c77d088202
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130912219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.130912219
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.68439805
Short name T1388
Test name
Test status
Simulation time 518228740 ps
CPU time 9.37 seconds
Started Mar 24 02:36:38 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 219724 kb
Host smart-5e02b6e2-53a1-47ea-b568-aa813ec7398c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68439805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.68439805
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1705753455
Short name T1282
Test name
Test status
Simulation time 1499100258 ps
CPU time 9.53 seconds
Started Mar 24 02:36:30 PM PDT 24
Finished Mar 24 02:36:40 PM PDT 24
Peak memory 218536 kb
Host smart-246505b6-5d96-48c1-a06d-6bb94bbabc85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705753455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1705753455
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.814442272
Short name T1119
Test name
Test status
Simulation time 907952961 ps
CPU time 7.34 seconds
Started Mar 24 01:56:28 PM PDT 24
Finished Mar 24 01:56:35 PM PDT 24
Peak memory 218560 kb
Host smart-322bc54f-f718-4049-b92e-5958ebed44c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814442272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.814442272
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1777202268
Short name T769
Test name
Test status
Simulation time 257670841 ps
CPU time 7.54 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:56:37 PM PDT 24
Peak memory 218624 kb
Host smart-94b62a7c-d8fd-4b62-94b4-639ceac1003d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777202268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1777202268
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3155262885
Short name T647
Test name
Test status
Simulation time 279330999 ps
CPU time 7.11 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:42 PM PDT 24
Peak memory 218468 kb
Host smart-a34088ff-9832-4b21-9051-d6406ab19522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155262885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3155262885
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1939377549
Short name T729
Test name
Test status
Simulation time 2970942973 ps
CPU time 8.42 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:40 PM PDT 24
Peak memory 225600 kb
Host smart-165d49f3-9a43-4486-a0a8-7d6d08562b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939377549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1939377549
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2923564960
Short name T1200
Test name
Test status
Simulation time 2730845278 ps
CPU time 15.3 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 01:56:42 PM PDT 24
Peak memory 226732 kb
Host smart-b1df9c89-48cc-49a6-88fa-04714f0c78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923564960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2923564960
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1464775423
Short name T1321
Test name
Test status
Simulation time 54418866 ps
CPU time 2.24 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 214288 kb
Host smart-388ccdfb-68d2-4914-a1e8-fa6c07511755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464775423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1464775423
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1685331903
Short name T581
Test name
Test status
Simulation time 62012844 ps
CPU time 2.19 seconds
Started Mar 24 02:36:32 PM PDT 24
Finished Mar 24 02:36:35 PM PDT 24
Peak memory 218168 kb
Host smart-0eb0ef8c-ef68-47fc-b180-900767d0b32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685331903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1685331903
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3769385907
Short name T310
Test name
Test status
Simulation time 634746694 ps
CPU time 19.75 seconds
Started Mar 24 02:36:25 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 246808 kb
Host smart-72f83d26-a61b-4ef8-9451-17954102ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769385907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3769385907
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.3833872589
Short name T1109
Test name
Test status
Simulation time 200979215 ps
CPU time 21.21 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 01:56:48 PM PDT 24
Peak memory 251536 kb
Host smart-cca4db40-a810-4f6c-90ad-946c8118e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833872589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.3833872589
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1292228958
Short name T219
Test name
Test status
Simulation time 407988331 ps
CPU time 7.6 seconds
Started Mar 24 01:56:28 PM PDT 24
Finished Mar 24 01:56:36 PM PDT 24
Peak memory 251464 kb
Host smart-78e5da87-167b-4cb3-9397-291a5f7a8b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292228958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1292228958
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1347613289
Short name T1564
Test name
Test status
Simulation time 73608651 ps
CPU time 6.49 seconds
Started Mar 24 02:36:30 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 250672 kb
Host smart-11ce91e0-e286-4220-ba45-b8743687492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347613289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1347613289
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1114480529
Short name T62
Test name
Test status
Simulation time 10495831035 ps
CPU time 219.51 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 278024 kb
Host smart-07c25b4b-95e8-4dd9-8f7c-2da689441fd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114480529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1114480529
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3055217267
Short name T710
Test name
Test status
Simulation time 9377601484 ps
CPU time 42.25 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:57:11 PM PDT 24
Peak memory 251556 kb
Host smart-98eb38c7-9ef5-4b07-9281-da9662fc917f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055217267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3055217267
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3302515662
Short name T523
Test name
Test status
Simulation time 18186482 ps
CPU time 1.02 seconds
Started Mar 24 02:36:25 PM PDT 24
Finished Mar 24 02:36:26 PM PDT 24
Peak memory 212120 kb
Host smart-9cbedf3a-9ebe-4c2d-b6f6-6622a445fa58
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302515662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3302515662
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3635842281
Short name T372
Test name
Test status
Simulation time 15429290 ps
CPU time 0.88 seconds
Started Mar 24 01:56:28 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 208980 kb
Host smart-67793da0-623e-483f-9c52-be4cb1680637
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635842281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3635842281
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1418993407
Short name T905
Test name
Test status
Simulation time 42769795 ps
CPU time 0.95 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 209948 kb
Host smart-cdb11582-4adc-4f9f-bebb-7393d13a4109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418993407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1418993407
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2499982174
Short name T1434
Test name
Test status
Simulation time 13180243 ps
CPU time 0.96 seconds
Started Mar 24 02:34:55 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 210240 kb
Host smart-d17b6fee-2099-4d92-ae1f-a446382a1c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499982174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2499982174
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3034212176
Short name T432
Test name
Test status
Simulation time 33814945 ps
CPU time 0.78 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:47 PM PDT 24
Peak memory 209868 kb
Host smart-ebadeb98-cca7-414b-8a01-0ca1b3f5710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034212176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3034212176
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1418332809
Short name T398
Test name
Test status
Simulation time 1284623159 ps
CPU time 10.37 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 218592 kb
Host smart-178c7e88-e9a0-4ccf-b67d-af9129d64701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418332809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1418332809
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.2051494122
Short name T1676
Test name
Test status
Simulation time 1062045171 ps
CPU time 14.11 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 218460 kb
Host smart-58ac279c-8a3d-4621-aba4-6a36345dcb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051494122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2051494122
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2834101710
Short name T948
Test name
Test status
Simulation time 127296415 ps
CPU time 2.56 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:49 PM PDT 24
Peak memory 210028 kb
Host smart-1397a99d-1d62-4ffc-aaee-f60fc47a5838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834101710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2834101710
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4151286666
Short name T471
Test name
Test status
Simulation time 71972646 ps
CPU time 1.67 seconds
Started Mar 24 02:34:54 PM PDT 24
Finished Mar 24 02:34:55 PM PDT 24
Peak memory 210052 kb
Host smart-9da86bbd-9e54-416f-a068-bd8f99a6ac04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151286666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4151286666
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1001192679
Short name T1172
Test name
Test status
Simulation time 2083122841 ps
CPU time 52.89 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:55:41 PM PDT 24
Peak memory 218576 kb
Host smart-0a5ac0b1-35a1-460f-bc5c-d449ca9dbdbd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001192679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1001192679
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3921888356
Short name T537
Test name
Test status
Simulation time 2027036869 ps
CPU time 57.09 seconds
Started Mar 24 02:34:53 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 218508 kb
Host smart-4ffb6629-b8f1-45a8-b393-55da1354d667
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921888356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3921888356
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1281919392
Short name T1208
Test name
Test status
Simulation time 763329130 ps
CPU time 9.86 seconds
Started Mar 24 02:34:54 PM PDT 24
Finished Mar 24 02:35:04 PM PDT 24
Peak memory 217928 kb
Host smart-8cae536c-4ecb-41e7-a698-7851fc93ec16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281919392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
281919392
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3889684073
Short name T1416
Test name
Test status
Simulation time 285795736 ps
CPU time 3.87 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:50 PM PDT 24
Peak memory 217812 kb
Host smart-8f0c3eeb-b1e6-4f41-b09b-68933be5ff1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889684073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
889684073
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2448379774
Short name T1271
Test name
Test status
Simulation time 762621117 ps
CPU time 4 seconds
Started Mar 24 02:34:53 PM PDT 24
Finished Mar 24 02:34:58 PM PDT 24
Peak memory 218448 kb
Host smart-9bd71746-fcf0-4b00-b1e0-afb8136be995
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448379774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2448379774
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4017061688
Short name T1246
Test name
Test status
Simulation time 317921912 ps
CPU time 9.97 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 218532 kb
Host smart-b7618f6b-dfcd-4a96-b322-e069457d534b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017061688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4017061688
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3001510707
Short name T78
Test name
Test status
Simulation time 1169715794 ps
CPU time 17.23 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:35:10 PM PDT 24
Peak memory 213524 kb
Host smart-cc6d0837-de41-4436-89e9-f83e6672f681
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001510707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3001510707
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3538680138
Short name T863
Test name
Test status
Simulation time 12999266170 ps
CPU time 19.82 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:55:06 PM PDT 24
Peak memory 214296 kb
Host smart-628e04a2-b4c6-4ee0-9685-1b3dcf80d75e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538680138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3538680138
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.2926966109
Short name T921
Test name
Test status
Simulation time 447823836 ps
CPU time 7.92 seconds
Started Mar 24 01:54:45 PM PDT 24
Finished Mar 24 01:54:53 PM PDT 24
Peak memory 214424 kb
Host smart-c5683d12-e9ba-46b8-a538-f4cb4e828e18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926966109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
2926966109
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3051623056
Short name T1181
Test name
Test status
Simulation time 60046272 ps
CPU time 1.49 seconds
Started Mar 24 02:34:54 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 213156 kb
Host smart-1f5d848c-7bfc-428c-aaf9-c23e7d86fb01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051623056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3051623056
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3123637113
Short name T1666
Test name
Test status
Simulation time 4662888023 ps
CPU time 52.17 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 251492 kb
Host smart-2d94c538-5e0f-4d2f-9156-94988b743a9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123637113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3123637113
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3557484147
Short name T104
Test name
Test status
Simulation time 1685046349 ps
CPU time 47.64 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 248400 kb
Host smart-eee42483-8850-4324-a305-d1304b03af72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557484147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3557484147
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4072623131
Short name T1039
Test name
Test status
Simulation time 825292796 ps
CPU time 11.59 seconds
Started Mar 24 02:34:55 PM PDT 24
Finished Mar 24 02:35:07 PM PDT 24
Peak memory 250964 kb
Host smart-a0b75fb5-14ef-492a-8299-f4076aedc74d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072623131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4072623131
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4115362699
Short name T1573
Test name
Test status
Simulation time 1012695003 ps
CPU time 16.24 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 226876 kb
Host smart-adeccc0f-0d14-4dfa-ada8-ec3d30e05a26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115362699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4115362699
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1258866318
Short name T346
Test name
Test status
Simulation time 54044476 ps
CPU time 1.55 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 218656 kb
Host smart-3fecaadb-91ae-48ed-907b-b937b17ffb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258866318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1258866318
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.4067860651
Short name T463
Test name
Test status
Simulation time 292432327 ps
CPU time 3.63 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 218644 kb
Host smart-f5fe636c-dd03-4f92-a3b2-b8537aed25a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067860651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.4067860651
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.181096794
Short name T1503
Test name
Test status
Simulation time 1289097967 ps
CPU time 11.58 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 218408 kb
Host smart-e66b1a61-9c2e-4d7c-90c3-fa7268919c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181096794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.181096794
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2929197648
Short name T701
Test name
Test status
Simulation time 234091086 ps
CPU time 6.15 seconds
Started Mar 24 02:34:55 PM PDT 24
Finished Mar 24 02:35:01 PM PDT 24
Peak memory 214668 kb
Host smart-af0ac847-4cb9-4748-bee0-b5e526d01283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929197648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2929197648
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2354057860
Short name T116
Test name
Test status
Simulation time 124028275 ps
CPU time 24.17 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:55:13 PM PDT 24
Peak memory 282312 kb
Host smart-1cab952b-4c04-4622-9c2f-814c4c44aeb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354057860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2354057860
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3965370333
Short name T92
Test name
Test status
Simulation time 424379190 ps
CPU time 35.74 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 268840 kb
Host smart-709847c1-8201-4232-b19e-66b50cf92f56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965370333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3965370333
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1605128012
Short name T1010
Test name
Test status
Simulation time 1280249534 ps
CPU time 12.82 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:59 PM PDT 24
Peak memory 219420 kb
Host smart-6d090e00-ca7f-4855-a6f5-0dae63725986
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605128012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1605128012
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2476533452
Short name T11
Test name
Test status
Simulation time 414329818 ps
CPU time 14.4 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 218868 kb
Host smart-a3ec55ac-0b4e-4761-a11f-7f2fbd249f91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476533452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2476533452
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2794930841
Short name T1262
Test name
Test status
Simulation time 356482126 ps
CPU time 8.7 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:54:57 PM PDT 24
Peak memory 218528 kb
Host smart-4cf0fade-c955-46bb-be9a-fd86d3ce5c5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794930841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2794930841
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.4253876138
Short name T600
Test name
Test status
Simulation time 366780609 ps
CPU time 12.79 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 218504 kb
Host smart-b96eaf38-e9f3-4d6b-938a-5b7f62fe795b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253876138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.4253876138
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1381346492
Short name T1148
Test name
Test status
Simulation time 212901106 ps
CPU time 5.67 seconds
Started Mar 24 02:34:56 PM PDT 24
Finished Mar 24 02:35:02 PM PDT 24
Peak memory 218572 kb
Host smart-9fd57b51-fe99-4220-bdef-ba77da6c9fdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381346492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
381346492
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3211279957
Short name T831
Test name
Test status
Simulation time 284747758 ps
CPU time 7.78 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 218652 kb
Host smart-2a247066-ff6b-4a3a-a4ee-51aa12cc437f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211279957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
211279957
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.1618919865
Short name T218
Test name
Test status
Simulation time 1286011053 ps
CPU time 7.99 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:54 PM PDT 24
Peak memory 225008 kb
Host smart-5dd1d12d-c3d8-4900-b52f-7af14feebb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618919865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1618919865
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3924927905
Short name T379
Test name
Test status
Simulation time 1729923477 ps
CPU time 10.67 seconds
Started Mar 24 02:34:54 PM PDT 24
Finished Mar 24 02:35:05 PM PDT 24
Peak memory 225156 kb
Host smart-dbd23323-9543-40cb-ba7f-578a2f163275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924927905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3924927905
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3415625851
Short name T1099
Test name
Test status
Simulation time 121812662 ps
CPU time 2.22 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 218264 kb
Host smart-0dbdc1b8-9981-4cce-b6b5-27f0b2fb1659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415625851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3415625851
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3996421441
Short name T1600
Test name
Test status
Simulation time 148635744 ps
CPU time 2.64 seconds
Started Mar 24 01:54:48 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 214672 kb
Host smart-547b5bc7-531b-4084-86a5-a316692175f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996421441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3996421441
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3365867707
Short name T321
Test name
Test status
Simulation time 2486078047 ps
CPU time 21.47 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 251564 kb
Host smart-6ba1b366-5b9a-4cf9-b7e2-c8099ffd3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365867707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3365867707
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.867949910
Short name T1036
Test name
Test status
Simulation time 199491282 ps
CPU time 15.27 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:35:08 PM PDT 24
Peak memory 251536 kb
Host smart-eba99128-740e-4629-bf34-bcf871a79cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867949910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.867949910
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3902420298
Short name T1513
Test name
Test status
Simulation time 539657557 ps
CPU time 7.65 seconds
Started Mar 24 02:34:50 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 251472 kb
Host smart-e7b80048-419b-46ad-8fbf-005992b93c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902420298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3902420298
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.572974202
Short name T715
Test name
Test status
Simulation time 79654218 ps
CPU time 6.54 seconds
Started Mar 24 01:54:45 PM PDT 24
Finished Mar 24 01:54:52 PM PDT 24
Peak memory 246640 kb
Host smart-27c29b43-ea5c-4e43-a71e-b40a5810eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572974202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.572974202
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.380174264
Short name T1122
Test name
Test status
Simulation time 17803317019 ps
CPU time 172.95 seconds
Started Mar 24 02:34:53 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 314540 kb
Host smart-69d66e7a-7060-4dea-a0a2-5d81e37ebf9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380174264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.380174264
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.922369177
Short name T957
Test name
Test status
Simulation time 17655349511 ps
CPU time 57.02 seconds
Started Mar 24 01:54:47 PM PDT 24
Finished Mar 24 01:55:44 PM PDT 24
Peak memory 251292 kb
Host smart-8aa3bd7f-1e07-4e5c-9ebd-3656c6d79595
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922369177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.922369177
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1378434380
Short name T61
Test name
Test status
Simulation time 17492109453 ps
CPU time 521.56 seconds
Started Mar 24 01:54:47 PM PDT 24
Finished Mar 24 02:03:29 PM PDT 24
Peak memory 281720 kb
Host smart-064dbd18-d40a-497b-a337-cae8caf2e444
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1378434380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1378434380
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1284962218
Short name T337
Test name
Test status
Simulation time 135940878 ps
CPU time 0.77 seconds
Started Mar 24 01:54:46 PM PDT 24
Finished Mar 24 01:54:47 PM PDT 24
Peak memory 209088 kb
Host smart-67d89e3c-038a-4744-b877-7c0babf9e614
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284962218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1284962218
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3631510972
Short name T364
Test name
Test status
Simulation time 33636049 ps
CPU time 0.92 seconds
Started Mar 24 02:34:49 PM PDT 24
Finished Mar 24 02:34:54 PM PDT 24
Peak memory 212152 kb
Host smart-29944f76-7fa6-4fb1-868c-8f2ff5b78ea4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631510972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3631510972
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2501225994
Short name T909
Test name
Test status
Simulation time 19283881 ps
CPU time 0.92 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 209972 kb
Host smart-54f35f34-67ac-4d49-802a-c92994c97f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501225994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2501225994
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2593287940
Short name T1399
Test name
Test status
Simulation time 60713087 ps
CPU time 0.86 seconds
Started Mar 24 01:56:34 PM PDT 24
Finished Mar 24 01:56:35 PM PDT 24
Peak memory 209984 kb
Host smart-cb547933-431f-45d1-b5fd-1677538dbe94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593287940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2593287940
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.319918197
Short name T565
Test name
Test status
Simulation time 247954428 ps
CPU time 12.3 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 218540 kb
Host smart-eac6f7bf-c37d-4db5-9579-4bb6b964a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319918197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.319918197
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1884584418
Short name T1684
Test name
Test status
Simulation time 2070354262 ps
CPU time 11.82 seconds
Started Mar 24 02:36:35 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 210016 kb
Host smart-ba54c942-edfd-4e4c-8c36-f22e7cc94a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884584418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1884584418
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.406837115
Short name T875
Test name
Test status
Simulation time 283034127 ps
CPU time 2.35 seconds
Started Mar 24 01:56:34 PM PDT 24
Finished Mar 24 01:56:36 PM PDT 24
Peak memory 217364 kb
Host smart-1d12b9a7-7fc8-4001-aa0b-4f2fe858ffa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406837115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.406837115
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2098240991
Short name T817
Test name
Test status
Simulation time 354574804 ps
CPU time 2.86 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:35 PM PDT 24
Peak memory 222396 kb
Host smart-faff75a3-2c1b-4ac9-930b-0dabbfee6603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098240991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2098240991
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.773596552
Short name T455
Test name
Test status
Simulation time 332985917 ps
CPU time 3.95 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 01:56:31 PM PDT 24
Peak memory 218624 kb
Host smart-c0721a38-7fbd-4603-8d0d-d60d83f521cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773596552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.773596552
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3025364297
Short name T958
Test name
Test status
Simulation time 304466964 ps
CPU time 13.73 seconds
Started Mar 24 01:56:38 PM PDT 24
Finished Mar 24 01:56:51 PM PDT 24
Peak memory 226684 kb
Host smart-0d314140-b05a-4bd4-a178-2428fc4604b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025364297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3025364297
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.4240211797
Short name T672
Test name
Test status
Simulation time 519450179 ps
CPU time 14.47 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 219496 kb
Host smart-1612b054-a1fe-49a7-9f3e-e25fc23d7750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240211797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.4240211797
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4084755250
Short name T1485
Test name
Test status
Simulation time 175060576 ps
CPU time 8.43 seconds
Started Mar 24 02:36:32 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 218592 kb
Host smart-6ada11f1-c583-42cc-9647-576a05045a35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084755250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4084755250
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.998877850
Short name T680
Test name
Test status
Simulation time 364533024 ps
CPU time 10.48 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:56:56 PM PDT 24
Peak memory 218444 kb
Host smart-3aafd9a7-15cd-4782-99b1-2aa7fa1ecbb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998877850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_di
gest.998877850
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2644325150
Short name T750
Test name
Test status
Simulation time 466707451 ps
CPU time 9.02 seconds
Started Mar 24 02:36:30 PM PDT 24
Finished Mar 24 02:36:39 PM PDT 24
Peak memory 218548 kb
Host smart-f67707c6-b31a-4f90-89a9-8a12e75d0ad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644325150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2644325150
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2756800948
Short name T667
Test name
Test status
Simulation time 1242271752 ps
CPU time 6.46 seconds
Started Mar 24 01:56:35 PM PDT 24
Finished Mar 24 01:56:42 PM PDT 24
Peak memory 218504 kb
Host smart-56c9c0ef-ea26-47cb-9c4b-4209ceb38c5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756800948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2756800948
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2427950051
Short name T670
Test name
Test status
Simulation time 255862359 ps
CPU time 11.21 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 225960 kb
Host smart-433d60e1-1bce-4370-9b3b-ccfb8e2efd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427950051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2427950051
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.443903735
Short name T696
Test name
Test status
Simulation time 298335777 ps
CPU time 8.18 seconds
Started Mar 24 01:56:33 PM PDT 24
Finished Mar 24 01:56:41 PM PDT 24
Peak memory 225004 kb
Host smart-edf237f5-3cc0-420a-9769-f9d4e8e4bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443903735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.443903735
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2192352467
Short name T687
Test name
Test status
Simulation time 78383588 ps
CPU time 1.8 seconds
Started Mar 24 02:36:30 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 214336 kb
Host smart-dfcf352c-9f4c-4779-8457-46ecca5df490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192352467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2192352467
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2682848692
Short name T45
Test name
Test status
Simulation time 65095437 ps
CPU time 3.94 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:56:33 PM PDT 24
Peak memory 218212 kb
Host smart-9496436c-9390-4f92-8acb-4569f6a13e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682848692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2682848692
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.298098949
Short name T892
Test name
Test status
Simulation time 2044316014 ps
CPU time 21.96 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:53 PM PDT 24
Peak memory 251468 kb
Host smart-b6781492-fcb5-4c79-94ce-5c8d42ea3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298098949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.298098949
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.808805491
Short name T812
Test name
Test status
Simulation time 413017285 ps
CPU time 27.73 seconds
Started Mar 24 01:56:31 PM PDT 24
Finished Mar 24 01:56:58 PM PDT 24
Peak memory 251496 kb
Host smart-40d43e87-7076-4b26-ab13-b8cbbacfc858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808805491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.808805491
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.348961153
Short name T404
Test name
Test status
Simulation time 287361664 ps
CPU time 6.11 seconds
Started Mar 24 01:56:29 PM PDT 24
Finished Mar 24 01:56:35 PM PDT 24
Peak memory 246776 kb
Host smart-207cb548-10ed-43cd-9371-0790c6d513bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348961153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.348961153
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3740962089
Short name T730
Test name
Test status
Simulation time 93802255 ps
CPU time 6.73 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:38 PM PDT 24
Peak memory 247232 kb
Host smart-6d4b1d2f-e554-4e40-92cc-8e9478a5d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740962089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3740962089
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.282157016
Short name T510
Test name
Test status
Simulation time 27157056740 ps
CPU time 101.06 seconds
Started Mar 24 02:36:32 PM PDT 24
Finished Mar 24 02:38:14 PM PDT 24
Peak memory 251628 kb
Host smart-b080a040-1a82-435f-8c1f-81439dfbb458
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282157016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.282157016
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.30575227
Short name T597
Test name
Test status
Simulation time 7578639603 ps
CPU time 82.31 seconds
Started Mar 24 01:56:38 PM PDT 24
Finished Mar 24 01:58:01 PM PDT 24
Peak memory 251408 kb
Host smart-a3f19684-b9d3-4c3b-a36b-93b992b17aed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30575227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.lc_ctrl_stress_all.30575227
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2119235040
Short name T974
Test name
Test status
Simulation time 29828156 ps
CPU time 1.17 seconds
Started Mar 24 01:56:27 PM PDT 24
Finished Mar 24 01:56:29 PM PDT 24
Peak memory 212156 kb
Host smart-4712c3a7-1376-40a8-a401-0bc2659edfb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119235040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.2119235040
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3543972320
Short name T1646
Test name
Test status
Simulation time 42740859 ps
CPU time 0.77 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 209024 kb
Host smart-28326f4c-9eae-49fa-955a-1806f3664b06
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543972320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3543972320
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1484697881
Short name T663
Test name
Test status
Simulation time 29171771 ps
CPU time 1.08 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:36 PM PDT 24
Peak memory 209972 kb
Host smart-79fd5e32-d366-41c6-aa77-c07f24d05acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484697881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1484697881
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3469883749
Short name T832
Test name
Test status
Simulation time 21802719 ps
CPU time 1.23 seconds
Started Mar 24 01:56:39 PM PDT 24
Finished Mar 24 01:56:40 PM PDT 24
Peak memory 209980 kb
Host smart-b8fd038c-65c5-40b2-820f-82fdfe230239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469883749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3469883749
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1558873451
Short name T1338
Test name
Test status
Simulation time 4638743768 ps
CPU time 12.02 seconds
Started Mar 24 01:56:34 PM PDT 24
Finished Mar 24 01:56:46 PM PDT 24
Peak memory 218612 kb
Host smart-a4f5fbef-6b0b-4cff-afa9-69cc36abba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558873451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1558873451
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1780303258
Short name T492
Test name
Test status
Simulation time 884924653 ps
CPU time 12.8 seconds
Started Mar 24 02:36:35 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 218468 kb
Host smart-a7c9109e-d124-423a-816b-c38be5bd98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780303258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1780303258
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1055558875
Short name T1377
Test name
Test status
Simulation time 319457714 ps
CPU time 7.9 seconds
Started Mar 24 01:56:39 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 217472 kb
Host smart-8b514d0b-a24d-4398-aa4b-c80dc5d53b54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055558875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1055558875
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1072488373
Short name T1706
Test name
Test status
Simulation time 2499946649 ps
CPU time 6.36 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 210100 kb
Host smart-c662cf29-8663-428a-a971-b5dce54aa6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072488373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1072488373
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1258809898
Short name T567
Test name
Test status
Simulation time 68113008 ps
CPU time 2.9 seconds
Started Mar 24 01:56:38 PM PDT 24
Finished Mar 24 01:56:41 PM PDT 24
Peak memory 222876 kb
Host smart-bad37fb3-c802-4ead-bd56-8896d285d612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258809898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1258809898
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3792462750
Short name T1525
Test name
Test status
Simulation time 21540177 ps
CPU time 1.8 seconds
Started Mar 24 02:36:30 PM PDT 24
Finished Mar 24 02:36:32 PM PDT 24
Peak memory 221824 kb
Host smart-47b942c8-f3b1-47e4-86eb-7c666d3d7686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792462750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3792462750
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.1659027490
Short name T1391
Test name
Test status
Simulation time 3391260262 ps
CPU time 25.37 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:57 PM PDT 24
Peak memory 219856 kb
Host smart-60db21bd-f9b7-4fbf-abcd-cba4dbb6d9f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659027490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.1659027490
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2853080075
Short name T1538
Test name
Test status
Simulation time 1311448204 ps
CPU time 14.68 seconds
Started Mar 24 01:56:32 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 226696 kb
Host smart-fe663945-e115-4742-bb98-7817f546b5e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853080075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2853080075
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3361198037
Short name T1114
Test name
Test status
Simulation time 1651997187 ps
CPU time 12.8 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 218532 kb
Host smart-0adfc978-8ecd-4c8e-9fc8-b038782e482f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361198037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3361198037
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.420984353
Short name T645
Test name
Test status
Simulation time 847375324 ps
CPU time 11.94 seconds
Started Mar 24 02:36:35 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 218572 kb
Host smart-d8c254bf-3fc8-4e96-891f-a7b135dc9f62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420984353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.420984353
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1512924644
Short name T866
Test name
Test status
Simulation time 13017415440 ps
CPU time 14.89 seconds
Started Mar 24 02:36:30 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 218648 kb
Host smart-8f139249-3f71-40dd-b0f9-3906ad8eeae8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512924644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1512924644
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1813147140
Short name T1466
Test name
Test status
Simulation time 847286174 ps
CPU time 6.78 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:56:53 PM PDT 24
Peak memory 218512 kb
Host smart-0fbc558f-c332-456e-8232-c395293e9979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813147140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1813147140
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3225386478
Short name T1195
Test name
Test status
Simulation time 924614347 ps
CPU time 16.63 seconds
Started Mar 24 01:56:35 PM PDT 24
Finished Mar 24 01:56:52 PM PDT 24
Peak memory 226564 kb
Host smart-26743154-c1e3-48a5-92e5-af31ab06ae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225386478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3225386478
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.508824968
Short name T1086
Test name
Test status
Simulation time 4931932323 ps
CPU time 11.67 seconds
Started Mar 24 02:36:31 PM PDT 24
Finished Mar 24 02:36:43 PM PDT 24
Peak memory 226436 kb
Host smart-c605cf7f-efdd-467b-a8bb-60663cd329ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508824968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.508824968
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2286255521
Short name T1633
Test name
Test status
Simulation time 44319854 ps
CPU time 2.99 seconds
Started Mar 24 02:36:32 PM PDT 24
Finished Mar 24 02:36:35 PM PDT 24
Peak memory 214584 kb
Host smart-aa686bce-6d44-4af7-b96c-be205ffa5c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286255521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2286255521
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.4255805203
Short name T772
Test name
Test status
Simulation time 94679698 ps
CPU time 2.71 seconds
Started Mar 24 01:56:33 PM PDT 24
Finished Mar 24 01:56:36 PM PDT 24
Peak memory 214876 kb
Host smart-e549a54a-7668-4ad2-9fdb-47de8e1e5413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255805203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4255805203
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.439284320
Short name T381
Test name
Test status
Simulation time 206457007 ps
CPU time 25.97 seconds
Started Mar 24 01:56:33 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 251500 kb
Host smart-e1bc2e86-6331-45ad-a188-223885357b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439284320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.439284320
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.577833713
Short name T1473
Test name
Test status
Simulation time 413050920 ps
CPU time 31.28 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:37:06 PM PDT 24
Peak memory 251484 kb
Host smart-c15bb967-99b0-4442-97bb-751483fbdcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577833713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.577833713
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1336567543
Short name T1017
Test name
Test status
Simulation time 282535190 ps
CPU time 7.09 seconds
Started Mar 24 01:56:32 PM PDT 24
Finished Mar 24 01:56:40 PM PDT 24
Peak memory 248092 kb
Host smart-bf07e8c0-f6b0-4d1a-919f-833cdbd9c0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336567543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1336567543
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1363324497
Short name T1440
Test name
Test status
Simulation time 113787445 ps
CPU time 4 seconds
Started Mar 24 02:36:32 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 223196 kb
Host smart-b2acbea1-1a69-44f3-87f8-c4781ec33433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363324497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1363324497
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.401381312
Short name T608
Test name
Test status
Simulation time 14761970665 ps
CPU time 54.98 seconds
Started Mar 24 02:36:36 PM PDT 24
Finished Mar 24 02:37:31 PM PDT 24
Peak memory 251532 kb
Host smart-6da9c585-eeb5-4372-8840-9cfeb347523d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401381312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.401381312
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4251138409
Short name T1161
Test name
Test status
Simulation time 24917313543 ps
CPU time 201.24 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 02:00:07 PM PDT 24
Peak memory 276128 kb
Host smart-e584b076-27a7-46e1-8966-aa1a0698fec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251138409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4251138409
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2432763240
Short name T415
Test name
Test status
Simulation time 21028299 ps
CPU time 0.99 seconds
Started Mar 24 01:56:38 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 212028 kb
Host smart-3a75b280-4d2e-43f7-b84d-7b1ee641a30b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432763240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2432763240
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3130171202
Short name T716
Test name
Test status
Simulation time 13200933 ps
CPU time 0.77 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 209756 kb
Host smart-3cd7479d-1619-4534-8c1a-ae44ae9bdb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130171202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3130171202
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.687211724
Short name T285
Test name
Test status
Simulation time 73192952 ps
CPU time 0.97 seconds
Started Mar 24 01:56:37 PM PDT 24
Finished Mar 24 01:56:38 PM PDT 24
Peak memory 209876 kb
Host smart-180300bb-3073-442c-8aa7-e0600e4b647f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687211724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.687211724
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.165759935
Short name T1085
Test name
Test status
Simulation time 222155772 ps
CPU time 10.79 seconds
Started Mar 24 02:36:35 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 218568 kb
Host smart-c3fa6e79-c931-475f-af6e-441440fb91ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165759935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.165759935
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3873783459
Short name T434
Test name
Test status
Simulation time 1175883572 ps
CPU time 14.16 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:57:00 PM PDT 24
Peak memory 218508 kb
Host smart-3295f763-fdf3-40e6-95d3-cf1c441c385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873783459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3873783459
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1274765227
Short name T1193
Test name
Test status
Simulation time 70113135 ps
CPU time 1.42 seconds
Started Mar 24 02:36:37 PM PDT 24
Finished Mar 24 02:36:39 PM PDT 24
Peak memory 210016 kb
Host smart-f8c19791-4743-45cc-86e6-92d6ceeb8a08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274765227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1274765227
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2149023977
Short name T1096
Test name
Test status
Simulation time 241924809 ps
CPU time 1.42 seconds
Started Mar 24 01:56:37 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 217356 kb
Host smart-bd7c33ee-58d7-4323-bac6-7f1d22625bdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149023977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2149023977
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3000862940
Short name T953
Test name
Test status
Simulation time 73905696 ps
CPU time 2.74 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:43 PM PDT 24
Peak memory 222520 kb
Host smart-c9acbaa2-1eaa-4fb0-8e2f-53be2f852c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000862940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3000862940
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4111435821
Short name T204
Test name
Test status
Simulation time 44104863 ps
CPU time 1.53 seconds
Started Mar 24 01:56:37 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 222148 kb
Host smart-8028bf43-db8a-4060-b5d9-e56f0f4b3160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111435821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4111435821
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.146742810
Short name T991
Test name
Test status
Simulation time 3192784046 ps
CPU time 19.22 seconds
Started Mar 24 01:56:39 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 219956 kb
Host smart-71d80d90-7f9a-4dbe-8791-101ad4e55b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146742810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.146742810
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1879968512
Short name T1037
Test name
Test status
Simulation time 334563422 ps
CPU time 14.99 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:55 PM PDT 24
Peak memory 219516 kb
Host smart-a2f24fe0-251e-4f6e-8dc4-b7f28c300852
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879968512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1879968512
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.111138885
Short name T1502
Test name
Test status
Simulation time 705029929 ps
CPU time 10.8 seconds
Started Mar 24 02:36:37 PM PDT 24
Finished Mar 24 02:36:49 PM PDT 24
Peak memory 218596 kb
Host smart-48aff443-c09f-4a44-88f4-d53ac540bf66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111138885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.111138885
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.2849173592
Short name T979
Test name
Test status
Simulation time 3755418566 ps
CPU time 12.72 seconds
Started Mar 24 01:56:41 PM PDT 24
Finished Mar 24 01:56:54 PM PDT 24
Peak memory 219540 kb
Host smart-67b3abc9-aed2-4567-b4db-3e80b83e7b92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849173592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.2849173592
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1450487605
Short name T515
Test name
Test status
Simulation time 339174826 ps
CPU time 13.61 seconds
Started Mar 24 01:56:39 PM PDT 24
Finished Mar 24 01:56:53 PM PDT 24
Peak memory 218636 kb
Host smart-131e6fb3-65a9-4246-92ae-8f32c2165f43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450487605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1450487605
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.234780157
Short name T799
Test name
Test status
Simulation time 1444195479 ps
CPU time 9.89 seconds
Started Mar 24 02:36:36 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 218652 kb
Host smart-38fea97a-f699-4d7a-84d5-1c91a6860a82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234780157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.234780157
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3856092356
Short name T676
Test name
Test status
Simulation time 2232535245 ps
CPU time 13.91 seconds
Started Mar 24 01:56:41 PM PDT 24
Finished Mar 24 01:56:55 PM PDT 24
Peak memory 225508 kb
Host smart-ddac071c-ac63-4171-bdbd-fe524847a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856092356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3856092356
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.687938574
Short name T1201
Test name
Test status
Simulation time 4673759707 ps
CPU time 12.51 seconds
Started Mar 24 02:36:38 PM PDT 24
Finished Mar 24 02:36:51 PM PDT 24
Peak memory 226720 kb
Host smart-0b26e5e3-39c7-4d6b-8c51-a2bf97c56a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687938574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.687938574
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2609322176
Short name T1000
Test name
Test status
Simulation time 53119298 ps
CPU time 2.93 seconds
Started Mar 24 01:56:39 PM PDT 24
Finished Mar 24 01:56:42 PM PDT 24
Peak memory 214664 kb
Host smart-1ad0e998-f030-4934-bb03-cb01334d0a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609322176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2609322176
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4019292301
Short name T528
Test name
Test status
Simulation time 62345667 ps
CPU time 1.57 seconds
Started Mar 24 02:36:37 PM PDT 24
Finished Mar 24 02:36:39 PM PDT 24
Peak memory 214300 kb
Host smart-056fa65a-8979-4a5d-8f89-9d120f0aa511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019292301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4019292301
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2615648803
Short name T1251
Test name
Test status
Simulation time 275051612 ps
CPU time 32.71 seconds
Started Mar 24 01:56:33 PM PDT 24
Finished Mar 24 01:57:06 PM PDT 24
Peak memory 251488 kb
Host smart-bf81e99c-cc4e-40ae-9fa5-b3d8097962ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615648803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2615648803
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.650191500
Short name T1335
Test name
Test status
Simulation time 1872356403 ps
CPU time 26.95 seconds
Started Mar 24 02:36:35 PM PDT 24
Finished Mar 24 02:37:02 PM PDT 24
Peak memory 251460 kb
Host smart-872209e1-f6cb-471e-bd14-52efe62a0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650191500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.650191500
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2864517825
Short name T1140
Test name
Test status
Simulation time 411560429 ps
CPU time 7.59 seconds
Started Mar 24 01:56:34 PM PDT 24
Finished Mar 24 01:56:42 PM PDT 24
Peak memory 250916 kb
Host smart-f4215ba2-1a19-4cf1-ba26-285717a92dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864517825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2864517825
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3149571109
Short name T1559
Test name
Test status
Simulation time 214526403 ps
CPU time 11.89 seconds
Started Mar 24 02:36:36 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 251488 kb
Host smart-444b5075-ead4-4163-9b2a-683aa7397b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149571109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3149571109
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3091713420
Short name T1343
Test name
Test status
Simulation time 7630261898 ps
CPU time 58.45 seconds
Started Mar 24 02:36:35 PM PDT 24
Finished Mar 24 02:37:34 PM PDT 24
Peak memory 226732 kb
Host smart-3db1c05c-c387-43f9-9240-9d34bc7379de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091713420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3091713420
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.676128197
Short name T989
Test name
Test status
Simulation time 68763519655 ps
CPU time 225.11 seconds
Started Mar 24 01:56:41 PM PDT 24
Finished Mar 24 02:00:26 PM PDT 24
Peak memory 243372 kb
Host smart-fdd69a9c-de12-4e10-b9b6-dbefe1b26c2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676128197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.676128197
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.953256147
Short name T800
Test name
Test status
Simulation time 34060268350 ps
CPU time 293.81 seconds
Started Mar 24 01:56:39 PM PDT 24
Finished Mar 24 02:01:33 PM PDT 24
Peak memory 260940 kb
Host smart-02e922db-d248-4057-91be-65a79a1b7bcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=953256147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.953256147
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3675200801
Short name T1056
Test name
Test status
Simulation time 36472742 ps
CPU time 0.83 seconds
Started Mar 24 01:56:33 PM PDT 24
Finished Mar 24 01:56:34 PM PDT 24
Peak memory 208884 kb
Host smart-78cd8638-daba-4ccd-9746-38ce4584d395
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675200801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3675200801
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3711058165
Short name T1173
Test name
Test status
Simulation time 13677418 ps
CPU time 0.8 seconds
Started Mar 24 02:36:37 PM PDT 24
Finished Mar 24 02:36:38 PM PDT 24
Peak memory 208304 kb
Host smart-93e7672a-5051-4636-adab-adc1389b1084
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711058165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3711058165
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3815018143
Short name T307
Test name
Test status
Simulation time 17770387 ps
CPU time 1.17 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 210008 kb
Host smart-fcd938df-949a-42dc-8da5-3d67670bbb25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815018143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3815018143
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.4268850277
Short name T646
Test name
Test status
Simulation time 18482552 ps
CPU time 0.86 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 209896 kb
Host smart-f523c21b-acb0-49c2-b438-a0c7f921e9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268850277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.4268850277
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1523625384
Short name T287
Test name
Test status
Simulation time 301193914 ps
CPU time 12.5 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 218556 kb
Host smart-1c493f76-24d5-4e94-b640-e754017efcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523625384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1523625384
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.540161654
Short name T1669
Test name
Test status
Simulation time 1541272003 ps
CPU time 14.03 seconds
Started Mar 24 01:56:44 PM PDT 24
Finished Mar 24 01:56:58 PM PDT 24
Peak memory 226688 kb
Host smart-0a516e83-244d-4534-9f97-a3ce2e0e8fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540161654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.540161654
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3246539009
Short name T719
Test name
Test status
Simulation time 559126061 ps
CPU time 8.19 seconds
Started Mar 24 01:56:42 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 210048 kb
Host smart-f6af7b39-1321-45f4-ab41-53d759891c1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246539009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3246539009
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3360547644
Short name T556
Test name
Test status
Simulation time 1778119602 ps
CPU time 15.85 seconds
Started Mar 24 02:36:37 PM PDT 24
Finished Mar 24 02:36:53 PM PDT 24
Peak memory 210048 kb
Host smart-cacbc536-6281-4893-8a92-cc7742683381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360547644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3360547644
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1631400566
Short name T907
Test name
Test status
Simulation time 134507947 ps
CPU time 2.95 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 222688 kb
Host smart-8b94ef18-111c-43fd-bb95-eddd3462f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631400566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1631400566
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.726303466
Short name T890
Test name
Test status
Simulation time 144214836 ps
CPU time 1.95 seconds
Started Mar 24 01:56:38 PM PDT 24
Finished Mar 24 01:56:40 PM PDT 24
Peak memory 218588 kb
Host smart-e58aa41c-b615-4963-87cf-35159cf82cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726303466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.726303466
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.183059737
Short name T1230
Test name
Test status
Simulation time 932445414 ps
CPU time 11.73 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 219548 kb
Host smart-3302abec-ee1a-4a0d-830c-96c130a62566
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183059737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.183059737
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1415940296
Short name T402
Test name
Test status
Simulation time 1037384886 ps
CPU time 9.61 seconds
Started Mar 24 02:36:37 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 218500 kb
Host smart-a66b75c2-2e78-47d1-8936-0abfd1952563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415940296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1415940296
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3428964842
Short name T776
Test name
Test status
Simulation time 3486091153 ps
CPU time 14.03 seconds
Started Mar 24 01:56:42 PM PDT 24
Finished Mar 24 01:56:56 PM PDT 24
Peak memory 219520 kb
Host smart-09dc3613-580f-41dc-a2cd-efbbdf505409
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428964842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3428964842
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2769094363
Short name T1310
Test name
Test status
Simulation time 171494237 ps
CPU time 7.8 seconds
Started Mar 24 01:56:47 PM PDT 24
Finished Mar 24 01:56:55 PM PDT 24
Peak memory 218604 kb
Host smart-b687c697-b62e-4087-8e10-c6ffb9d57831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769094363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2769094363
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.601822942
Short name T1597
Test name
Test status
Simulation time 1068838007 ps
CPU time 6.01 seconds
Started Mar 24 02:36:34 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 218536 kb
Host smart-4b4d36c9-6e01-421c-a67c-0e465610c74d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601822942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.601822942
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3995299275
Short name T1294
Test name
Test status
Simulation time 343503317 ps
CPU time 8.7 seconds
Started Mar 24 01:56:43 PM PDT 24
Finished Mar 24 01:56:52 PM PDT 24
Peak memory 225280 kb
Host smart-5f21544d-e132-443e-95c2-387353503a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995299275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3995299275
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.4138011880
Short name T1641
Test name
Test status
Simulation time 222220205 ps
CPU time 8.85 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:52 PM PDT 24
Peak memory 225244 kb
Host smart-01c2880e-17b3-4aa6-95db-d4db90685cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138011880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.4138011880
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2257673887
Short name T1166
Test name
Test status
Simulation time 180109870 ps
CPU time 2.72 seconds
Started Mar 24 02:36:36 PM PDT 24
Finished Mar 24 02:36:39 PM PDT 24
Peak memory 218752 kb
Host smart-6641d8a0-0078-48ef-9418-a6593c89af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257673887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2257673887
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.4282043603
Short name T1158
Test name
Test status
Simulation time 126864771 ps
CPU time 4.28 seconds
Started Mar 24 01:56:36 PM PDT 24
Finished Mar 24 01:56:41 PM PDT 24
Peak memory 218228 kb
Host smart-f344b5fc-a65d-4986-9810-637200998c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282043603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.4282043603
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.1503192290
Short name T1429
Test name
Test status
Simulation time 1793135231 ps
CPU time 28.5 seconds
Started Mar 24 01:56:40 PM PDT 24
Finished Mar 24 01:57:09 PM PDT 24
Peak memory 251572 kb
Host smart-1b539bed-eb47-4184-9280-3b2a0991b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503192290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.1503192290
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3773240360
Short name T1110
Test name
Test status
Simulation time 191763033 ps
CPU time 22.83 seconds
Started Mar 24 02:36:36 PM PDT 24
Finished Mar 24 02:36:59 PM PDT 24
Peak memory 251532 kb
Host smart-135b11e2-6301-45e1-859b-9bab31b00026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773240360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3773240360
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1249992967
Short name T1527
Test name
Test status
Simulation time 302905945 ps
CPU time 3.12 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 222744 kb
Host smart-ab5ff3fb-3488-464c-97e6-0aa08ea27a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249992967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1249992967
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3473656865
Short name T1364
Test name
Test status
Simulation time 125879288 ps
CPU time 2.92 seconds
Started Mar 24 01:56:40 PM PDT 24
Finished Mar 24 01:56:43 PM PDT 24
Peak memory 221464 kb
Host smart-dfe05cf5-f861-4d78-b917-1b9b18297d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473656865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3473656865
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1473587292
Short name T112
Test name
Test status
Simulation time 20808133270 ps
CPU time 116.65 seconds
Started Mar 24 01:56:45 PM PDT 24
Finished Mar 24 01:58:42 PM PDT 24
Peak memory 251556 kb
Host smart-f1665268-2b30-4769-b8b2-e9ad07d0f473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473587292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1473587292
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2064289513
Short name T1631
Test name
Test status
Simulation time 4528904898 ps
CPU time 124.29 seconds
Started Mar 24 02:36:42 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 251528 kb
Host smart-729205a9-8298-4daf-8bc8-643398ce34e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064289513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2064289513
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.302552320
Short name T852
Test name
Test status
Simulation time 14056980 ps
CPU time 0.85 seconds
Started Mar 24 01:56:38 PM PDT 24
Finished Mar 24 01:56:39 PM PDT 24
Peak memory 209036 kb
Host smart-b06d4aa2-fe41-4a68-bf5b-e3e4e376aa45
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302552320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.302552320
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.593247039
Short name T1411
Test name
Test status
Simulation time 50161324 ps
CPU time 0.92 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:42 PM PDT 24
Peak memory 212212 kb
Host smart-283cfae3-ee25-43d6-855a-1ffb838f2ebf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593247039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.593247039
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2513565840
Short name T120
Test name
Test status
Simulation time 24027032 ps
CPU time 1.07 seconds
Started Mar 24 02:36:42 PM PDT 24
Finished Mar 24 02:36:43 PM PDT 24
Peak memory 210016 kb
Host smart-7bf2c9e0-de58-4a47-904a-b9f1482e2591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513565840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2513565840
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.612947101
Short name T201
Test name
Test status
Simulation time 100504393 ps
CPU time 1.32 seconds
Started Mar 24 01:56:42 PM PDT 24
Finished Mar 24 01:56:44 PM PDT 24
Peak memory 209924 kb
Host smart-36158466-7ae1-41c8-96b5-bfece72080e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612947101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.612947101
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1682629111
Short name T1507
Test name
Test status
Simulation time 318718725 ps
CPU time 10.72 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:57 PM PDT 24
Peak memory 226676 kb
Host smart-06a1cecb-c0ef-48b9-b480-7eb8b5229fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682629111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1682629111
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3783414320
Short name T522
Test name
Test status
Simulation time 1292183789 ps
CPU time 12.13 seconds
Started Mar 24 01:56:43 PM PDT 24
Finished Mar 24 01:56:56 PM PDT 24
Peak memory 226696 kb
Host smart-ac952d1e-1128-4366-b940-189a7474adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783414320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3783414320
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1292393403
Short name T1232
Test name
Test status
Simulation time 1584265797 ps
CPU time 9.81 seconds
Started Mar 24 01:56:44 PM PDT 24
Finished Mar 24 01:56:54 PM PDT 24
Peak memory 210040 kb
Host smart-b8b0de28-7a16-486c-8050-a7fa95e0ce4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292393403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1292393403
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.376578613
Short name T1691
Test name
Test status
Simulation time 3228674445 ps
CPU time 8.08 seconds
Started Mar 24 02:36:42 PM PDT 24
Finished Mar 24 02:36:50 PM PDT 24
Peak memory 218096 kb
Host smart-79a68e7e-809d-4d8d-8f98-b03ea77ebbc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376578613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.376578613
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1045389525
Short name T386
Test name
Test status
Simulation time 89657516 ps
CPU time 3.2 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 218672 kb
Host smart-2705c41f-74d1-4181-87f7-635ac1413adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045389525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1045389525
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2422927311
Short name T530
Test name
Test status
Simulation time 146529949 ps
CPU time 2.57 seconds
Started Mar 24 01:56:45 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 222404 kb
Host smart-52ca9bbc-2c48-4e82-a7ad-d4b847a334ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422927311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2422927311
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1157604596
Short name T929
Test name
Test status
Simulation time 1229597670 ps
CPU time 9.24 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:52 PM PDT 24
Peak memory 218856 kb
Host smart-474145b2-f09b-458c-9ad3-c267f475eb3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157604596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1157604596
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2957120258
Short name T1105
Test name
Test status
Simulation time 453269840 ps
CPU time 18.52 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:57:05 PM PDT 24
Peak memory 219512 kb
Host smart-47bb5421-a7d8-4743-a3a8-d4ea54eca99c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957120258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2957120258
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1563935882
Short name T596
Test name
Test status
Simulation time 489055318 ps
CPU time 13.03 seconds
Started Mar 24 01:56:42 PM PDT 24
Finished Mar 24 01:56:55 PM PDT 24
Peak memory 218500 kb
Host smart-8d89d5f1-0a4b-4a33-bc95-78d761b0515b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563935882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1563935882
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2091209615
Short name T1413
Test name
Test status
Simulation time 224136607 ps
CPU time 10.44 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:36:55 PM PDT 24
Peak memory 218660 kb
Host smart-3ea2bc3b-5d51-4bb9-a088-90c85c03c580
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091209615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2091209615
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.109472322
Short name T754
Test name
Test status
Simulation time 920149671 ps
CPU time 6.65 seconds
Started Mar 24 02:36:38 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 218512 kb
Host smart-8138c67e-824e-41e1-b497-65c7660b98e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109472322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.109472322
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1796027547
Short name T1007
Test name
Test status
Simulation time 4294369124 ps
CPU time 10.5 seconds
Started Mar 24 01:56:43 PM PDT 24
Finished Mar 24 01:56:54 PM PDT 24
Peak memory 218628 kb
Host smart-8879a124-70e3-4e49-8ec4-7011a5d5e109
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796027547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1796027547
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.38066872
Short name T102
Test name
Test status
Simulation time 391458953 ps
CPU time 14.09 seconds
Started Mar 24 02:36:41 PM PDT 24
Finished Mar 24 02:36:55 PM PDT 24
Peak memory 226684 kb
Host smart-ae435b7a-4221-4a69-8eca-7f74c34f1fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38066872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.38066872
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.754299991
Short name T450
Test name
Test status
Simulation time 372267883 ps
CPU time 14.36 seconds
Started Mar 24 01:56:43 PM PDT 24
Finished Mar 24 01:56:58 PM PDT 24
Peak memory 226684 kb
Host smart-965c69a7-be25-4056-a85c-3bc3722b5597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754299991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.754299991
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4167841188
Short name T917
Test name
Test status
Simulation time 169799916 ps
CPU time 1.45 seconds
Started Mar 24 01:56:50 PM PDT 24
Finished Mar 24 01:56:52 PM PDT 24
Peak memory 218220 kb
Host smart-abbae191-7b9b-4e6a-8373-fcb3034af379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167841188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4167841188
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.971330537
Short name T781
Test name
Test status
Simulation time 54993056 ps
CPU time 2.19 seconds
Started Mar 24 02:36:42 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 214800 kb
Host smart-e326720b-d7ff-4738-a3bb-f181d795317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971330537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.971330537
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1012858721
Short name T918
Test name
Test status
Simulation time 891307527 ps
CPU time 28.59 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 247512 kb
Host smart-147fa241-a51d-439b-a16f-cdc546deab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012858721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1012858721
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2101858220
Short name T286
Test name
Test status
Simulation time 992644925 ps
CPU time 30.89 seconds
Started Mar 24 01:56:43 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 245976 kb
Host smart-6705a8a2-adf6-48fa-a349-602af79c5f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101858220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2101858220
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3381095329
Short name T278
Test name
Test status
Simulation time 349658103 ps
CPU time 7.96 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 251536 kb
Host smart-ae8bcad2-5abb-48fb-af9b-9bb748ae6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381095329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3381095329
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3896685320
Short name T868
Test name
Test status
Simulation time 77889239 ps
CPU time 3.31 seconds
Started Mar 24 01:56:47 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 222668 kb
Host smart-ba05393b-52b2-4cc6-966d-5dd812c46b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896685320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3896685320
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3211251561
Short name T1309
Test name
Test status
Simulation time 26981515058 ps
CPU time 792.66 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 02:10:02 PM PDT 24
Peak memory 286004 kb
Host smart-a576f265-6670-438e-9bdd-5b5a611c33d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211251561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3211251561
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.649763640
Short name T620
Test name
Test status
Simulation time 30837087882 ps
CPU time 231.77 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:40:39 PM PDT 24
Peak memory 276796 kb
Host smart-0242ee60-ee9c-407b-ade6-c9071128bb18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649763640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.649763640
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2320024857
Short name T1560
Test name
Test status
Simulation time 14775885 ps
CPU time 1.08 seconds
Started Mar 24 02:36:41 PM PDT 24
Finished Mar 24 02:36:42 PM PDT 24
Peak memory 212096 kb
Host smart-95ae08e7-d1bf-45ba-9a99-d11838941162
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320024857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2320024857
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3279478523
Short name T1333
Test name
Test status
Simulation time 11288646 ps
CPU time 0.82 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 209208 kb
Host smart-60e6977e-f200-46ac-9d32-bb42f80f8819
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279478523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3279478523
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2342421516
Short name T682
Test name
Test status
Simulation time 61841045 ps
CPU time 1.1 seconds
Started Mar 24 01:56:48 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 209972 kb
Host smart-fe6aa743-ce48-4f2a-9315-24ab8df4c02a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342421516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2342421516
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4238049155
Short name T971
Test name
Test status
Simulation time 17817653 ps
CPU time 0.87 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 209936 kb
Host smart-4819531c-f5f8-4045-877e-9a59c97c11bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238049155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4238049155
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.302729367
Short name T121
Test name
Test status
Simulation time 1713538961 ps
CPU time 17.56 seconds
Started Mar 24 01:56:50 PM PDT 24
Finished Mar 24 01:57:08 PM PDT 24
Peak memory 218512 kb
Host smart-7ee0809e-92ab-467c-9ed3-2899e9d491f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302729367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.302729367
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4270147743
Short name T1483
Test name
Test status
Simulation time 233987689 ps
CPU time 11.21 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:54 PM PDT 24
Peak memory 218804 kb
Host smart-1d4ad6b3-214b-4316-a806-280bf37d1efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270147743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4270147743
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2687031595
Short name T494
Test name
Test status
Simulation time 391770302 ps
CPU time 10.85 seconds
Started Mar 24 01:56:50 PM PDT 24
Finished Mar 24 01:57:01 PM PDT 24
Peak memory 210036 kb
Host smart-7ca9c052-ab2a-4cc8-ad69-b9911651b083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687031595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2687031595
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.710929697
Short name T1670
Test name
Test status
Simulation time 290518129 ps
CPU time 5.37 seconds
Started Mar 24 02:36:44 PM PDT 24
Finished Mar 24 02:36:50 PM PDT 24
Peak memory 210300 kb
Host smart-df54994e-b101-4c37-9b52-544c55508b78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710929697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.710929697
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2148050769
Short name T1452
Test name
Test status
Simulation time 47456207 ps
CPU time 2.32 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 222268 kb
Host smart-d5446a43-585f-40b4-bcb7-fa05b0106219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148050769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2148050769
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.27042542
Short name T651
Test name
Test status
Simulation time 40029835 ps
CPU time 1.55 seconds
Started Mar 24 01:56:48 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 222176 kb
Host smart-651bbbda-0cb0-46bc-8366-a29021063909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27042542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.27042542
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.256381811
Short name T1361
Test name
Test status
Simulation time 424732499 ps
CPU time 10.8 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 01:57:00 PM PDT 24
Peak memory 218948 kb
Host smart-bb7e62ee-4637-4bfe-8389-6a95c8f9ee48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256381811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.256381811
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4164124119
Short name T1225
Test name
Test status
Simulation time 1324970136 ps
CPU time 16.24 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:57 PM PDT 24
Peak memory 219484 kb
Host smart-78ccde94-8b83-484c-91a4-214d1ee08e03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164124119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4164124119
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.111970109
Short name T44
Test name
Test status
Simulation time 330350658 ps
CPU time 13.7 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:13 PM PDT 24
Peak memory 218580 kb
Host smart-fc984bed-35ca-4a48-b930-91ba51168328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111970109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.111970109
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3396115444
Short name T1442
Test name
Test status
Simulation time 771538777 ps
CPU time 16.74 seconds
Started Mar 24 02:36:52 PM PDT 24
Finished Mar 24 02:37:11 PM PDT 24
Peak memory 218528 kb
Host smart-a15cf70b-6a1d-443c-8795-79d1b5ec4798
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396115444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3396115444
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.682808498
Short name T1111
Test name
Test status
Simulation time 292034127 ps
CPU time 10.55 seconds
Started Mar 24 01:56:51 PM PDT 24
Finished Mar 24 01:57:02 PM PDT 24
Peak memory 218588 kb
Host smart-c6cfb763-9469-484f-b659-4c325c60be7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682808498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.682808498
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.68335059
Short name T1183
Test name
Test status
Simulation time 348690156 ps
CPU time 12.97 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:36:58 PM PDT 24
Peak memory 218592 kb
Host smart-ae0e2960-91f8-4d46-9fd6-0065ca7755f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68335059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.68335059
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2782653876
Short name T1214
Test name
Test status
Simulation time 948527642 ps
CPU time 9.47 seconds
Started Mar 24 02:36:42 PM PDT 24
Finished Mar 24 02:36:52 PM PDT 24
Peak memory 226040 kb
Host smart-3af238a5-d4ed-4716-8afe-5188b2bb8988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782653876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2782653876
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.814968676
Short name T223
Test name
Test status
Simulation time 1877928770 ps
CPU time 11.21 seconds
Started Mar 24 01:56:52 PM PDT 24
Finished Mar 24 01:57:03 PM PDT 24
Peak memory 226568 kb
Host smart-e995d143-1330-4a89-8e29-a7a6a17ed6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814968676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.814968676
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.1307987418
Short name T976
Test name
Test status
Simulation time 775019038 ps
CPU time 2.99 seconds
Started Mar 24 01:56:43 PM PDT 24
Finished Mar 24 01:56:46 PM PDT 24
Peak memory 214980 kb
Host smart-a1c0cb26-fa5b-4707-ab01-4f2e369431d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307987418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1307987418
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.273866067
Short name T775
Test name
Test status
Simulation time 40781254 ps
CPU time 1.83 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:45 PM PDT 24
Peak memory 214156 kb
Host smart-47d5d0dd-1d0e-461f-88f7-d7949a4ebd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273866067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.273866067
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3186307077
Short name T1566
Test name
Test status
Simulation time 428295314 ps
CPU time 24.72 seconds
Started Mar 24 02:36:39 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 251496 kb
Host smart-cbc7d2a8-6404-45f8-8d77-b66ddbe2c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186307077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3186307077
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.659456996
Short name T1138
Test name
Test status
Simulation time 1100743431 ps
CPU time 27.05 seconds
Started Mar 24 01:56:45 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 251500 kb
Host smart-613ec4aa-7b8a-486d-ad90-a2829219718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659456996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.659456996
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2119072439
Short name T601
Test name
Test status
Simulation time 96696775 ps
CPU time 10.4 seconds
Started Mar 24 02:36:40 PM PDT 24
Finished Mar 24 02:36:51 PM PDT 24
Peak memory 251512 kb
Host smart-09189c9d-1a5f-4cf7-b1b7-6eec2b1bccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119072439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2119072439
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2529367990
Short name T458
Test name
Test status
Simulation time 41918117 ps
CPU time 3.1 seconds
Started Mar 24 01:56:42 PM PDT 24
Finished Mar 24 01:56:45 PM PDT 24
Peak memory 218512 kb
Host smart-1ac9b963-7a2f-4ef2-842f-2b4ae731ae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529367990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2529367990
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2573798608
Short name T320
Test name
Test status
Simulation time 4066408000 ps
CPU time 76.5 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 01:58:06 PM PDT 24
Peak memory 277108 kb
Host smart-91701b0b-dd88-4aa2-8804-7e4244489b53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573798608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2573798608
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.4236907476
Short name T1229
Test name
Test status
Simulation time 5173351006 ps
CPU time 101.66 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 273000 kb
Host smart-100fcdee-f424-4092-b6dd-34077021986c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236907476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.4236907476
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2060822623
Short name T128
Test name
Test status
Simulation time 19207711805 ps
CPU time 625.09 seconds
Started Mar 24 02:36:47 PM PDT 24
Finished Mar 24 02:47:14 PM PDT 24
Peak memory 284388 kb
Host smart-ae2b5d25-3953-4831-9520-cd85f00b2a28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2060822623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.2060822623
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2341036947
Short name T878
Test name
Test status
Simulation time 18901963 ps
CPU time 0.86 seconds
Started Mar 24 02:36:43 PM PDT 24
Finished Mar 24 02:36:44 PM PDT 24
Peak memory 212480 kb
Host smart-34872a3a-ca25-4ac3-bd86-5b55b589c4b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341036947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2341036947
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2738071367
Short name T1642
Test name
Test status
Simulation time 18467678 ps
CPU time 0.89 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:56:47 PM PDT 24
Peak memory 209068 kb
Host smart-9162b732-6976-4526-a031-eb7f07d980f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738071367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2738071367
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3172963503
Short name T460
Test name
Test status
Simulation time 19774972 ps
CPU time 1.03 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 209980 kb
Host smart-f954a3a9-4633-4c4c-a390-a5213e463970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172963503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3172963503
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.944787284
Short name T508
Test name
Test status
Simulation time 63259677 ps
CPU time 1.14 seconds
Started Mar 24 01:56:51 PM PDT 24
Finished Mar 24 01:56:52 PM PDT 24
Peak memory 209868 kb
Host smart-c93a4180-0398-486d-98de-d7bb3ba07977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944787284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.944787284
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1500490247
Short name T927
Test name
Test status
Simulation time 5436497509 ps
CPU time 18.05 seconds
Started Mar 24 02:36:52 PM PDT 24
Finished Mar 24 02:37:13 PM PDT 24
Peak memory 218892 kb
Host smart-950a4778-f0f9-480a-94b7-3f5027bba0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500490247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1500490247
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3499633387
Short name T97
Test name
Test status
Simulation time 306823772 ps
CPU time 10.35 seconds
Started Mar 24 01:56:50 PM PDT 24
Finished Mar 24 01:57:01 PM PDT 24
Peak memory 226620 kb
Host smart-da1df83d-f068-43f6-941a-fe0b152df9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499633387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3499633387
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2004079170
Short name T1374
Test name
Test status
Simulation time 532340285 ps
CPU time 4.79 seconds
Started Mar 24 01:56:48 PM PDT 24
Finished Mar 24 01:56:53 PM PDT 24
Peak memory 217352 kb
Host smart-20240944-75c1-47dc-913b-93cee0c27975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004079170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2004079170
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2480176838
Short name T1094
Test name
Test status
Simulation time 286887831 ps
CPU time 4.13 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:51 PM PDT 24
Peak memory 217756 kb
Host smart-4674ed73-e18e-48f2-a138-0f148058e16b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480176838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2480176838
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2906392524
Short name T1565
Test name
Test status
Simulation time 30399079 ps
CPU time 1.49 seconds
Started Mar 24 01:56:51 PM PDT 24
Finished Mar 24 01:56:53 PM PDT 24
Peak memory 221784 kb
Host smart-1a988b73-5663-4bf5-914b-174266ccfb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906392524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2906392524
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3550130381
Short name T611
Test name
Test status
Simulation time 78565029 ps
CPU time 2.12 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:49 PM PDT 24
Peak memory 222248 kb
Host smart-4f94691c-d769-4444-9760-a9dc29b6833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550130381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3550130381
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3669388431
Short name T1269
Test name
Test status
Simulation time 2288740626 ps
CPU time 10.01 seconds
Started Mar 24 01:56:51 PM PDT 24
Finished Mar 24 01:57:01 PM PDT 24
Peak memory 219524 kb
Host smart-a66d94f6-17b0-43c8-afd3-f9ec5383afba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669388431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3669388431
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.4060688284
Short name T43
Test name
Test status
Simulation time 1850489588 ps
CPU time 12.43 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:58 PM PDT 24
Peak memory 218664 kb
Host smart-a9be24dc-bc99-4aaa-8d03-25bc654bdc1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060688284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.4060688284
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.161335789
Short name T1617
Test name
Test status
Simulation time 341970688 ps
CPU time 13.21 seconds
Started Mar 24 01:56:50 PM PDT 24
Finished Mar 24 01:57:03 PM PDT 24
Peak memory 218572 kb
Host smart-1b6a34d1-0950-4101-8243-ed820f07feb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161335789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.161335789
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.905862794
Short name T1585
Test name
Test status
Simulation time 4223652837 ps
CPU time 11.63 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:36:57 PM PDT 24
Peak memory 218700 kb
Host smart-4d9470e7-580b-4991-aa49-7d2d77f9f8b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905862794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.905862794
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2431216442
Short name T659
Test name
Test status
Simulation time 250440337 ps
CPU time 10.87 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 01:57:00 PM PDT 24
Peak memory 218564 kb
Host smart-499bdcb5-aa82-4ea1-8b5a-defb07e7924a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431216442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2431216442
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3533131491
Short name T407
Test name
Test status
Simulation time 2218355042 ps
CPU time 12.69 seconds
Started Mar 24 02:36:52 PM PDT 24
Finished Mar 24 02:37:06 PM PDT 24
Peak memory 218596 kb
Host smart-2794c3b3-5265-48e7-bdcd-0856d3140ed3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533131491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3533131491
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1665092544
Short name T1134
Test name
Test status
Simulation time 544744342 ps
CPU time 8.89 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:56 PM PDT 24
Peak memory 225196 kb
Host smart-84dcb56a-5b77-4cc2-82c5-d1208922b95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665092544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1665092544
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3475203997
Short name T1322
Test name
Test status
Simulation time 266487313 ps
CPU time 8.41 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:07 PM PDT 24
Peak memory 225476 kb
Host smart-e53b4416-369e-483f-a270-21c05ae884c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475203997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3475203997
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1099012318
Short name T1576
Test name
Test status
Simulation time 91204812 ps
CPU time 3.54 seconds
Started Mar 24 01:56:53 PM PDT 24
Finished Mar 24 01:56:57 PM PDT 24
Peak memory 218404 kb
Host smart-84aa5f33-f9c7-4151-8d88-c16fba10406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099012318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1099012318
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.4199390657
Short name T1295
Test name
Test status
Simulation time 249025700 ps
CPU time 1.76 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:36:47 PM PDT 24
Peak memory 218216 kb
Host smart-f6e15873-50fc-483b-95b8-1eeca1946d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199390657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.4199390657
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2506726879
Short name T1686
Test name
Test status
Simulation time 506834534 ps
CPU time 35.76 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:37:21 PM PDT 24
Peak memory 251452 kb
Host smart-d0a2de6a-062e-4a24-9b0f-2dbb20e37c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506726879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2506726879
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3534571201
Short name T1237
Test name
Test status
Simulation time 195486418 ps
CPU time 25.56 seconds
Started Mar 24 01:56:48 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 251488 kb
Host smart-3997dff8-c11f-404d-9d20-de9dac05ce32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534571201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3534571201
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3771502955
Short name T343
Test name
Test status
Simulation time 55403443 ps
CPU time 6.41 seconds
Started Mar 24 02:36:47 PM PDT 24
Finished Mar 24 02:36:55 PM PDT 24
Peak memory 248804 kb
Host smart-c1325c91-83f2-40b4-88be-b526eab79caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771502955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3771502955
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.65340918
Short name T1351
Test name
Test status
Simulation time 50756712 ps
CPU time 3.42 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:02 PM PDT 24
Peak memory 222940 kb
Host smart-79e329bf-a649-4b0c-92f1-f3c8214b4747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65340918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.65340918
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2757077503
Short name T813
Test name
Test status
Simulation time 35233651846 ps
CPU time 61.12 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 01:57:51 PM PDT 24
Peak memory 229552 kb
Host smart-b1044870-b570-49ca-a0fc-d87b96e31b22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757077503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2757077503
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.832636245
Short name T208
Test name
Test status
Simulation time 95386178510 ps
CPU time 714.61 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:48:39 PM PDT 24
Peak memory 251320 kb
Host smart-1f56cc9d-4af4-4af3-a46c-ee6ad156e7e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832636245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.832636245
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2618731074
Short name T192
Test name
Test status
Simulation time 19552289010 ps
CPU time 691.85 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 02:08:21 PM PDT 24
Peak memory 422676 kb
Host smart-e411226b-085a-43ee-9055-1b476d071e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2618731074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2618731074
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3529110551
Short name T194
Test name
Test status
Simulation time 62242034608 ps
CPU time 547.11 seconds
Started Mar 24 02:36:50 PM PDT 24
Finished Mar 24 02:46:00 PM PDT 24
Peak memory 280440 kb
Host smart-83854172-ff62-43fe-9c47-76a41fdda975
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3529110551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3529110551
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1910022772
Short name T819
Test name
Test status
Simulation time 11993839 ps
CPU time 0.9 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:00 PM PDT 24
Peak memory 209060 kb
Host smart-670d3c93-b08f-4cfd-916f-616549ca5dbe
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910022772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1910022772
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.801074376
Short name T1511
Test name
Test status
Simulation time 44162284 ps
CPU time 0.85 seconds
Started Mar 24 02:36:45 PM PDT 24
Finished Mar 24 02:36:46 PM PDT 24
Peak memory 209048 kb
Host smart-6dc71319-8979-4ce7-ab9c-3943eff718ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801074376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.801074376
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3963989098
Short name T356
Test name
Test status
Simulation time 382756017 ps
CPU time 0.97 seconds
Started Mar 24 01:56:56 PM PDT 24
Finished Mar 24 01:56:57 PM PDT 24
Peak memory 209968 kb
Host smart-1cebaec6-5f2d-493e-80cb-01a2564005b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963989098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3963989098
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.89344472
Short name T767
Test name
Test status
Simulation time 22994132 ps
CPU time 1.12 seconds
Started Mar 24 02:36:55 PM PDT 24
Finished Mar 24 02:36:57 PM PDT 24
Peak memory 210164 kb
Host smart-3f339438-873a-4dd2-a8b6-734e1c8e02c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89344472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.89344472
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1781275816
Short name T420
Test name
Test status
Simulation time 381175957 ps
CPU time 10.39 seconds
Started Mar 24 02:36:49 PM PDT 24
Finished Mar 24 02:37:02 PM PDT 24
Peak memory 218488 kb
Host smart-f21c234b-faed-4e8b-bf0e-8fc916e42815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781275816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1781275816
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3611198251
Short name T1369
Test name
Test status
Simulation time 981047596 ps
CPU time 10.8 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:57:05 PM PDT 24
Peak memory 218512 kb
Host smart-420c2e51-7e83-46b6-a68c-bc4e386d3760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611198251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3611198251
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.191234421
Short name T886
Test name
Test status
Simulation time 153046093 ps
CPU time 1.58 seconds
Started Mar 24 02:36:50 PM PDT 24
Finished Mar 24 02:36:54 PM PDT 24
Peak memory 217368 kb
Host smart-ae0ea2b0-e363-46d5-9ed5-b969e64322bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191234421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.191234421
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.668775768
Short name T1088
Test name
Test status
Simulation time 1861716308 ps
CPU time 11.93 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:11 PM PDT 24
Peak memory 210000 kb
Host smart-60b9fedc-b670-40a7-98de-c186f4bbe01f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668775768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.668775768
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1447110523
Short name T427
Test name
Test status
Simulation time 97208216 ps
CPU time 2.17 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:56:58 PM PDT 24
Peak memory 222472 kb
Host smart-f6ca447b-be25-4a34-81ca-679898ecd138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447110523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1447110523
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.650562390
Short name T1548
Test name
Test status
Simulation time 479840883 ps
CPU time 3.02 seconds
Started Mar 24 02:36:49 PM PDT 24
Finished Mar 24 02:36:52 PM PDT 24
Peak memory 222464 kb
Host smart-23251b10-d082-4c39-9b86-649bcf826102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650562390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.650562390
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3421104914
Short name T1582
Test name
Test status
Simulation time 495549561 ps
CPU time 16.74 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 219500 kb
Host smart-1d3817da-8306-4e25-8683-e10a25a6db42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421104914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3421104914
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.3477770480
Short name T1422
Test name
Test status
Simulation time 627047592 ps
CPU time 25.65 seconds
Started Mar 24 02:36:49 PM PDT 24
Finished Mar 24 02:37:18 PM PDT 24
Peak memory 219828 kb
Host smart-b68285c0-8392-4942-9355-3f781eddfd98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477770480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3477770480
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2299377083
Short name T704
Test name
Test status
Simulation time 260121704 ps
CPU time 10.64 seconds
Started Mar 24 01:56:53 PM PDT 24
Finished Mar 24 01:57:04 PM PDT 24
Peak memory 218636 kb
Host smart-377d3906-5c6a-4041-a585-4f078acdd49a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299377083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2299377083
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3784180922
Short name T448
Test name
Test status
Simulation time 1010467460 ps
CPU time 11.62 seconds
Started Mar 24 02:36:50 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 218584 kb
Host smart-ee615ed7-4e6a-4181-93d3-b053a6a66203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784180922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3784180922
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2722075985
Short name T1501
Test name
Test status
Simulation time 509368912 ps
CPU time 8.56 seconds
Started Mar 24 02:36:51 PM PDT 24
Finished Mar 24 02:37:01 PM PDT 24
Peak memory 218588 kb
Host smart-17970c81-34cc-4993-bc28-b0e3c004dfbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722075985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2722075985
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3274922663
Short name T1580
Test name
Test status
Simulation time 315517272 ps
CPU time 9.54 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:57:04 PM PDT 24
Peak memory 218620 kb
Host smart-38d7ea91-ad59-4dca-8d4b-7a7046b0b34e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274922663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3274922663
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1558088667
Short name T1444
Test name
Test status
Simulation time 716467052 ps
CPU time 7.63 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:57:02 PM PDT 24
Peak memory 226648 kb
Host smart-d7708504-d8e8-4136-90e9-da186d43ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558088667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1558088667
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.233842853
Short name T417
Test name
Test status
Simulation time 6519207749 ps
CPU time 13.61 seconds
Started Mar 24 02:36:51 PM PDT 24
Finished Mar 24 02:37:06 PM PDT 24
Peak memory 226576 kb
Host smart-fc13809a-ab09-42be-a22a-cc6e8400c5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233842853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.233842853
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2208900687
Short name T617
Test name
Test status
Simulation time 12276653 ps
CPU time 1.22 seconds
Started Mar 24 02:36:47 PM PDT 24
Finished Mar 24 02:36:50 PM PDT 24
Peak memory 213720 kb
Host smart-cf2d99b0-25c7-41a9-b88e-2e7f95ebf5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208900687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2208900687
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.4156702396
Short name T859
Test name
Test status
Simulation time 50716707 ps
CPU time 1.35 seconds
Started Mar 24 01:56:49 PM PDT 24
Finished Mar 24 01:56:50 PM PDT 24
Peak memory 213920 kb
Host smart-02a20395-e8b2-4c29-a50c-da4e837840ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156702396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4156702396
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1172440724
Short name T861
Test name
Test status
Simulation time 151527728 ps
CPU time 25 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 251592 kb
Host smart-d8b69afd-6c77-4653-baa9-654b6e3dcf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172440724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1172440724
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1489358516
Short name T335
Test name
Test status
Simulation time 235041021 ps
CPU time 24.55 seconds
Started Mar 24 01:56:46 PM PDT 24
Finished Mar 24 01:57:11 PM PDT 24
Peak memory 251480 kb
Host smart-7a5f7f96-73e7-43cc-a918-b6dd7b34f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489358516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1489358516
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3818687516
Short name T1500
Test name
Test status
Simulation time 63019480 ps
CPU time 7.2 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:57:02 PM PDT 24
Peak memory 251492 kb
Host smart-c0130acf-5d40-4b0d-97b6-d6d6f333dd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818687516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3818687516
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.4202102747
Short name T327
Test name
Test status
Simulation time 130351337 ps
CPU time 6.19 seconds
Started Mar 24 02:36:47 PM PDT 24
Finished Mar 24 02:36:55 PM PDT 24
Peak memory 243308 kb
Host smart-866f4a5d-ed45-44b1-8f76-fbf3733e5466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202102747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.4202102747
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4016006952
Short name T798
Test name
Test status
Simulation time 10971980678 ps
CPU time 262.28 seconds
Started Mar 24 02:36:50 PM PDT 24
Finished Mar 24 02:41:15 PM PDT 24
Peak memory 277576 kb
Host smart-041b794a-e5de-485d-bd09-6767885d2eef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016006952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4016006952
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4177078163
Short name T1065
Test name
Test status
Simulation time 37339159970 ps
CPU time 192.27 seconds
Started Mar 24 01:56:57 PM PDT 24
Finished Mar 24 02:00:10 PM PDT 24
Peak memory 284288 kb
Host smart-5c873a1a-b06d-409b-8109-38c833d00490
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177078163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4177078163
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1640128882
Short name T49
Test name
Test status
Simulation time 22411091442 ps
CPU time 124.6 seconds
Started Mar 24 01:56:53 PM PDT 24
Finished Mar 24 01:58:58 PM PDT 24
Peak memory 277756 kb
Host smart-629123c3-3a99-4f17-ab56-ba4bff9fc90e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1640128882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1640128882
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3138279577
Short name T232
Test name
Test status
Simulation time 80207479490 ps
CPU time 1351.63 seconds
Started Mar 24 02:36:51 PM PDT 24
Finished Mar 24 02:59:25 PM PDT 24
Peak memory 293040 kb
Host smart-74b5688b-114c-4e7a-a0ce-fb470313fab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3138279577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3138279577
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1997453332
Short name T1184
Test name
Test status
Simulation time 17824219 ps
CPU time 1.02 seconds
Started Mar 24 02:36:46 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 212040 kb
Host smart-6af9e8e5-1435-4f4c-89a9-0f1231264539
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997453332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1997453332
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2597285989
Short name T35
Test name
Test status
Simulation time 27083904 ps
CPU time 1.11 seconds
Started Mar 24 01:56:50 PM PDT 24
Finished Mar 24 01:56:51 PM PDT 24
Peak memory 213284 kb
Host smart-7f084d1f-9488-454b-b77d-3f8490aa330f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597285989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2597285989
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1523915477
Short name T1265
Test name
Test status
Simulation time 82687273 ps
CPU time 0.98 seconds
Started Mar 24 02:36:57 PM PDT 24
Finished Mar 24 02:37:00 PM PDT 24
Peak memory 209932 kb
Host smart-8196df0f-d0f9-4c32-a0ba-b1a0bb57563e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523915477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1523915477
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3279846356
Short name T925
Test name
Test status
Simulation time 39223698 ps
CPU time 1.16 seconds
Started Mar 24 01:56:57 PM PDT 24
Finished Mar 24 01:56:58 PM PDT 24
Peak memory 209968 kb
Host smart-6b3cf68e-3931-4f15-a4a7-5d87c082870c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279846356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3279846356
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1994129446
Short name T1084
Test name
Test status
Simulation time 446353550 ps
CPU time 19.67 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 218544 kb
Host smart-91ae7ff2-870b-4cab-92d8-43fd2c94e899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994129446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1994129446
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3514528125
Short name T561
Test name
Test status
Simulation time 2053289230 ps
CPU time 5.79 seconds
Started Mar 24 02:36:49 PM PDT 24
Finished Mar 24 02:36:55 PM PDT 24
Peak memory 217388 kb
Host smart-d4eeb1ec-e54e-4bb9-967c-e21eb9504e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514528125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3514528125
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.459123655
Short name T326
Test name
Test status
Simulation time 128214484 ps
CPU time 2.28 seconds
Started Mar 24 01:56:56 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 210068 kb
Host smart-4a0a6e57-8cec-48cf-bfa5-b5110808d0ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459123655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.459123655
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3783941009
Short name T1169
Test name
Test status
Simulation time 164622538 ps
CPU time 7.17 seconds
Started Mar 24 02:36:53 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 218564 kb
Host smart-f884b439-5081-4fe3-a518-d17610e6f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783941009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3783941009
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.394147858
Short name T657
Test name
Test status
Simulation time 170739793 ps
CPU time 2.68 seconds
Started Mar 24 01:56:53 PM PDT 24
Finished Mar 24 01:56:56 PM PDT 24
Peak memory 218660 kb
Host smart-b7ebd24a-9956-4884-9e02-8332b610e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394147858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.394147858
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1555770306
Short name T488
Test name
Test status
Simulation time 735617228 ps
CPU time 16.87 seconds
Started Mar 24 02:36:56 PM PDT 24
Finished Mar 24 02:37:15 PM PDT 24
Peak memory 219492 kb
Host smart-167d9923-f7d0-4023-8c85-b900ec3a4f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555770306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1555770306
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2128058189
Short name T966
Test name
Test status
Simulation time 336517794 ps
CPU time 14.83 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:57:08 PM PDT 24
Peak memory 219528 kb
Host smart-fe3822e0-61ec-4dd2-8c65-29f0eb97235f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128058189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2128058189
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1647288772
Short name T936
Test name
Test status
Simulation time 5475285396 ps
CPU time 8.22 seconds
Started Mar 24 02:36:54 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 218640 kb
Host smart-8f3dfa24-b6dc-4465-b1c4-cb6ad55dab87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647288772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1647288772
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.312178944
Short name T1697
Test name
Test status
Simulation time 792740396 ps
CPU time 9.06 seconds
Started Mar 24 01:57:01 PM PDT 24
Finished Mar 24 01:57:10 PM PDT 24
Peak memory 218584 kb
Host smart-0adb59f6-e0f7-424b-9d9e-ca687bdab337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312178944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.312178944
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.790288869
Short name T1435
Test name
Test status
Simulation time 720784367 ps
CPU time 7.43 seconds
Started Mar 24 02:36:55 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 218588 kb
Host smart-864e5d63-2a5f-414f-9393-40b8a2a13dce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790288869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.790288869
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2700474856
Short name T562
Test name
Test status
Simulation time 372703024 ps
CPU time 14.98 seconds
Started Mar 24 02:36:50 PM PDT 24
Finished Mar 24 02:37:08 PM PDT 24
Peak memory 225408 kb
Host smart-4d4ee6d6-f1b1-43cf-a5e8-bd887ec6f9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700474856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2700474856
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3992007119
Short name T1345
Test name
Test status
Simulation time 1011090375 ps
CPU time 7.7 seconds
Started Mar 24 01:56:53 PM PDT 24
Finished Mar 24 01:57:01 PM PDT 24
Peak memory 226696 kb
Host smart-9873c68a-65e3-40ba-9442-71aea38eab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992007119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3992007119
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1903899454
Short name T902
Test name
Test status
Simulation time 206922059 ps
CPU time 3.35 seconds
Started Mar 24 01:56:56 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 218216 kb
Host smart-a1ecd69d-1fb8-4234-ace2-0edd062b84df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903899454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1903899454
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2521474642
Short name T72
Test name
Test status
Simulation time 661411602 ps
CPU time 5.61 seconds
Started Mar 24 02:36:51 PM PDT 24
Finished Mar 24 02:36:58 PM PDT 24
Peak memory 218224 kb
Host smart-006c1a96-463b-477b-83e2-9045eedf4b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521474642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2521474642
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.630289108
Short name T1499
Test name
Test status
Simulation time 1010904384 ps
CPU time 34.72 seconds
Started Mar 24 01:56:56 PM PDT 24
Finished Mar 24 01:57:31 PM PDT 24
Peak memory 251544 kb
Host smart-be1af127-36b8-49cb-8334-41246224bb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630289108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.630289108
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.850884112
Short name T436
Test name
Test status
Simulation time 128124295 ps
CPU time 22.84 seconds
Started Mar 24 02:36:51 PM PDT 24
Finished Mar 24 02:37:16 PM PDT 24
Peak memory 251432 kb
Host smart-374d1cbf-458e-4e6b-b178-8f4ec549de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850884112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.850884112
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1241173831
Short name T723
Test name
Test status
Simulation time 65529685 ps
CPU time 9.25 seconds
Started Mar 24 02:36:49 PM PDT 24
Finished Mar 24 02:37:01 PM PDT 24
Peak memory 251432 kb
Host smart-229e2d46-93bb-4652-bbb3-771e3de53bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241173831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1241173831
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3424700537
Short name T1497
Test name
Test status
Simulation time 102965399 ps
CPU time 3.58 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 222848 kb
Host smart-c84808dc-cea8-40a9-b1da-1264f9c6137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424700537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3424700537
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3748930077
Short name T225
Test name
Test status
Simulation time 5099786635 ps
CPU time 31.22 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 251528 kb
Host smart-682c7197-e31c-4845-92b0-6c8136d721bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748930077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3748930077
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.943627551
Short name T521
Test name
Test status
Simulation time 6917928184 ps
CPU time 136.8 seconds
Started Mar 24 02:36:55 PM PDT 24
Finished Mar 24 02:39:15 PM PDT 24
Peak memory 276812 kb
Host smart-3973231b-f38a-4d9b-9e46-b40a8d767b33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943627551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.943627551
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2516943090
Short name T1595
Test name
Test status
Simulation time 17780435636 ps
CPU time 168.84 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:59:43 PM PDT 24
Peak memory 333564 kb
Host smart-44314b1a-2a50-4503-8102-abc7cc1256a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2516943090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2516943090
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2980163849
Short name T621
Test name
Test status
Simulation time 37992492735 ps
CPU time 213.65 seconds
Started Mar 24 02:36:56 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 284752 kb
Host smart-1d94f167-f7ec-474e-aa37-0c8bd20dcc63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2980163849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2980163849
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1098639443
Short name T535
Test name
Test status
Simulation time 18400408 ps
CPU time 1.13 seconds
Started Mar 24 02:36:50 PM PDT 24
Finished Mar 24 02:36:54 PM PDT 24
Peak memory 213244 kb
Host smart-a7a2e018-04b7-4a53-b284-0570fc2b70db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098639443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1098639443
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.182464889
Short name T428
Test name
Test status
Simulation time 39506365 ps
CPU time 0.79 seconds
Started Mar 24 01:56:54 PM PDT 24
Finished Mar 24 01:56:55 PM PDT 24
Peak memory 209016 kb
Host smart-f381744a-368a-45ed-b4d6-114fbf60a646
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182464889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.182464889
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2805422542
Short name T349
Test name
Test status
Simulation time 18106147 ps
CPU time 0.87 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:01 PM PDT 24
Peak memory 209932 kb
Host smart-3455a935-7d88-428d-8f87-d55b06ca24f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805422542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2805422542
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3213837585
Short name T1616
Test name
Test status
Simulation time 64029217 ps
CPU time 0.95 seconds
Started Mar 24 02:37:02 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 210188 kb
Host smart-91d61cc9-8982-479f-970a-3691c2915280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213837585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3213837585
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.161157738
Short name T1253
Test name
Test status
Simulation time 3312939348 ps
CPU time 10.57 seconds
Started Mar 24 02:36:57 PM PDT 24
Finished Mar 24 02:37:09 PM PDT 24
Peak memory 218628 kb
Host smart-f250e9ca-9c25-418b-8491-f362531621c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161157738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.161157738
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.742245412
Short name T1026
Test name
Test status
Simulation time 989632568 ps
CPU time 14.84 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 218556 kb
Host smart-d8595efa-9e2f-4503-9377-bca41c19e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742245412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.742245412
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1621599134
Short name T1089
Test name
Test status
Simulation time 1175163828 ps
CPU time 5.33 seconds
Started Mar 24 02:36:56 PM PDT 24
Finished Mar 24 02:37:03 PM PDT 24
Peak memory 210040 kb
Host smart-81252ba7-96c4-449e-b170-a9b2b6c90d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621599134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1621599134
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.4148535227
Short name T666
Test name
Test status
Simulation time 2386325401 ps
CPU time 5.31 seconds
Started Mar 24 01:56:58 PM PDT 24
Finished Mar 24 01:57:03 PM PDT 24
Peak memory 210104 kb
Host smart-fb4424a0-7edd-43ff-afa0-06cbeade462b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148535227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4148535227
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1436012134
Short name T1700
Test name
Test status
Simulation time 87402874 ps
CPU time 3.47 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:03 PM PDT 24
Peak memory 222740 kb
Host smart-33eb7e27-5932-49aa-a5f0-9f8e6b657e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436012134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1436012134
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3793802699
Short name T1135
Test name
Test status
Simulation time 138654127 ps
CPU time 2.17 seconds
Started Mar 24 02:36:58 PM PDT 24
Finished Mar 24 02:37:01 PM PDT 24
Peak memory 222248 kb
Host smart-f32a9821-e11c-4380-a34a-defc75e539d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793802699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3793802699
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.152427918
Short name T1539
Test name
Test status
Simulation time 2070992889 ps
CPU time 17.16 seconds
Started Mar 24 02:36:54 PM PDT 24
Finished Mar 24 02:37:14 PM PDT 24
Peak memory 219496 kb
Host smart-e40eb8ef-ce99-41b6-a267-fc72bee21d0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152427918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.152427918
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3789409568
Short name T1378
Test name
Test status
Simulation time 1173290618 ps
CPU time 15.73 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:16 PM PDT 24
Peak memory 219520 kb
Host smart-154e0f97-f7ec-4a0f-bfd8-8cdf24878652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789409568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3789409568
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1030538183
Short name T187
Test name
Test status
Simulation time 2579739859 ps
CPU time 12.84 seconds
Started Mar 24 01:56:58 PM PDT 24
Finished Mar 24 01:57:11 PM PDT 24
Peak memory 218636 kb
Host smart-27cedec9-2c6f-498f-83e1-842ee80c4f71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030538183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1030538183
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3466958507
Short name T1102
Test name
Test status
Simulation time 1055071378 ps
CPU time 7.83 seconds
Started Mar 24 02:37:02 PM PDT 24
Finished Mar 24 02:37:11 PM PDT 24
Peak memory 218576 kb
Host smart-5cac0326-7682-4f11-8d90-56bdc591337f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466958507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3466958507
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1235817791
Short name T967
Test name
Test status
Simulation time 1138415336 ps
CPU time 10.87 seconds
Started Mar 24 01:57:01 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 218592 kb
Host smart-b041bada-04ae-4349-bceb-3a067b8cf49d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235817791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1235817791
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2527595696
Short name T815
Test name
Test status
Simulation time 548837572 ps
CPU time 7.25 seconds
Started Mar 24 02:36:55 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 218784 kb
Host smart-d6af5826-d0bd-491a-b7ea-ec2be8d446d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527595696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2527595696
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.161933180
Short name T1681
Test name
Test status
Simulation time 559444127 ps
CPU time 11.75 seconds
Started Mar 24 02:36:56 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 226564 kb
Host smart-d5bc0405-8c07-4c56-ac07-d445bece38f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161933180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.161933180
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.182521686
Short name T1284
Test name
Test status
Simulation time 2108050917 ps
CPU time 7.05 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:07 PM PDT 24
Peak memory 225304 kb
Host smart-996ebbaf-6a7a-4f54-95a0-1d7c032d2879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182521686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.182521686
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2482944845
Short name T614
Test name
Test status
Simulation time 85553481 ps
CPU time 1.68 seconds
Started Mar 24 01:57:01 PM PDT 24
Finished Mar 24 01:57:03 PM PDT 24
Peak memory 218256 kb
Host smart-f86bd98f-af31-4810-8a62-c65f1ff78edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482944845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2482944845
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3699197430
Short name T331
Test name
Test status
Simulation time 327989028 ps
CPU time 3.03 seconds
Started Mar 24 02:36:58 PM PDT 24
Finished Mar 24 02:37:02 PM PDT 24
Peak memory 218248 kb
Host smart-f4e52882-5ad0-4b7f-b9a9-d5ee4d4b7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699197430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3699197430
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1539980020
Short name T341
Test name
Test status
Simulation time 1499121145 ps
CPU time 30.44 seconds
Started Mar 24 02:37:02 PM PDT 24
Finished Mar 24 02:37:33 PM PDT 24
Peak memory 251432 kb
Host smart-45c66a8f-1de5-43f6-a5ca-2e2c3f96e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539980020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1539980020
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3805011674
Short name T639
Test name
Test status
Simulation time 297911524 ps
CPU time 29.44 seconds
Started Mar 24 01:56:53 PM PDT 24
Finished Mar 24 01:57:23 PM PDT 24
Peak memory 251464 kb
Host smart-52e6f195-f726-4c1f-a391-32dea48e8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805011674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3805011674
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1291895633
Short name T946
Test name
Test status
Simulation time 482154880 ps
CPU time 7.69 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:11 PM PDT 24
Peak memory 247116 kb
Host smart-841f6a5c-84f2-4f68-82bc-2f39a56f05c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291895633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1291895633
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2828170389
Short name T1375
Test name
Test status
Simulation time 174013686 ps
CPU time 8.35 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:57:04 PM PDT 24
Peak memory 243304 kb
Host smart-8aa36035-2041-4d5a-83f0-59318840a2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828170389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2828170389
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2282468487
Short name T472
Test name
Test status
Simulation time 11822649311 ps
CPU time 46.84 seconds
Started Mar 24 02:36:53 PM PDT 24
Finished Mar 24 02:37:44 PM PDT 24
Peak memory 226720 kb
Host smart-10186d3c-60cd-4afc-ae9c-7b66cd69d395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282468487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2282468487
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3524455976
Short name T1291
Test name
Test status
Simulation time 6776032450 ps
CPU time 118.29 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:58:58 PM PDT 24
Peak memory 226716 kb
Host smart-647db6a6-c43e-4a1c-8486-8c6c6e163a3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524455976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3524455976
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3093269318
Short name T196
Test name
Test status
Simulation time 187417230372 ps
CPU time 1293.94 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 02:18:33 PM PDT 24
Peak memory 694076 kb
Host smart-7500980d-42b0-4498-8b00-11e410b24828
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3093269318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3093269318
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1818309665
Short name T660
Test name
Test status
Simulation time 25049952 ps
CPU time 0.97 seconds
Started Mar 24 02:36:59 PM PDT 24
Finished Mar 24 02:37:00 PM PDT 24
Peak memory 212252 kb
Host smart-c80cd94e-bfe3-4035-b663-6123e3a861cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818309665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1818309665
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.919372081
Short name T768
Test name
Test status
Simulation time 18885760 ps
CPU time 1.3 seconds
Started Mar 24 01:56:55 PM PDT 24
Finished Mar 24 01:56:56 PM PDT 24
Peak memory 213264 kb
Host smart-91bc0a9e-94c9-4087-89ed-1373ad8143b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919372081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.919372081
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1879609146
Short name T558
Test name
Test status
Simulation time 73884884 ps
CPU time 0.91 seconds
Started Mar 24 02:35:05 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 209948 kb
Host smart-cda51765-5041-4dc1-9551-5869eb912a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879609146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1879609146
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.507349216
Short name T1279
Test name
Test status
Simulation time 15043013 ps
CPU time 0.88 seconds
Started Mar 24 01:54:54 PM PDT 24
Finished Mar 24 01:54:55 PM PDT 24
Peak memory 209936 kb
Host smart-467ed426-b81f-4858-b326-753e24defaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507349216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.507349216
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3576398576
Short name T270
Test name
Test status
Simulation time 11398104 ps
CPU time 0.82 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 209868 kb
Host smart-a571631a-870c-497b-94f5-5f3b684c3f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576398576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3576398576
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3430541935
Short name T678
Test name
Test status
Simulation time 275918653 ps
CPU time 12.11 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:35:05 PM PDT 24
Peak memory 218564 kb
Host smart-bff72c65-7f78-458a-ab68-26eb9bd3285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430541935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3430541935
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3878986644
Short name T516
Test name
Test status
Simulation time 565461323 ps
CPU time 11.85 seconds
Started Mar 24 01:54:54 PM PDT 24
Finished Mar 24 01:55:06 PM PDT 24
Peak memory 218528 kb
Host smart-9e539cd8-7a1f-46d8-840a-b1050cd24f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878986644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3878986644
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1640611972
Short name T1494
Test name
Test status
Simulation time 154137979 ps
CPU time 2.47 seconds
Started Mar 24 02:34:52 PM PDT 24
Finished Mar 24 02:34:55 PM PDT 24
Peak memory 210032 kb
Host smart-754d1ebb-384c-4fb7-a78b-f219af627e64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640611972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1640611972
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.935994326
Short name T1632
Test name
Test status
Simulation time 1195900773 ps
CPU time 4.2 seconds
Started Mar 24 01:54:54 PM PDT 24
Finished Mar 24 01:54:58 PM PDT 24
Peak memory 209992 kb
Host smart-438973a1-d507-4b92-86a8-895672802ea5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935994326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.935994326
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2561114616
Short name T697
Test name
Test status
Simulation time 17582728742 ps
CPU time 45.72 seconds
Started Mar 24 02:34:53 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 219468 kb
Host smart-714f9698-5fe4-4d3e-abcc-72f5d245282c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561114616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2561114616
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3725414822
Short name T396
Test name
Test status
Simulation time 5819252262 ps
CPU time 23.24 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:55:14 PM PDT 24
Peak memory 218988 kb
Host smart-3b903bd2-e28f-47ea-bbb9-d440ce04897f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725414822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3725414822
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2158602027
Short name T1054
Test name
Test status
Simulation time 1825467956 ps
CPU time 11.43 seconds
Started Mar 24 01:54:49 PM PDT 24
Finished Mar 24 01:55:01 PM PDT 24
Peak memory 217688 kb
Host smart-0f657ff3-8054-46b7-8280-41fe6b0827ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158602027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
158602027
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.4038236655
Short name T394
Test name
Test status
Simulation time 831482863 ps
CPU time 2.88 seconds
Started Mar 24 02:34:57 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 217560 kb
Host smart-2f701bff-68e3-43a3-83d4-9d73747b708d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038236655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.4
038236655
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2226108903
Short name T746
Test name
Test status
Simulation time 1162717667 ps
CPU time 5.36 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:04 PM PDT 24
Peak memory 218520 kb
Host smart-387a692e-bb3b-4604-bbbb-a14885d5352e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226108903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2226108903
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4181972415
Short name T664
Test name
Test status
Simulation time 826298497 ps
CPU time 12.85 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 218560 kb
Host smart-24a8c324-8dac-4b77-a9a0-922c5f10e47f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181972415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4181972415
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2257719773
Short name T589
Test name
Test status
Simulation time 11188842433 ps
CPU time 35.71 seconds
Started Mar 24 02:34:59 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 214512 kb
Host smart-7311a2d4-fa51-49c8-a040-a8a62418568c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257719773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2257719773
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.729665195
Short name T474
Test name
Test status
Simulation time 1205496536 ps
CPU time 17.45 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:55:12 PM PDT 24
Peak memory 213784 kb
Host smart-23a226de-73fb-4e0b-91ce-27aeae624cd6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729665195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.729665195
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2038096580
Short name T1362
Test name
Test status
Simulation time 1824717710 ps
CPU time 10.21 seconds
Started Mar 24 02:34:50 PM PDT 24
Finished Mar 24 02:35:03 PM PDT 24
Peak memory 214304 kb
Host smart-c38b43fc-4d25-42d0-b16c-4eaae8b91a8b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038096580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2038096580
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3408881744
Short name T85
Test name
Test status
Simulation time 656063918 ps
CPU time 9.12 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:55:00 PM PDT 24
Peak memory 214012 kb
Host smart-afa49aec-696c-4594-9933-612743e9846a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408881744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3408881744
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2061382283
Short name T1120
Test name
Test status
Simulation time 1772301992 ps
CPU time 35.91 seconds
Started Mar 24 02:34:57 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 251376 kb
Host smart-e0d8b443-546a-410f-a5f2-ad23db9a457f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061382283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2061382283
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3290085504
Short name T1222
Test name
Test status
Simulation time 1448941848 ps
CPU time 45.05 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:55:40 PM PDT 24
Peak memory 267848 kb
Host smart-0add9217-c517-480c-a4a9-0eee1f09a01c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290085504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3290085504
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.100405218
Short name T1446
Test name
Test status
Simulation time 704757055 ps
CPU time 27.39 seconds
Started Mar 24 02:34:57 PM PDT 24
Finished Mar 24 02:35:24 PM PDT 24
Peak memory 251440 kb
Host smart-51467c32-4ea9-4161-a3d4-a6f2c1dedd9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100405218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.100405218
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3712358318
Short name T1589
Test name
Test status
Simulation time 507194197 ps
CPU time 11.22 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 251416 kb
Host smart-f068677c-37ea-4101-8d1c-02690a7ca1b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712358318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3712358318
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1533768762
Short name T986
Test name
Test status
Simulation time 79921109 ps
CPU time 3.02 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:01 PM PDT 24
Peak memory 218564 kb
Host smart-20b02618-e02b-4562-8581-44df709c212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533768762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1533768762
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3376060390
Short name T1577
Test name
Test status
Simulation time 414410356 ps
CPU time 5.09 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 222652 kb
Host smart-2d8b30b4-2a8b-49a1-9891-ca4da4e41fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376060390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3376060390
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1869627782
Short name T233
Test name
Test status
Simulation time 511850606 ps
CPU time 18.01 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 214296 kb
Host smart-9ed2b311-e7e1-4fe1-a30e-af8a265aa3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869627782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1869627782
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3654243607
Short name T1383
Test name
Test status
Simulation time 2679375228 ps
CPU time 11.1 seconds
Started Mar 24 02:34:53 PM PDT 24
Finished Mar 24 02:35:04 PM PDT 24
Peak memory 215304 kb
Host smart-21dc8781-32ec-414b-8fbf-46eb92714dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654243607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3654243607
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1447464150
Short name T59
Test name
Test status
Simulation time 855046426 ps
CPU time 24.28 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 284532 kb
Host smart-4625fcea-b985-48a5-831e-ef211a568f65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447464150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1447464150
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3410508092
Short name T118
Test name
Test status
Simulation time 444514345 ps
CPU time 23.96 seconds
Started Mar 24 01:54:57 PM PDT 24
Finished Mar 24 01:55:21 PM PDT 24
Peak memory 284684 kb
Host smart-b42ab6b4-907b-4b32-8838-0ec7ec6bf1eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410508092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3410508092
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1333602211
Short name T1117
Test name
Test status
Simulation time 1140668629 ps
CPU time 12.5 seconds
Started Mar 24 02:35:15 PM PDT 24
Finished Mar 24 02:35:28 PM PDT 24
Peak memory 219484 kb
Host smart-6db95ee6-8e10-4381-bb4a-569243a0fc81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333602211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1333602211
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1494378069
Short name T1702
Test name
Test status
Simulation time 1092367215 ps
CPU time 18.1 seconds
Started Mar 24 01:54:49 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 219512 kb
Host smart-0102e127-bd98-485d-b869-f5c42d800b32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494378069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1494378069
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1150470982
Short name T340
Test name
Test status
Simulation time 483729847 ps
CPU time 8.62 seconds
Started Mar 24 01:54:52 PM PDT 24
Finished Mar 24 01:55:01 PM PDT 24
Peak memory 218620 kb
Host smart-a611b71a-4fc8-4362-bf17-1aa61b64d405
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150470982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1150470982
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3238943639
Short name T1101
Test name
Test status
Simulation time 1510598052 ps
CPU time 15.83 seconds
Started Mar 24 02:34:56 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 218876 kb
Host smart-7314b971-4d47-46cf-a5e3-10361b47abc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238943639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3238943639
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1279011287
Short name T1254
Test name
Test status
Simulation time 2653260603 ps
CPU time 19.1 seconds
Started Mar 24 01:54:51 PM PDT 24
Finished Mar 24 01:55:10 PM PDT 24
Peak memory 218532 kb
Host smart-01a13f29-4bb9-4e29-9504-84f032295538
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279011287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
279011287
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2153454175
Short name T399
Test name
Test status
Simulation time 1412357195 ps
CPU time 9.14 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:07 PM PDT 24
Peak memory 218592 kb
Host smart-a1d9ed7a-eba7-41f2-92fb-2cbc31cdb1c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153454175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
153454175
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3350978508
Short name T688
Test name
Test status
Simulation time 1054819707 ps
CPU time 10.56 seconds
Started Mar 24 02:34:51 PM PDT 24
Finished Mar 24 02:35:03 PM PDT 24
Peak memory 225884 kb
Host smart-15642690-282e-4aa6-ba74-391198db33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350978508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3350978508
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.809973362
Short name T1097
Test name
Test status
Simulation time 445988134 ps
CPU time 8.95 seconds
Started Mar 24 01:54:49 PM PDT 24
Finished Mar 24 01:54:58 PM PDT 24
Peak memory 226624 kb
Host smart-c45c54bc-6535-4f03-a026-1e70ae90ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809973362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.809973362
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2427825665
Short name T1360
Test name
Test status
Simulation time 109848554 ps
CPU time 2.14 seconds
Started Mar 24 01:54:53 PM PDT 24
Finished Mar 24 01:54:55 PM PDT 24
Peak memory 218232 kb
Host smart-810d2cff-0d44-42de-9508-b90cfc1af6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427825665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2427825665
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3074655682
Short name T1112
Test name
Test status
Simulation time 88945882 ps
CPU time 3.01 seconds
Started Mar 24 02:34:53 PM PDT 24
Finished Mar 24 02:34:56 PM PDT 24
Peak memory 214996 kb
Host smart-3e396187-8a10-44b1-9891-1abcd694d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074655682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3074655682
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1663442466
Short name T1661
Test name
Test status
Simulation time 557427280 ps
CPU time 28.72 seconds
Started Mar 24 01:54:53 PM PDT 24
Finished Mar 24 01:55:22 PM PDT 24
Peak memory 251328 kb
Host smart-fde6e1f0-ffbe-43b8-a2a6-8fa25c4dc69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663442466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1663442466
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1801989049
Short name T1648
Test name
Test status
Simulation time 189549357 ps
CPU time 22.41 seconds
Started Mar 24 02:34:55 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 251516 kb
Host smart-d0db3731-6401-4b8c-b5de-75f66842b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801989049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1801989049
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3515238955
Short name T752
Test name
Test status
Simulation time 91725427 ps
CPU time 3.1 seconds
Started Mar 24 02:34:54 PM PDT 24
Finished Mar 24 02:34:57 PM PDT 24
Peak memory 224236 kb
Host smart-51927913-19ca-441f-833e-310fb2116162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515238955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3515238955
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.4268296409
Short name T968
Test name
Test status
Simulation time 225075693 ps
CPU time 7.49 seconds
Started Mar 24 01:54:52 PM PDT 24
Finished Mar 24 01:54:59 PM PDT 24
Peak memory 251492 kb
Host smart-fb0d2509-71db-4d66-949d-088f2fdd08d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268296409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.4268296409
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3672849377
Short name T1359
Test name
Test status
Simulation time 10000337938 ps
CPU time 202.54 seconds
Started Mar 24 02:34:55 PM PDT 24
Finished Mar 24 02:38:17 PM PDT 24
Peak memory 281816 kb
Host smart-b318d1fe-bac4-4055-a0bb-1140b4492e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672849377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3672849377
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.821092267
Short name T481
Test name
Test status
Simulation time 7715447214 ps
CPU time 147.89 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:57:18 PM PDT 24
Peak memory 284176 kb
Host smart-ab94e964-860e-42e0-9399-a77171a6900b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821092267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.821092267
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2155845899
Short name T40
Test name
Test status
Simulation time 12373511 ps
CPU time 0.82 seconds
Started Mar 24 01:54:50 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 208920 kb
Host smart-d6b832d3-840e-4c0a-8e08-d760c5f447b1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155845899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2155845899
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3414314137
Short name T373
Test name
Test status
Simulation time 32021463 ps
CPU time 0.85 seconds
Started Mar 24 02:34:59 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 209068 kb
Host smart-df50b425-550d-4bc9-a3d2-945ef9fb579d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414314137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3414314137
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3059061914
Short name T1403
Test name
Test status
Simulation time 84029114 ps
CPU time 1.18 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 209984 kb
Host smart-da00ce69-859b-48c0-b6a0-96820c5a550e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059061914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3059061914
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.817487090
Short name T1341
Test name
Test status
Simulation time 14690898 ps
CPU time 1.07 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:06 PM PDT 24
Peak memory 209960 kb
Host smart-de32cd13-9aee-4eb3-b2b3-eda58ea23cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817487090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.817487090
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2293701562
Short name T1319
Test name
Test status
Simulation time 543521394 ps
CPU time 12.67 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:16 PM PDT 24
Peak memory 226612 kb
Host smart-805b990d-3da9-4226-a9b0-0d1c447798de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293701562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2293701562
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4178731980
Short name T654
Test name
Test status
Simulation time 207477806 ps
CPU time 8 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:08 PM PDT 24
Peak memory 218488 kb
Host smart-33bcab3b-4a79-4abb-bab4-aed630ecc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178731980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4178731980
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1037992766
Short name T940
Test name
Test status
Simulation time 750774735 ps
CPU time 2.46 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:06 PM PDT 24
Peak memory 209968 kb
Host smart-7ecd4ac2-1647-4289-95a7-d029b8ca9b38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037992766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1037992766
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.750275325
Short name T806
Test name
Test status
Simulation time 1083048006 ps
CPU time 14.51 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 208980 kb
Host smart-594d7b7b-6fcc-42b2-a13f-8b9483c65e9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750275325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.750275325
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2791030792
Short name T1547
Test name
Test status
Simulation time 42239917 ps
CPU time 2.31 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:02 PM PDT 24
Peak memory 218872 kb
Host smart-c8484f79-4e6e-43e9-b803-84700049e898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791030792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2791030792
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.448153117
Short name T426
Test name
Test status
Simulation time 687177007 ps
CPU time 4.29 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:07 PM PDT 24
Peak memory 222660 kb
Host smart-f7b86c8f-3bb1-4229-bdb6-d59296afa870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448153117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.448153117
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1872155884
Short name T1477
Test name
Test status
Simulation time 351568733 ps
CPU time 15.17 seconds
Started Mar 24 02:37:00 PM PDT 24
Finished Mar 24 02:37:18 PM PDT 24
Peak memory 219552 kb
Host smart-80a863e2-90df-4f16-8994-334f193f24bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872155884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1872155884
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1892478262
Short name T1152
Test name
Test status
Simulation time 339804294 ps
CPU time 10.26 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:10 PM PDT 24
Peak memory 218680 kb
Host smart-5553a2a7-59f0-4b07-8ee3-3d4d8e087d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892478262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1892478262
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3194336985
Short name T883
Test name
Test status
Simulation time 536289104 ps
CPU time 10.17 seconds
Started Mar 24 01:57:02 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 218636 kb
Host smart-6ffd12e4-15ad-4007-9453-e1ac22129710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194336985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3194336985
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3753913307
Short name T385
Test name
Test status
Simulation time 2474154376 ps
CPU time 14.46 seconds
Started Mar 24 02:37:01 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 218724 kb
Host smart-8497747f-a911-40f9-8911-ea7cb6a58bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753913307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3753913307
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.177946813
Short name T1155
Test name
Test status
Simulation time 800439605 ps
CPU time 6.98 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:07 PM PDT 24
Peak memory 218572 kb
Host smart-da622255-2cad-4ef9-b884-01618cad61c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177946813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.177946813
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.34672808
Short name T65
Test name
Test status
Simulation time 1062438686 ps
CPU time 7.09 seconds
Started Mar 24 02:37:01 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 218480 kb
Host smart-201523cf-f2d9-46ba-9f5a-72a246901d9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34672808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.34672808
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2962188979
Short name T330
Test name
Test status
Simulation time 321739673 ps
CPU time 7.99 seconds
Started Mar 24 01:57:00 PM PDT 24
Finished Mar 24 01:57:09 PM PDT 24
Peak memory 224168 kb
Host smart-a4eea9fe-93d3-4820-81a8-63fd35b2f2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962188979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2962188979
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.558741260
Short name T1459
Test name
Test status
Simulation time 538789950 ps
CPU time 8.92 seconds
Started Mar 24 02:36:59 PM PDT 24
Finished Mar 24 02:37:09 PM PDT 24
Peak memory 226696 kb
Host smart-8d21f416-d54e-49a1-8a0b-0f77ca155ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558741260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.558741260
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2589929488
Short name T75
Test name
Test status
Simulation time 27003714 ps
CPU time 2.17 seconds
Started Mar 24 01:57:01 PM PDT 24
Finished Mar 24 01:57:04 PM PDT 24
Peak memory 214292 kb
Host smart-a1ed7cfe-6674-4b9a-b468-434ff82ffda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589929488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2589929488
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3860229943
Short name T788
Test name
Test status
Simulation time 99026104 ps
CPU time 1.69 seconds
Started Mar 24 02:36:55 PM PDT 24
Finished Mar 24 02:37:00 PM PDT 24
Peak memory 214132 kb
Host smart-ea382757-3a95-443a-807a-2c85d85bc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860229943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3860229943
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3337904250
Short name T803
Test name
Test status
Simulation time 386622084 ps
CPU time 24.72 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 251404 kb
Host smart-c2075733-0bc6-46fd-a050-0604b2d6605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337904250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3337904250
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.415298427
Short name T123
Test name
Test status
Simulation time 296167664 ps
CPU time 25.88 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 251496 kb
Host smart-9f556c59-5ad0-46c8-be42-2609b549e7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415298427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.415298427
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.798865260
Short name T1264
Test name
Test status
Simulation time 75738877 ps
CPU time 8.58 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 251436 kb
Host smart-4c5087cf-d902-4a29-917f-f0093ce3300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798865260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.798865260
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.92722638
Short name T809
Test name
Test status
Simulation time 172531084 ps
CPU time 8.93 seconds
Started Mar 24 01:56:59 PM PDT 24
Finished Mar 24 01:57:08 PM PDT 24
Peak memory 251496 kb
Host smart-158fe256-559c-45d3-a9cf-7a32d4d3b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92722638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.92722638
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2999065061
Short name T412
Test name
Test status
Simulation time 26537576836 ps
CPU time 120.38 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:59:05 PM PDT 24
Peak memory 276024 kb
Host smart-5da18950-fc7f-40bc-9fb2-bc35c86b0022
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999065061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2999065061
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3438074720
Short name T1680
Test name
Test status
Simulation time 5586242059 ps
CPU time 192.05 seconds
Started Mar 24 02:37:00 PM PDT 24
Finished Mar 24 02:40:13 PM PDT 24
Peak memory 284320 kb
Host smart-ecea57c2-e743-4715-96a1-78ba0aa6f556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438074720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3438074720
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2199240340
Short name T203
Test name
Test status
Simulation time 25620679 ps
CPU time 1.03 seconds
Started Mar 24 02:36:55 PM PDT 24
Finished Mar 24 02:36:59 PM PDT 24
Peak memory 211988 kb
Host smart-0a45852f-d128-4e91-b759-3db34a6e2193
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199240340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2199240340
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3245938610
Short name T1278
Test name
Test status
Simulation time 24018048 ps
CPU time 0.98 seconds
Started Mar 24 01:56:57 PM PDT 24
Finished Mar 24 01:56:59 PM PDT 24
Peak memory 209108 kb
Host smart-73385ae8-d552-4640-848a-46975f12b04c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245938610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3245938610
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1762509430
Short name T1412
Test name
Test status
Simulation time 24947119 ps
CPU time 1.25 seconds
Started Mar 24 01:57:06 PM PDT 24
Finished Mar 24 01:57:07 PM PDT 24
Peak memory 209988 kb
Host smart-d48cc85b-cffd-4476-984e-4f6b4cb7244f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762509430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1762509430
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3866263511
Short name T1635
Test name
Test status
Simulation time 64869845 ps
CPU time 1.4 seconds
Started Mar 24 02:36:58 PM PDT 24
Finished Mar 24 02:37:00 PM PDT 24
Peak memory 209980 kb
Host smart-174f2479-0936-4800-8ace-6e14550711e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866263511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3866263511
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2757457822
Short name T1187
Test name
Test status
Simulation time 4384874238 ps
CPU time 16.66 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:22 PM PDT 24
Peak memory 226600 kb
Host smart-66023804-b20c-4ef2-9f20-feace0409220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757457822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2757457822
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3788416338
Short name T1141
Test name
Test status
Simulation time 522396222 ps
CPU time 15.12 seconds
Started Mar 24 02:36:59 PM PDT 24
Finished Mar 24 02:37:14 PM PDT 24
Peak memory 218584 kb
Host smart-ac66fd9f-0420-4629-9dcd-26a4b423a7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788416338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3788416338
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1995351122
Short name T644
Test name
Test status
Simulation time 617976894 ps
CPU time 8.37 seconds
Started Mar 24 02:36:59 PM PDT 24
Finished Mar 24 02:37:08 PM PDT 24
Peak memory 209992 kb
Host smart-a9fc71a2-6e39-44cc-b6ba-6bae104484f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995351122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1995351122
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2751971023
Short name T1210
Test name
Test status
Simulation time 5019371455 ps
CPU time 29.33 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:35 PM PDT 24
Peak memory 218092 kb
Host smart-a9dd3b73-840c-4298-8248-01de6a1269cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751971023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2751971023
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.309917850
Short name T919
Test name
Test status
Simulation time 269944802 ps
CPU time 2.38 seconds
Started Mar 24 02:37:01 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 218644 kb
Host smart-d2d73cba-bffc-4c16-8559-2b9a7d8b5192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309917850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.309917850
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3796562541
Short name T700
Test name
Test status
Simulation time 147671841 ps
CPU time 2.93 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:08 PM PDT 24
Peak memory 222712 kb
Host smart-5462b2b4-8074-4685-b7f5-8ed17e3eb4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796562541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3796562541
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2152590118
Short name T625
Test name
Test status
Simulation time 1375824308 ps
CPU time 14.84 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:20 PM PDT 24
Peak memory 218568 kb
Host smart-29edec34-e49b-40a2-b33b-1724fa0a9cd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152590118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2152590118
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3027097051
Short name T960
Test name
Test status
Simulation time 675191306 ps
CPU time 14.55 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:19 PM PDT 24
Peak memory 219508 kb
Host smart-1d5a36a5-d305-47cd-ac19-477d9e0859a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027097051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3027097051
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.708434832
Short name T34
Test name
Test status
Simulation time 1474998152 ps
CPU time 9.91 seconds
Started Mar 24 01:57:04 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 218548 kb
Host smart-0848f208-f793-4f03-aaab-60adb65486e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708434832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.708434832
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.799413880
Short name T499
Test name
Test status
Simulation time 563997262 ps
CPU time 9.99 seconds
Started Mar 24 02:37:00 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 218524 kb
Host smart-f0148bba-a330-42ac-892a-21415bd63b69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799413880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.799413880
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3445014038
Short name T541
Test name
Test status
Simulation time 635824573 ps
CPU time 8.05 seconds
Started Mar 24 02:37:02 PM PDT 24
Finished Mar 24 02:37:11 PM PDT 24
Peak memory 218588 kb
Host smart-daafefe9-f97b-4e51-9c28-6f5d037031d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445014038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3445014038
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.680526052
Short name T1667
Test name
Test status
Simulation time 624414091 ps
CPU time 11.53 seconds
Started Mar 24 01:57:03 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 218568 kb
Host smart-13c0f841-9227-4ee9-a384-92204a9d1f54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680526052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.680526052
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1546050857
Short name T901
Test name
Test status
Simulation time 1112277878 ps
CPU time 12.59 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:18 PM PDT 24
Peak memory 226644 kb
Host smart-64921fbd-ca0b-4070-96ff-207e86d26ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546050857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1546050857
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3385211636
Short name T1529
Test name
Test status
Simulation time 233336700 ps
CPU time 6.34 seconds
Started Mar 24 02:37:02 PM PDT 24
Finished Mar 24 02:37:09 PM PDT 24
Peak memory 225276 kb
Host smart-9726cb1f-baf0-412a-94f1-5630de9ffdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385211636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3385211636
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1495758319
Short name T1052
Test name
Test status
Simulation time 291470726 ps
CPU time 5.18 seconds
Started Mar 24 02:37:02 PM PDT 24
Finished Mar 24 02:37:08 PM PDT 24
Peak memory 214552 kb
Host smart-66ea3e52-f102-4cf4-9c6b-c3e752bc1a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495758319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1495758319
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2120826269
Short name T73
Test name
Test status
Simulation time 161355712 ps
CPU time 2.87 seconds
Started Mar 24 01:57:10 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 214664 kb
Host smart-67341dd4-1f7a-433b-87f4-7839d9b364b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120826269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2120826269
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1945149416
Short name T1536
Test name
Test status
Simulation time 296975797 ps
CPU time 21.29 seconds
Started Mar 24 01:57:04 PM PDT 24
Finished Mar 24 01:57:26 PM PDT 24
Peak memory 251488 kb
Host smart-8a7ed3db-b7be-4435-874a-f59fa99f3908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945149416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1945149416
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.674393897
Short name T1462
Test name
Test status
Simulation time 295239609 ps
CPU time 34.04 seconds
Started Mar 24 02:37:01 PM PDT 24
Finished Mar 24 02:37:37 PM PDT 24
Peak memory 251508 kb
Host smart-33cf07d0-fa7e-485b-9478-0914a90944bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674393897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.674393897
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2055084022
Short name T1098
Test name
Test status
Simulation time 269537563 ps
CPU time 7.46 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 251500 kb
Host smart-f850e97f-b9fd-4a36-a6be-c22891b5026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055084022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2055084022
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.744473958
Short name T1571
Test name
Test status
Simulation time 162083808 ps
CPU time 7.56 seconds
Started Mar 24 02:37:01 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 248672 kb
Host smart-95329868-49c9-42b7-9110-d0f9b81daa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744473958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.744473958
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.219500763
Short name T1523
Test name
Test status
Simulation time 172231082829 ps
CPU time 216.67 seconds
Started Mar 24 02:37:00 PM PDT 24
Finished Mar 24 02:40:37 PM PDT 24
Peak memory 283800 kb
Host smart-012f6a54-9901-4ef3-b6e3-3b5913f9ca25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219500763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.219500763
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.3887870840
Short name T778
Test name
Test status
Simulation time 7822414742 ps
CPU time 145.21 seconds
Started Mar 24 01:57:04 PM PDT 24
Finished Mar 24 01:59:30 PM PDT 24
Peak memory 317120 kb
Host smart-72076694-ce69-4bd1-ba75-0462721e68ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887870840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.3887870840
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3516433273
Short name T1055
Test name
Test status
Simulation time 11228593 ps
CPU time 0.81 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 209000 kb
Host smart-42013840-7be5-4a08-9b95-0032abec3b11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516433273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3516433273
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4012883999
Short name T864
Test name
Test status
Simulation time 28890669 ps
CPU time 1 seconds
Started Mar 24 01:57:06 PM PDT 24
Finished Mar 24 01:57:07 PM PDT 24
Peak memory 212988 kb
Host smart-c0bdfa4a-ea9c-4ff4-aa43-0a664b64e2a5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012883999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.4012883999
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2500029788
Short name T741
Test name
Test status
Simulation time 30230476 ps
CPU time 0.77 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 209616 kb
Host smart-97e2ecbf-6394-4ad2-bfbf-412488d3aef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500029788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2500029788
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.936638106
Short name T1460
Test name
Test status
Simulation time 24279547 ps
CPU time 1.23 seconds
Started Mar 24 01:57:10 PM PDT 24
Finished Mar 24 01:57:11 PM PDT 24
Peak memory 209868 kb
Host smart-cc6f985f-df45-4ca7-b954-f9aa6020801a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936638106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.936638106
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2654219581
Short name T517
Test name
Test status
Simulation time 2081372016 ps
CPU time 13.15 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:19 PM PDT 24
Peak memory 218592 kb
Host smart-278f77e1-74fa-4ada-bace-369adf6591c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654219581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2654219581
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3283786541
Short name T1353
Test name
Test status
Simulation time 2014549453 ps
CPU time 8.44 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 218572 kb
Host smart-4efee434-3ccc-44f1-b9bc-97be0090062e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283786541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3283786541
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3561272949
Short name T1006
Test name
Test status
Simulation time 2151303900 ps
CPU time 6.08 seconds
Started Mar 24 01:57:08 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 210100 kb
Host smart-9b3b0adf-7792-400e-abf8-692b36f30e99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561272949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3561272949
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3646219110
Short name T668
Test name
Test status
Simulation time 904533289 ps
CPU time 12.77 seconds
Started Mar 24 02:37:07 PM PDT 24
Finished Mar 24 02:37:20 PM PDT 24
Peak memory 217580 kb
Host smart-19895657-1a20-42bf-aab1-f9f44b433e54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646219110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3646219110
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2512461677
Short name T1236
Test name
Test status
Simulation time 65422396 ps
CPU time 3.41 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:08 PM PDT 24
Peak memory 222568 kb
Host smart-73f2d7ea-49d3-4b9c-b8dd-c7b4882c0390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512461677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2512461677
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2672595600
Short name T999
Test name
Test status
Simulation time 95794577 ps
CPU time 3.66 seconds
Started Mar 24 02:37:07 PM PDT 24
Finished Mar 24 02:37:11 PM PDT 24
Peak memory 218672 kb
Host smart-bdbeca3e-9f03-4daf-a3f7-331c3cf3713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672595600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2672595600
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.709332609
Short name T302
Test name
Test status
Simulation time 411421643 ps
CPU time 19.43 seconds
Started Mar 24 02:37:06 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 219480 kb
Host smart-7a27d711-63b2-41c8-bc85-2d1d0a8f237b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709332609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.709332609
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.880126132
Short name T867
Test name
Test status
Simulation time 274535246 ps
CPU time 9.74 seconds
Started Mar 24 01:57:11 PM PDT 24
Finished Mar 24 01:57:21 PM PDT 24
Peak memory 218616 kb
Host smart-d537e06b-056e-46eb-beba-48217cfc144e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880126132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.880126132
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2503355493
Short name T718
Test name
Test status
Simulation time 1750924201 ps
CPU time 12.65 seconds
Started Mar 24 02:37:05 PM PDT 24
Finished Mar 24 02:37:18 PM PDT 24
Peak memory 218552 kb
Host smart-29c2cc40-8d73-44bd-af55-025e908310c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503355493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2503355493
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.463638106
Short name T1247
Test name
Test status
Simulation time 1902312851 ps
CPU time 8.78 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:23 PM PDT 24
Peak memory 218604 kb
Host smart-b6c8d7bd-1698-43cd-886f-b928a7506a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463638106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.463638106
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1436928785
Short name T1218
Test name
Test status
Simulation time 376378945 ps
CPU time 7.81 seconds
Started Mar 24 01:57:07 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 218568 kb
Host smart-c809b441-1d2a-447b-95ba-e650de02cdef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436928785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1436928785
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3345928483
Short name T1100
Test name
Test status
Simulation time 1269325046 ps
CPU time 12.18 seconds
Started Mar 24 02:37:06 PM PDT 24
Finished Mar 24 02:37:19 PM PDT 24
Peak memory 218584 kb
Host smart-eafdb147-feb9-4465-a1d2-1305a782c70b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345928483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3345928483
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1447191015
Short name T910
Test name
Test status
Simulation time 350471545 ps
CPU time 10.03 seconds
Started Mar 24 01:57:09 PM PDT 24
Finished Mar 24 01:57:19 PM PDT 24
Peak memory 226308 kb
Host smart-e5e19582-e6ee-462c-8063-7cd993dff742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447191015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1447191015
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.4214686199
Short name T789
Test name
Test status
Simulation time 229558024 ps
CPU time 10.09 seconds
Started Mar 24 02:37:05 PM PDT 24
Finished Mar 24 02:37:15 PM PDT 24
Peak memory 226692 kb
Host smart-529d06a7-4c76-4ca3-b647-95cbc711355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214686199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4214686199
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3240729242
Short name T80
Test name
Test status
Simulation time 122930527 ps
CPU time 2.22 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:06 PM PDT 24
Peak memory 214572 kb
Host smart-72a30aab-a885-4153-add6-fdf2dc0f5e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240729242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3240729242
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3913605648
Short name T643
Test name
Test status
Simulation time 197960577 ps
CPU time 3.09 seconds
Started Mar 24 01:57:09 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 218812 kb
Host smart-bfab9845-110e-4331-85b8-e01be62e82a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913605648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3913605648
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4058978353
Short name T480
Test name
Test status
Simulation time 392903755 ps
CPU time 30.41 seconds
Started Mar 24 01:57:09 PM PDT 24
Finished Mar 24 01:57:39 PM PDT 24
Peak memory 251608 kb
Host smart-55c4b466-c902-48a6-93d1-0e7f003940c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058978353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4058978353
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.669770114
Short name T1370
Test name
Test status
Simulation time 2945543074 ps
CPU time 21.24 seconds
Started Mar 24 02:37:00 PM PDT 24
Finished Mar 24 02:37:22 PM PDT 24
Peak memory 251536 kb
Host smart-f321194c-96ef-406d-a1e9-db545e51478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669770114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.669770114
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3768869014
Short name T1227
Test name
Test status
Simulation time 124592183 ps
CPU time 7.92 seconds
Started Mar 24 01:57:05 PM PDT 24
Finished Mar 24 01:57:13 PM PDT 24
Peak memory 251460 kb
Host smart-b8ce4d1f-fa19-4f96-8894-ea7a2d46cfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768869014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3768869014
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.691942294
Short name T1053
Test name
Test status
Simulation time 808621490 ps
CPU time 3.96 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:08 PM PDT 24
Peak memory 226920 kb
Host smart-1a960e52-8403-4968-89a5-2c992052c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691942294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.691942294
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3158231987
Short name T1558
Test name
Test status
Simulation time 5508648342 ps
CPU time 202.6 seconds
Started Mar 24 02:37:06 PM PDT 24
Finished Mar 24 02:40:30 PM PDT 24
Peak memory 283732 kb
Host smart-1e9ef71e-9668-49a3-8a81-1072489deeca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158231987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3158231987
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3673557245
Short name T738
Test name
Test status
Simulation time 18874193737 ps
CPU time 278.19 seconds
Started Mar 24 01:57:10 PM PDT 24
Finished Mar 24 02:01:49 PM PDT 24
Peak memory 271080 kb
Host smart-125f8c1c-d4fe-44c7-aa8d-a48dadda3328
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673557245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3673557245
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4213822472
Short name T210
Test name
Test status
Simulation time 180872061473 ps
CPU time 1437.31 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 03:01:02 PM PDT 24
Peak memory 464456 kb
Host smart-e7cceab6-153f-4af6-bf78-546d6f66933d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4213822472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.4213822472
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1441834219
Short name T1478
Test name
Test status
Simulation time 81554780 ps
CPU time 0.78 seconds
Started Mar 24 01:57:09 PM PDT 24
Finished Mar 24 01:57:10 PM PDT 24
Peak memory 208828 kb
Host smart-5b5bf369-7237-41c0-a20b-b5928936a543
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441834219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1441834219
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1634139707
Short name T674
Test name
Test status
Simulation time 45663353 ps
CPU time 0.76 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:05 PM PDT 24
Peak memory 208900 kb
Host smart-e865ad04-3b62-476b-8a09-94a5c85b9b51
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634139707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1634139707
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4078796414
Short name T1228
Test name
Test status
Simulation time 18329764 ps
CPU time 0.96 seconds
Started Mar 24 02:37:14 PM PDT 24
Finished Mar 24 02:37:16 PM PDT 24
Peak memory 209964 kb
Host smart-0b48aa16-b229-477c-b923-397b7cec3cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078796414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4078796414
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.4267378015
Short name T1250
Test name
Test status
Simulation time 26836082 ps
CPU time 0.85 seconds
Started Mar 24 01:57:11 PM PDT 24
Finished Mar 24 01:57:13 PM PDT 24
Peak memory 209808 kb
Host smart-756fa15f-067e-4073-bc3f-c5e5bce668c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267378015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.4267378015
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2721359006
Short name T1168
Test name
Test status
Simulation time 909904181 ps
CPU time 7.36 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:22 PM PDT 24
Peak memory 226644 kb
Host smart-39229226-78e8-4bf0-b44c-d06385480b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721359006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2721359006
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.4188000173
Short name T582
Test name
Test status
Simulation time 185840964 ps
CPU time 9.69 seconds
Started Mar 24 02:37:04 PM PDT 24
Finished Mar 24 02:37:14 PM PDT 24
Peak memory 218568 kb
Host smart-f637c268-d554-42f9-b379-2363e52543de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188000173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.4188000173
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3283088359
Short name T31
Test name
Test status
Simulation time 168314615 ps
CPU time 2.56 seconds
Started Mar 24 01:57:10 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 210308 kb
Host smart-7b377657-483b-4b91-8803-11ee573edd9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283088359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3283088359
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.820550141
Short name T1314
Test name
Test status
Simulation time 199727536 ps
CPU time 2.93 seconds
Started Mar 24 02:37:07 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 210052 kb
Host smart-af51bfbb-7e1f-4799-889d-6b6f1340341c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820550141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.820550141
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1875010960
Short name T1328
Test name
Test status
Simulation time 42698277 ps
CPU time 2.6 seconds
Started Mar 24 01:57:08 PM PDT 24
Finished Mar 24 01:57:11 PM PDT 24
Peak memory 218624 kb
Host smart-c5cbaaba-bfc3-45a9-9304-f7ad1f77a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875010960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1875010960
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.688172930
Short name T1530
Test name
Test status
Simulation time 121943007 ps
CPU time 2.45 seconds
Started Mar 24 02:37:08 PM PDT 24
Finished Mar 24 02:37:10 PM PDT 24
Peak memory 218572 kb
Host smart-684905ec-8d12-4eea-a9d9-4e9241f94695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688172930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.688172930
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1642874046
Short name T609
Test name
Test status
Simulation time 799971807 ps
CPU time 14.48 seconds
Started Mar 24 01:57:11 PM PDT 24
Finished Mar 24 01:57:26 PM PDT 24
Peak memory 219348 kb
Host smart-a2239eb4-b2b0-42ea-a452-864b52439c83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642874046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1642874046
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3126649044
Short name T1317
Test name
Test status
Simulation time 387853084 ps
CPU time 12.19 seconds
Started Mar 24 02:37:07 PM PDT 24
Finished Mar 24 02:37:19 PM PDT 24
Peak memory 219524 kb
Host smart-4b6d8369-62c7-4659-b906-6ab9867ce6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126649044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3126649044
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1195520770
Short name T553
Test name
Test status
Simulation time 2632134813 ps
CPU time 11.24 seconds
Started Mar 24 02:37:08 PM PDT 24
Finished Mar 24 02:37:20 PM PDT 24
Peak memory 218664 kb
Host smart-824e6b16-f634-4cd0-a294-631e268f6c9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195520770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1195520770
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3350469384
Short name T851
Test name
Test status
Simulation time 967829841 ps
CPU time 11.76 seconds
Started Mar 24 01:57:08 PM PDT 24
Finished Mar 24 01:57:20 PM PDT 24
Peak memory 218568 kb
Host smart-bd10e1fe-0c45-49e2-9b5a-cadeaaf8444c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350469384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3350469384
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.208567788
Short name T1650
Test name
Test status
Simulation time 515161408 ps
CPU time 9.53 seconds
Started Mar 24 01:57:10 PM PDT 24
Finished Mar 24 01:57:19 PM PDT 24
Peak memory 218548 kb
Host smart-c05fbecf-d81f-49e5-870a-81da0e665c15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208567788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.208567788
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3742138647
Short name T113
Test name
Test status
Simulation time 727797349 ps
CPU time 7.96 seconds
Started Mar 24 02:37:07 PM PDT 24
Finished Mar 24 02:37:15 PM PDT 24
Peak memory 218596 kb
Host smart-70abc292-c800-4731-aff6-2a1b07fd986f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742138647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3742138647
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1255216326
Short name T996
Test name
Test status
Simulation time 773058012 ps
CPU time 10.63 seconds
Started Mar 24 02:37:06 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 226024 kb
Host smart-bc09cd1e-ba4d-429c-9200-1adb3459de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255216326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1255216326
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.3309300555
Short name T1379
Test name
Test status
Simulation time 233821262 ps
CPU time 9.34 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:23 PM PDT 24
Peak memory 225352 kb
Host smart-e2aa0689-f413-4e38-b1d4-96f8a399a581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309300555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3309300555
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2983175907
Short name T853
Test name
Test status
Simulation time 43088725 ps
CPU time 1.72 seconds
Started Mar 24 02:37:05 PM PDT 24
Finished Mar 24 02:37:07 PM PDT 24
Peak memory 214116 kb
Host smart-a599fe8e-88b8-46dd-8568-cb9aecc0c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983175907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2983175907
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3255441104
Short name T1316
Test name
Test status
Simulation time 311588139 ps
CPU time 4.89 seconds
Started Mar 24 01:57:09 PM PDT 24
Finished Mar 24 01:57:14 PM PDT 24
Peak memory 218256 kb
Host smart-adc7e04b-d02b-4242-9006-d97915c89be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255441104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3255441104
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1685414918
Short name T1363
Test name
Test status
Simulation time 360794685 ps
CPU time 29.24 seconds
Started Mar 24 02:37:07 PM PDT 24
Finished Mar 24 02:37:36 PM PDT 24
Peak memory 251532 kb
Host smart-b79f8765-9af8-4081-bca6-d6bd09c143b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685414918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1685414918
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.354596551
Short name T1137
Test name
Test status
Simulation time 825042035 ps
CPU time 19.14 seconds
Started Mar 24 01:57:09 PM PDT 24
Finished Mar 24 01:57:28 PM PDT 24
Peak memory 251516 kb
Host smart-5bee35e3-a9be-40df-ab1a-c840672c5511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354596551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.354596551
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1104409124
Short name T1596
Test name
Test status
Simulation time 126101715 ps
CPU time 3.69 seconds
Started Mar 24 01:57:11 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 218556 kb
Host smart-2cf106ba-450f-4092-b5ab-aebb9e5bda16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104409124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1104409124
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3497199740
Short name T685
Test name
Test status
Simulation time 58191694 ps
CPU time 2.99 seconds
Started Mar 24 02:37:05 PM PDT 24
Finished Mar 24 02:37:08 PM PDT 24
Peak memory 224408 kb
Host smart-9d33f68c-90ee-4542-ad33-652737fda069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497199740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3497199740
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2018027060
Short name T932
Test name
Test status
Simulation time 3217057672 ps
CPU time 50 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:38:01 PM PDT 24
Peak memory 259720 kb
Host smart-20dcfec4-74b6-4e74-b4bd-d36a0fd42c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018027060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2018027060
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2991673889
Short name T220
Test name
Test status
Simulation time 30009475506 ps
CPU time 128.54 seconds
Started Mar 24 01:57:11 PM PDT 24
Finished Mar 24 01:59:20 PM PDT 24
Peak memory 282260 kb
Host smart-62efcd8d-09f9-437c-9678-506e9ad3bb11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991673889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2991673889
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.248173687
Short name T211
Test name
Test status
Simulation time 91215860834 ps
CPU time 946.4 seconds
Started Mar 24 01:57:10 PM PDT 24
Finished Mar 24 02:12:56 PM PDT 24
Peak memory 373540 kb
Host smart-4f31524e-5813-47cd-9aad-2cf9963e8857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=248173687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.248173687
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.172465112
Short name T1289
Test name
Test status
Simulation time 20969261 ps
CPU time 1.17 seconds
Started Mar 24 01:57:11 PM PDT 24
Finished Mar 24 01:57:12 PM PDT 24
Peak memory 213372 kb
Host smart-512bfc2c-e4b8-4f51-8c4a-b3ce7cb16d0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172465112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ct
rl_volatile_unlock_smoke.172465112
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2031423834
Short name T39
Test name
Test status
Simulation time 19100098 ps
CPU time 0.92 seconds
Started Mar 24 02:37:03 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 209004 kb
Host smart-e97ca76e-9175-4661-8fbf-67b8b4eeacad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031423834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2031423834
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1316861536
Short name T1609
Test name
Test status
Simulation time 44625450 ps
CPU time 1.08 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:16 PM PDT 24
Peak memory 210176 kb
Host smart-5435a1d6-71b2-4dbf-abe2-9ca51aa85501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316861536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1316861536
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1614390160
Short name T449
Test name
Test status
Simulation time 24295749 ps
CPU time 1.02 seconds
Started Mar 24 02:37:12 PM PDT 24
Finished Mar 24 02:37:14 PM PDT 24
Peak memory 209956 kb
Host smart-4d13f05a-1778-4a26-bbca-b6b8de786042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614390160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1614390160
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1147329510
Short name T433
Test name
Test status
Simulation time 660583711 ps
CPU time 12.52 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 218592 kb
Host smart-49702ec8-510d-4106-97ec-444542fb9cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147329510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1147329510
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3649252440
Short name T1034
Test name
Test status
Simulation time 1486218016 ps
CPU time 13.18 seconds
Started Mar 24 01:57:13 PM PDT 24
Finished Mar 24 01:57:26 PM PDT 24
Peak memory 218556 kb
Host smart-fba44a24-c305-48a7-97e8-d3418c3f01f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649252440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3649252440
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2744387519
Short name T655
Test name
Test status
Simulation time 1899067158 ps
CPU time 11.78 seconds
Started Mar 24 01:57:16 PM PDT 24
Finished Mar 24 01:57:28 PM PDT 24
Peak memory 210008 kb
Host smart-26076488-2457-468e-8b34-e536a189f863
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744387519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2744387519
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3350806765
Short name T1044
Test name
Test status
Simulation time 50035074 ps
CPU time 1.96 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:13 PM PDT 24
Peak memory 210052 kb
Host smart-ba92a325-182e-46e7-972f-6d17e6362d4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350806765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3350806765
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2914149190
Short name T1640
Test name
Test status
Simulation time 374447375 ps
CPU time 3.12 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:14 PM PDT 24
Peak memory 218624 kb
Host smart-e5cc0f9c-42d1-47c3-8bd1-73b5c681ffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914149190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2914149190
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.978367620
Short name T439
Test name
Test status
Simulation time 51763825 ps
CPU time 1.71 seconds
Started Mar 24 01:57:13 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 222200 kb
Host smart-2961d8b1-b417-45ba-808d-a2d24e710a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978367620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.978367620
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1387208708
Short name T756
Test name
Test status
Simulation time 1161361714 ps
CPU time 14.25 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 218608 kb
Host smart-10c6ad9e-a8fb-42fc-8458-35cea03d645d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387208708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1387208708
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2035566247
Short name T560
Test name
Test status
Simulation time 223325755 ps
CPU time 9.48 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 218592 kb
Host smart-1511776a-bcc2-4b8b-ae9d-1d34b533fdd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035566247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2035566247
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.429083368
Short name T805
Test name
Test status
Simulation time 2153034493 ps
CPU time 10.45 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 218552 kb
Host smart-26f9d070-05bc-4022-8f9e-5fc9b453ac24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429083368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.429083368
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.677504037
Short name T1380
Test name
Test status
Simulation time 889711275 ps
CPU time 10.57 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:20 PM PDT 24
Peak memory 218652 kb
Host smart-8e1a548f-0a1a-45d3-931e-189f81166886
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677504037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.677504037
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4089260308
Short name T939
Test name
Test status
Simulation time 1540491924 ps
CPU time 13.86 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:22 PM PDT 24
Peak memory 218504 kb
Host smart-06f66905-f7cf-440e-9b40-f99145bb72df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089260308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4089260308
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.766601306
Short name T125
Test name
Test status
Simulation time 265283558 ps
CPU time 11.53 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 218596 kb
Host smart-6458a996-fcc0-4f34-a3d7-1726a97c9142
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766601306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.766601306
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2470043854
Short name T101
Test name
Test status
Simulation time 1241635128 ps
CPU time 7.66 seconds
Started Mar 24 01:57:13 PM PDT 24
Finished Mar 24 01:57:21 PM PDT 24
Peak memory 225488 kb
Host smart-e734b0c5-28b1-4cb6-94aa-3adc7c91d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470043854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2470043854
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2877488923
Short name T355
Test name
Test status
Simulation time 618244929 ps
CPU time 11.57 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:22 PM PDT 24
Peak memory 226604 kb
Host smart-ca0832d4-e030-407e-879f-3cfcc9d650fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877488923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2877488923
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3668832468
Short name T452
Test name
Test status
Simulation time 186119453 ps
CPU time 2.87 seconds
Started Mar 24 01:57:07 PM PDT 24
Finished Mar 24 01:57:10 PM PDT 24
Peak memory 214840 kb
Host smart-6cac1858-8055-4ff2-83b7-ae737af7f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668832468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3668832468
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.83213147
Short name T490
Test name
Test status
Simulation time 84791529 ps
CPU time 2.53 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 218400 kb
Host smart-cc3e38e1-10a5-4fe8-bdb9-f6e71e23c95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83213147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.83213147
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2109950691
Short name T1095
Test name
Test status
Simulation time 343677698 ps
CPU time 19.76 seconds
Started Mar 24 02:37:08 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 251548 kb
Host smart-e0edad4e-8cd1-4c8c-b17c-558990747164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109950691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2109950691
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3251716205
Short name T301
Test name
Test status
Simulation time 3478017124 ps
CPU time 31.16 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:46 PM PDT 24
Peak memory 251536 kb
Host smart-1e174bdd-6982-4697-9075-1d7581c4aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251716205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3251716205
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2612839339
Short name T1206
Test name
Test status
Simulation time 114850332 ps
CPU time 3.11 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 226972 kb
Host smart-38e010c5-60ab-4f55-9831-869cfd6e1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612839339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2612839339
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.278903741
Short name T1170
Test name
Test status
Simulation time 84487279 ps
CPU time 3.37 seconds
Started Mar 24 01:57:13 PM PDT 24
Finished Mar 24 01:57:17 PM PDT 24
Peak memory 223060 kb
Host smart-c09c9c2e-b40d-4732-9680-6eed009ea68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278903741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.278903741
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2078803398
Short name T1190
Test name
Test status
Simulation time 32442714114 ps
CPU time 105.39 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:59:01 PM PDT 24
Peak memory 284336 kb
Host smart-20690b9e-8eed-4de4-bae2-1970dbd27689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078803398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2078803398
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3431976563
Short name T1630
Test name
Test status
Simulation time 11921869209 ps
CPU time 113.68 seconds
Started Mar 24 02:37:12 PM PDT 24
Finished Mar 24 02:39:06 PM PDT 24
Peak memory 251604 kb
Host smart-5285dfc3-71e4-4444-bd29-01758a15b8b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431976563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3431976563
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2223659544
Short name T261
Test name
Test status
Simulation time 77859455724 ps
CPU time 1119.34 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:55:51 PM PDT 24
Peak memory 644908 kb
Host smart-738f8ec1-3da5-4a14-8936-862f4f3727a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2223659544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2223659544
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3142838109
Short name T1475
Test name
Test status
Simulation time 15605777 ps
CPU time 0.97 seconds
Started Mar 24 02:37:10 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 212088 kb
Host smart-948661ca-3ec7-48ed-84d1-01e1f91296c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142838109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3142838109
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3938298850
Short name T555
Test name
Test status
Simulation time 18750919 ps
CPU time 0.8 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 208972 kb
Host smart-3088dd40-9a80-4ac0-8063-7fafb1a27f15
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938298850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3938298850
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.1574857617
Short name T1659
Test name
Test status
Simulation time 15363209 ps
CPU time 1.08 seconds
Started Mar 24 01:57:21 PM PDT 24
Finished Mar 24 01:57:22 PM PDT 24
Peak memory 209876 kb
Host smart-1da49cb2-6eb6-4255-91a7-2b1cf6c7d0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574857617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1574857617
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3611651206
Short name T328
Test name
Test status
Simulation time 15484506 ps
CPU time 1.04 seconds
Started Mar 24 02:37:16 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 209912 kb
Host smart-9808546e-c741-459a-917a-ac9a98829d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611651206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3611651206
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3224374893
Short name T1131
Test name
Test status
Simulation time 364976441 ps
CPU time 16.52 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:32 PM PDT 24
Peak memory 218596 kb
Host smart-5a0998a0-30b6-4ae5-94c0-4f7119e47a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224374893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3224374893
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3763875242
Short name T1624
Test name
Test status
Simulation time 279799125 ps
CPU time 11.12 seconds
Started Mar 24 02:37:10 PM PDT 24
Finished Mar 24 02:37:21 PM PDT 24
Peak memory 218580 kb
Host smart-cb88f609-b3e0-45a6-964b-21cc0faa2f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763875242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3763875242
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1018477769
Short name T1337
Test name
Test status
Simulation time 83370855 ps
CPU time 1.61 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:17 PM PDT 24
Peak memory 210060 kb
Host smart-2246bf53-3df8-4ce4-b4c0-8e76cf58c250
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018477769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1018477769
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.32359872
Short name T1067
Test name
Test status
Simulation time 2110246668 ps
CPU time 6.56 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 217736 kb
Host smart-f4395a05-84c3-4dd5-a884-3f4456295c91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32359872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.32359872
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3795781072
Short name T1217
Test name
Test status
Simulation time 112798528 ps
CPU time 2.57 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:16 PM PDT 24
Peak memory 222448 kb
Host smart-de2b028c-7560-4c5f-88fd-db1254e5a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795781072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3795781072
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.404791148
Short name T1136
Test name
Test status
Simulation time 152846552 ps
CPU time 4.71 seconds
Started Mar 24 02:37:10 PM PDT 24
Finished Mar 24 02:37:15 PM PDT 24
Peak memory 222852 kb
Host smart-aa38f756-07bf-4d8f-ad40-114432b57e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404791148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.404791148
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1635184431
Short name T578
Test name
Test status
Simulation time 984416577 ps
CPU time 11.14 seconds
Started Mar 24 01:57:18 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 219528 kb
Host smart-7e29b6a0-0a43-4873-94e4-1e71805cdaac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635184431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1635184431
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3439504275
Short name T1196
Test name
Test status
Simulation time 291168939 ps
CPU time 13.08 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:34 PM PDT 24
Peak memory 219712 kb
Host smart-969984de-4da0-43c3-8228-5fcbb3718bfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439504275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3439504275
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2961096330
Short name T1022
Test name
Test status
Simulation time 240601347 ps
CPU time 9.97 seconds
Started Mar 24 02:37:13 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 218480 kb
Host smart-6c2fc745-4cd2-43c0-8499-4db2cd814de5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961096330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2961096330
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.738705961
Short name T1447
Test name
Test status
Simulation time 532428822 ps
CPU time 12.42 seconds
Started Mar 24 01:57:20 PM PDT 24
Finished Mar 24 01:57:32 PM PDT 24
Peak memory 218652 kb
Host smart-d0c61f7d-f584-4ac3-8476-0ef9ad8309b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738705961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.738705961
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2905519545
Short name T1468
Test name
Test status
Simulation time 809910245 ps
CPU time 5.92 seconds
Started Mar 24 01:57:12 PM PDT 24
Finished Mar 24 01:57:18 PM PDT 24
Peak memory 218508 kb
Host smart-472b82a0-b145-49c9-b9de-928862d20d33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905519545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2905519545
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.687505035
Short name T804
Test name
Test status
Simulation time 523643264 ps
CPU time 12.01 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:33 PM PDT 24
Peak memory 218592 kb
Host smart-4b6a2493-89bc-459f-bdbc-63a53cb19bf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687505035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.687505035
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1637775018
Short name T684
Test name
Test status
Simulation time 1140205504 ps
CPU time 12.16 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:27 PM PDT 24
Peak memory 226216 kb
Host smart-c44ab273-9c0c-4115-a9f6-63b0085bde6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637775018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1637775018
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1898938020
Short name T1417
Test name
Test status
Simulation time 543117734 ps
CPU time 13.16 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:22 PM PDT 24
Peak memory 226232 kb
Host smart-e9c73bcc-41bc-4d96-a793-fbeaf75c6924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898938020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1898938020
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2853711015
Short name T1583
Test name
Test status
Simulation time 116463836 ps
CPU time 2.73 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 214412 kb
Host smart-aa810e0f-df27-4979-8720-21022f9e2a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853711015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2853711015
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3669097508
Short name T1707
Test name
Test status
Simulation time 55360965 ps
CPU time 3.64 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:18 PM PDT 24
Peak memory 218372 kb
Host smart-ef66d397-90af-48fc-83de-c1f9d507e909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669097508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3669097508
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1962574047
Short name T1354
Test name
Test status
Simulation time 1089121728 ps
CPU time 31.22 seconds
Started Mar 24 01:57:15 PM PDT 24
Finished Mar 24 01:57:47 PM PDT 24
Peak memory 251460 kb
Host smart-0b76bc78-964e-44b7-9c41-0e651672b264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962574047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1962574047
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3710929097
Short name T703
Test name
Test status
Simulation time 648440176 ps
CPU time 30.84 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 251472 kb
Host smart-091cdfcb-4007-4793-ac3f-aa5b20fcaf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710929097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3710929097
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2147434928
Short name T995
Test name
Test status
Simulation time 272905835 ps
CPU time 8.1 seconds
Started Mar 24 01:57:13 PM PDT 24
Finished Mar 24 01:57:21 PM PDT 24
Peak memory 251368 kb
Host smart-eceb0812-547a-4fde-98d5-ba5f540d5f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147434928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2147434928
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3003063135
Short name T964
Test name
Test status
Simulation time 212534245 ps
CPU time 6.21 seconds
Started Mar 24 02:37:09 PM PDT 24
Finished Mar 24 02:37:16 PM PDT 24
Peak memory 247232 kb
Host smart-93b804fd-d99a-426b-96eb-371bbdc1d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003063135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3003063135
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1666970702
Short name T47
Test name
Test status
Simulation time 2559914309 ps
CPU time 24.61 seconds
Started Mar 24 02:37:14 PM PDT 24
Finished Mar 24 02:37:39 PM PDT 24
Peak memory 227280 kb
Host smart-db791a49-d4e6-4a17-aad1-978a185f4182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666970702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1666970702
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3260424022
Short name T1602
Test name
Test status
Simulation time 8477605709 ps
CPU time 66.03 seconds
Started Mar 24 01:57:21 PM PDT 24
Finished Mar 24 01:58:27 PM PDT 24
Peak memory 249800 kb
Host smart-093bf318-dc6c-4395-b752-43b1fda814e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260424022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3260424022
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4089797392
Short name T195
Test name
Test status
Simulation time 62442812229 ps
CPU time 509.89 seconds
Started Mar 24 01:57:20 PM PDT 24
Finished Mar 24 02:05:50 PM PDT 24
Peak memory 300800 kb
Host smart-46cd9f4f-8bf0-42d7-b4f5-6f1068115f5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4089797392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4089797392
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4107101999
Short name T984
Test name
Test status
Simulation time 13633594 ps
CPU time 1.12 seconds
Started Mar 24 01:57:14 PM PDT 24
Finished Mar 24 01:57:15 PM PDT 24
Peak memory 212124 kb
Host smart-bc00db40-7281-4c6f-972f-58eb1d242ab3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107101999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4107101999
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4133113690
Short name T1524
Test name
Test status
Simulation time 14056186 ps
CPU time 1.14 seconds
Started Mar 24 02:37:11 PM PDT 24
Finished Mar 24 02:37:12 PM PDT 24
Peak memory 212128 kb
Host smart-5ca629bc-d911-43ae-a157-b6d0d4684fb6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133113690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4133113690
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1989088388
Short name T566
Test name
Test status
Simulation time 66662375 ps
CPU time 1.35 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 01:57:27 PM PDT 24
Peak memory 209956 kb
Host smart-52cc9533-7fae-40a7-897b-63c39e7ac827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989088388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1989088388
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.4206797838
Short name T763
Test name
Test status
Simulation time 37864437 ps
CPU time 0.93 seconds
Started Mar 24 02:37:16 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 210052 kb
Host smart-811dc36f-be4d-45e7-a8ec-baae883dab6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206797838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4206797838
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.42370259
Short name T1498
Test name
Test status
Simulation time 658158720 ps
CPU time 10.72 seconds
Started Mar 24 01:57:19 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 218584 kb
Host smart-3e28829d-8e1e-4b26-894a-761750e8175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42370259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.42370259
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.578706511
Short name T1610
Test name
Test status
Simulation time 1701588988 ps
CPU time 10.62 seconds
Started Mar 24 02:37:15 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 218600 kb
Host smart-7a75ce99-e799-494c-9212-28e16a9265c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578706511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.578706511
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2466886471
Short name T1414
Test name
Test status
Simulation time 2925629811 ps
CPU time 6.01 seconds
Started Mar 24 01:57:22 PM PDT 24
Finished Mar 24 01:57:28 PM PDT 24
Peak memory 210092 kb
Host smart-5ff3d59f-4ee7-44ac-be34-16e4acf85793
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466886471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2466886471
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3560008974
Short name T32
Test name
Test status
Simulation time 537451860 ps
CPU time 3.54 seconds
Started Mar 24 02:37:16 PM PDT 24
Finished Mar 24 02:37:20 PM PDT 24
Peak memory 217336 kb
Host smart-46307666-8d85-4d29-be2b-1282130e4553
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560008974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3560008974
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1797250617
Short name T1068
Test name
Test status
Simulation time 72175880 ps
CPU time 2.48 seconds
Started Mar 24 02:37:14 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 218636 kb
Host smart-e9deaa72-9387-424c-a655-de1fbaca441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797250617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1797250617
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.4010946286
Short name T602
Test name
Test status
Simulation time 48812301 ps
CPU time 1.83 seconds
Started Mar 24 01:57:21 PM PDT 24
Finished Mar 24 01:57:23 PM PDT 24
Peak memory 222160 kb
Host smart-10fc7676-9023-4925-8481-8120a57500d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010946286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.4010946286
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2961061010
Short name T66
Test name
Test status
Simulation time 521402061 ps
CPU time 10.17 seconds
Started Mar 24 01:57:21 PM PDT 24
Finished Mar 24 01:57:32 PM PDT 24
Peak memory 219544 kb
Host smart-42a4603f-d63e-46db-814f-c5d98c67f5bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961061010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2961061010
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3401727926
Short name T1063
Test name
Test status
Simulation time 573393786 ps
CPU time 12.28 seconds
Started Mar 24 02:37:14 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 219540 kb
Host smart-2613b147-f660-4b70-9b4a-3b57fc32bd85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401727926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3401727926
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2375770943
Short name T642
Test name
Test status
Simulation time 215112513 ps
CPU time 10.24 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 218660 kb
Host smart-585af986-73fb-46fc-a83a-23bdcfb7a6cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375770943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2375770943
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3912396623
Short name T951
Test name
Test status
Simulation time 285536083 ps
CPU time 13.66 seconds
Started Mar 24 01:57:21 PM PDT 24
Finished Mar 24 01:57:35 PM PDT 24
Peak memory 218568 kb
Host smart-5e23c3eb-9fa8-4839-b698-a6070961f885
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912396623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3912396623
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2224081123
Short name T1601
Test name
Test status
Simulation time 421402799 ps
CPU time 11.48 seconds
Started Mar 24 01:57:19 PM PDT 24
Finished Mar 24 01:57:31 PM PDT 24
Peak memory 218588 kb
Host smart-021495e5-f7c1-4390-b187-56d3a1accbcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224081123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2224081123
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.468162442
Short name T826
Test name
Test status
Simulation time 596815447 ps
CPU time 12.78 seconds
Started Mar 24 02:37:14 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 218572 kb
Host smart-803933fa-4e2b-44da-a6b9-2e7771e87294
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468162442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.468162442
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1938119283
Short name T520
Test name
Test status
Simulation time 847181428 ps
CPU time 7.54 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:29 PM PDT 24
Peak memory 226864 kb
Host smart-8f6c4bb5-f311-4678-97f7-fdf46ab28c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938119283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1938119283
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2423023166
Short name T207
Test name
Test status
Simulation time 1089016054 ps
CPU time 7.15 seconds
Started Mar 24 01:57:20 PM PDT 24
Finished Mar 24 01:57:28 PM PDT 24
Peak memory 224700 kb
Host smart-9ab0ccd6-1346-4d44-be97-ded3248e8a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423023166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2423023166
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.108078224
Short name T491
Test name
Test status
Simulation time 25890203 ps
CPU time 1.6 seconds
Started Mar 24 01:57:19 PM PDT 24
Finished Mar 24 01:57:21 PM PDT 24
Peak memory 218248 kb
Host smart-881ba335-5148-4189-a1d7-268873edba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108078224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.108078224
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2491584121
Short name T329
Test name
Test status
Simulation time 87786078 ps
CPU time 3.2 seconds
Started Mar 24 02:37:15 PM PDT 24
Finished Mar 24 02:37:19 PM PDT 24
Peak memory 218220 kb
Host smart-6160472d-d5e3-4dbc-80b2-13a658b5503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491584121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2491584121
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1825252757
Short name T363
Test name
Test status
Simulation time 957481609 ps
CPU time 31.72 seconds
Started Mar 24 01:57:20 PM PDT 24
Finished Mar 24 01:57:52 PM PDT 24
Peak memory 251488 kb
Host smart-ef98677f-daac-4584-a4f5-efef460179dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825252757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1825252757
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3281152477
Short name T1579
Test name
Test status
Simulation time 177944000 ps
CPU time 20.71 seconds
Started Mar 24 02:37:18 PM PDT 24
Finished Mar 24 02:37:39 PM PDT 24
Peak memory 251460 kb
Host smart-cb23b442-2720-4305-a07c-de08b5dcb3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281152477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3281152477
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3129576004
Short name T303
Test name
Test status
Simulation time 115112569 ps
CPU time 8.13 seconds
Started Mar 24 02:37:17 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 243288 kb
Host smart-580a4ccf-7628-44dd-b079-35b1e1255b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129576004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3129576004
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3266699971
Short name T928
Test name
Test status
Simulation time 73029230 ps
CPU time 3.84 seconds
Started Mar 24 01:57:22 PM PDT 24
Finished Mar 24 01:57:26 PM PDT 24
Peak memory 218484 kb
Host smart-bb95a605-2084-4d0c-86aa-23e036cd751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266699971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3266699971
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1551728680
Short name T1009
Test name
Test status
Simulation time 26194767783 ps
CPU time 104.09 seconds
Started Mar 24 01:57:19 PM PDT 24
Finished Mar 24 01:59:03 PM PDT 24
Peak memory 273212 kb
Host smart-d27a1103-cbf0-411b-9c85-5542e7e962ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551728680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1551728680
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.839607698
Short name T1456
Test name
Test status
Simulation time 18482417908 ps
CPU time 178.75 seconds
Started Mar 24 02:37:13 PM PDT 24
Finished Mar 24 02:40:12 PM PDT 24
Peak memory 251564 kb
Host smart-e7fe0097-1709-4cda-9c4a-410e810ac51c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839607698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.839607698
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.855929715
Short name T182
Test name
Test status
Simulation time 12367170859 ps
CPU time 227.85 seconds
Started Mar 24 02:37:16 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 281608 kb
Host smart-b8df1593-7720-4e51-b534-6fedcbf05d6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=855929715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.855929715
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.944339482
Short name T793
Test name
Test status
Simulation time 27738287657 ps
CPU time 645.83 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 02:08:12 PM PDT 24
Peak memory 497412 kb
Host smart-5547be83-2251-412f-aafd-d2401af08b9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=944339482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.944339482
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3976251217
Short name T765
Test name
Test status
Simulation time 69979366 ps
CPU time 0.95 seconds
Started Mar 24 02:37:16 PM PDT 24
Finished Mar 24 02:37:17 PM PDT 24
Peak memory 213116 kb
Host smart-d8fdf19d-c9cb-4edf-ac34-91387a5a918c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976251217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3976251217
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.883865784
Short name T580
Test name
Test status
Simulation time 13783498 ps
CPU time 0.93 seconds
Started Mar 24 01:57:19 PM PDT 24
Finished Mar 24 01:57:20 PM PDT 24
Peak memory 211992 kb
Host smart-64fafc72-4c32-427c-a653-cc6fc4b676d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883865784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.883865784
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1579067520
Short name T1027
Test name
Test status
Simulation time 94877426 ps
CPU time 0.98 seconds
Started Mar 24 01:57:23 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 209920 kb
Host smart-2ecfa591-7f5a-4fa7-b37e-706071babc7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579067520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1579067520
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.4049411784
Short name T498
Test name
Test status
Simulation time 78314411 ps
CPU time 0.99 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:22 PM PDT 24
Peak memory 209944 kb
Host smart-d8de3120-6026-4c13-851a-740cbe999b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049411784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4049411784
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2202298878
Short name T425
Test name
Test status
Simulation time 1484633790 ps
CPU time 11.02 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:37 PM PDT 24
Peak memory 218572 kb
Host smart-972e837d-458e-42d1-981f-98dd1585c4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202298878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2202298878
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3342715732
Short name T391
Test name
Test status
Simulation time 362351930 ps
CPU time 12.23 seconds
Started Mar 24 02:37:17 PM PDT 24
Finished Mar 24 02:37:29 PM PDT 24
Peak memory 218588 kb
Host smart-3ff81977-66dd-4b72-8031-94775c2bcb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342715732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3342715732
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2704005896
Short name T453
Test name
Test status
Simulation time 148075664 ps
CPU time 2.26 seconds
Started Mar 24 01:57:22 PM PDT 24
Finished Mar 24 01:57:25 PM PDT 24
Peak memory 210052 kb
Host smart-45678324-4bea-4c44-8c23-735e4922c046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704005896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2704005896
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2924835804
Short name T906
Test name
Test status
Simulation time 652040244 ps
CPU time 6.98 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 210016 kb
Host smart-ea7c9b38-cb14-4a05-b8c8-547fb6a887a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924835804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2924835804
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2109196169
Short name T1453
Test name
Test status
Simulation time 45683255 ps
CPU time 2.27 seconds
Started Mar 24 01:57:24 PM PDT 24
Finished Mar 24 01:57:26 PM PDT 24
Peak memory 222540 kb
Host smart-a23fb0c5-e08c-4d7e-bcc7-6989d0b1531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109196169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2109196169
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2859163827
Short name T780
Test name
Test status
Simulation time 64430180 ps
CPU time 3.2 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:25 PM PDT 24
Peak memory 222416 kb
Host smart-c67c42ae-0629-442b-a6ef-b548d94027cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859163827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2859163827
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1665426966
Short name T536
Test name
Test status
Simulation time 740905797 ps
CPU time 11.77 seconds
Started Mar 24 01:57:24 PM PDT 24
Finished Mar 24 01:57:37 PM PDT 24
Peak memory 226664 kb
Host smart-c56dc0f9-dc68-4b58-8ab4-db131009a830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665426966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1665426966
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.668866939
Short name T1198
Test name
Test status
Simulation time 838179732 ps
CPU time 23.46 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:45 PM PDT 24
Peak memory 218680 kb
Host smart-124fa36a-cb1b-4e1b-97a2-0994b7b3051e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668866939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.668866939
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2559899645
Short name T1203
Test name
Test status
Simulation time 349336070 ps
CPU time 13.45 seconds
Started Mar 24 01:57:23 PM PDT 24
Finished Mar 24 01:57:37 PM PDT 24
Peak memory 218592 kb
Host smart-2885a7cb-d44c-4a8e-8869-c07a6667ee87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559899645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2559899645
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3378647972
Short name T375
Test name
Test status
Simulation time 1060307488 ps
CPU time 9.67 seconds
Started Mar 24 02:37:22 PM PDT 24
Finished Mar 24 02:37:31 PM PDT 24
Peak memory 218552 kb
Host smart-8ce4dcc4-4662-4261-b298-f1d217e929f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378647972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3378647972
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2198347331
Short name T315
Test name
Test status
Simulation time 693034235 ps
CPU time 11.86 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:38 PM PDT 24
Peak memory 218564 kb
Host smart-85ae0099-31be-4435-b22b-ec679edc61f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198347331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2198347331
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2646076964
Short name T1552
Test name
Test status
Simulation time 277562346 ps
CPU time 6.93 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 218648 kb
Host smart-62a0a61b-d459-4958-85e2-b44052fe6fb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646076964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2646076964
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3816754417
Short name T1213
Test name
Test status
Simulation time 295664047 ps
CPU time 11.5 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:33 PM PDT 24
Peak memory 226068 kb
Host smart-b3a423e3-5a49-4e50-ac21-d5385ca2a067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816754417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3816754417
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3904040633
Short name T1191
Test name
Test status
Simulation time 1948742639 ps
CPU time 9.43 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:36 PM PDT 24
Peak memory 225472 kb
Host smart-4b7dcb67-5c47-492f-9dbd-c367301f6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904040633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3904040633
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2741646280
Short name T1400
Test name
Test status
Simulation time 137358544 ps
CPU time 3.12 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 01:57:28 PM PDT 24
Peak memory 218300 kb
Host smart-448dc3e5-53cb-437b-a8e7-bf0fe0d7c162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741646280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2741646280
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3314735605
Short name T1505
Test name
Test status
Simulation time 112784547 ps
CPU time 3.59 seconds
Started Mar 24 02:37:15 PM PDT 24
Finished Mar 24 02:37:19 PM PDT 24
Peak memory 218220 kb
Host smart-32437a32-2f83-44c9-b796-4a919d8ef7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314735605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3314735605
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2320661958
Short name T1241
Test name
Test status
Simulation time 281032551 ps
CPU time 31.21 seconds
Started Mar 24 02:37:15 PM PDT 24
Finished Mar 24 02:37:47 PM PDT 24
Peak memory 251352 kb
Host smart-02356661-e13a-4d61-8fa9-243cbf58d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320661958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2320661958
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3114056475
Short name T1199
Test name
Test status
Simulation time 4315997294 ps
CPU time 18.15 seconds
Started Mar 24 01:57:23 PM PDT 24
Finished Mar 24 01:57:42 PM PDT 24
Peak memory 251548 kb
Host smart-35242018-d970-440b-836a-6d5fd853050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114056475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3114056475
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2273409448
Short name T2
Test name
Test status
Simulation time 65282264 ps
CPU time 3.46 seconds
Started Mar 24 02:37:17 PM PDT 24
Finished Mar 24 02:37:20 PM PDT 24
Peak memory 226908 kb
Host smart-1e4fc773-1d32-4d64-93f4-4dd37476c9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273409448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2273409448
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.4040919189
Short name T206
Test name
Test status
Simulation time 18028746845 ps
CPU time 331.42 seconds
Started Mar 24 02:37:18 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 284236 kb
Host smart-e4cff956-0b6a-4707-af52-02482f26547d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040919189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.4040919189
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.889393908
Short name T183
Test name
Test status
Simulation time 12011814718 ps
CPU time 569.14 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 02:06:55 PM PDT 24
Peak memory 333584 kb
Host smart-5b0c0103-fcd7-44a6-a762-bdddc00dec00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=889393908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.889393908
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2278384156
Short name T1031
Test name
Test status
Simulation time 38990348 ps
CPU time 0.98 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:20 PM PDT 24
Peak memory 212072 kb
Host smart-80b0b4c2-e6ef-4613-a32f-b3ad339f9831
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278384156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2278384156
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2541108918
Short name T1373
Test name
Test status
Simulation time 11611692 ps
CPU time 0.78 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 01:57:26 PM PDT 24
Peak memory 208548 kb
Host smart-58c89892-b0fc-4f7c-8eb6-76236bf71645
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541108918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2541108918
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3899692948
Short name T1252
Test name
Test status
Simulation time 62026629 ps
CPU time 0.95 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 210172 kb
Host smart-56562337-d47c-4ad8-b73c-62bcfd3747ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899692948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3899692948
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1297316308
Short name T656
Test name
Test status
Simulation time 349877912 ps
CPU time 15.56 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:42 PM PDT 24
Peak memory 218576 kb
Host smart-e5ac4b1f-9a9b-4fb7-8f5b-9a22630988e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297316308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1297316308
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1879337633
Short name T681
Test name
Test status
Simulation time 1663784358 ps
CPU time 13.91 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:35 PM PDT 24
Peak memory 218508 kb
Host smart-829b4580-c0a9-48b0-bd11-2976d3f3ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879337633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1879337633
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2510945341
Short name T1004
Test name
Test status
Simulation time 306356924 ps
CPU time 7.9 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:29 PM PDT 24
Peak memory 210020 kb
Host smart-be3ef576-80d9-4768-9935-254c6644ae03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510945341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2510945341
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2919619028
Short name T495
Test name
Test status
Simulation time 703557707 ps
CPU time 4.92 seconds
Started Mar 24 01:57:24 PM PDT 24
Finished Mar 24 01:57:29 PM PDT 24
Peak memory 217652 kb
Host smart-9a8557e6-ccd3-49ff-95f2-5fdcbed56d38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919619028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2919619028
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2387531207
Short name T279
Test name
Test status
Simulation time 371474034 ps
CPU time 3.48 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 222788 kb
Host smart-7af22656-109f-452d-bee1-29d6397245db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387531207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2387531207
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3695905408
Short name T283
Test name
Test status
Simulation time 330930917 ps
CPU time 2.15 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 222180 kb
Host smart-b870e09c-c41d-4136-b0c4-408b0ebba0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695905408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3695905408
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3505232657
Short name T1266
Test name
Test status
Simulation time 221964147 ps
CPU time 7.93 seconds
Started Mar 24 01:57:28 PM PDT 24
Finished Mar 24 01:57:36 PM PDT 24
Peak memory 218480 kb
Host smart-b0afbba1-28fb-4dab-b5f3-097785d6eaa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505232657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3505232657
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3767635456
Short name T309
Test name
Test status
Simulation time 809109519 ps
CPU time 9.89 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:31 PM PDT 24
Peak memory 218708 kb
Host smart-d7ed7ed4-ce04-4de4-89c9-408daedbf5f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767635456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3767635456
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2408420824
Short name T424
Test name
Test status
Simulation time 247507689 ps
CPU time 7.86 seconds
Started Mar 24 01:57:28 PM PDT 24
Finished Mar 24 01:57:37 PM PDT 24
Peak memory 218512 kb
Host smart-25ea9dea-57fa-4665-86e3-463308450684
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408420824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2408420824
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.674127562
Short name T1002
Test name
Test status
Simulation time 1120658328 ps
CPU time 10.9 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 218592 kb
Host smart-3ae57d2a-ef24-4fbf-9831-08950c8cb911
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674127562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.674127562
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2180525509
Short name T1130
Test name
Test status
Simulation time 1146200338 ps
CPU time 11.33 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:33 PM PDT 24
Peak memory 218548 kb
Host smart-27fc41db-55a0-4346-bdc8-5eda71bd72ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180525509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2180525509
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.347917662
Short name T14
Test name
Test status
Simulation time 414442920 ps
CPU time 9.11 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:57:38 PM PDT 24
Peak memory 218648 kb
Host smart-c16dcd9e-0c78-4611-bcc3-1b845f47c137
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347917662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.347917662
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2921275981
Short name T1551
Test name
Test status
Simulation time 1683560431 ps
CPU time 11.04 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:37 PM PDT 24
Peak memory 226668 kb
Host smart-1c1028a6-3e84-40df-8b75-bf53a8c9edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921275981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2921275981
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.981123215
Short name T525
Test name
Test status
Simulation time 1485794123 ps
CPU time 11.69 seconds
Started Mar 24 02:37:18 PM PDT 24
Finished Mar 24 02:37:30 PM PDT 24
Peak memory 225800 kb
Host smart-e2671aa0-25b9-45da-9248-4e0531b7cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981123215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.981123215
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.1202106283
Short name T88
Test name
Test status
Simulation time 328587168 ps
CPU time 3.37 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 218268 kb
Host smart-f6f6b305-6d88-4242-92d4-6288d7458ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202106283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1202106283
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.51117608
Short name T1072
Test name
Test status
Simulation time 333983090 ps
CPU time 5.77 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 01:57:31 PM PDT 24
Peak memory 218192 kb
Host smart-09ee2df3-a10b-4617-b69a-763adef413e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51117608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.51117608
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2698642521
Short name T557
Test name
Test status
Simulation time 640600094 ps
CPU time 21.06 seconds
Started Mar 24 01:57:23 PM PDT 24
Finished Mar 24 01:57:45 PM PDT 24
Peak memory 251548 kb
Host smart-ae8e5f45-8817-4e3c-aff0-96c2fe50f820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698642521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2698642521
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.873997768
Short name T1450
Test name
Test status
Simulation time 224700730 ps
CPU time 22.22 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:43 PM PDT 24
Peak memory 251456 kb
Host smart-7b94d412-e1a8-4f15-95bc-df4e71579efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873997768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.873997768
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3014273482
Short name T277
Test name
Test status
Simulation time 224508290 ps
CPU time 3.16 seconds
Started Mar 24 01:57:23 PM PDT 24
Finished Mar 24 01:57:27 PM PDT 24
Peak memory 222632 kb
Host smart-700885f6-3a0e-4b89-86a8-9d34be40590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014273482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3014273482
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.554603197
Short name T1012
Test name
Test status
Simulation time 63859025 ps
CPU time 2.55 seconds
Started Mar 24 02:37:20 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 222644 kb
Host smart-dee3d307-eb83-49a0-83d5-af598d9f9b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554603197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.554603197
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2959522091
Short name T1275
Test name
Test status
Simulation time 3663296533 ps
CPU time 85.8 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:38:47 PM PDT 24
Peak memory 279936 kb
Host smart-fe680d37-9f65-4b20-8f63-7fce92f503fd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959522091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2959522091
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.242774649
Short name T212
Test name
Test status
Simulation time 100158216935 ps
CPU time 770.42 seconds
Started Mar 24 01:57:27 PM PDT 24
Finished Mar 24 02:10:18 PM PDT 24
Peak memory 439080 kb
Host smart-3514a9b3-9e68-4c93-a0fd-b08ba702ca9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=242774649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.242774649
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1438027144
Short name T1384
Test name
Test status
Simulation time 43860066 ps
CPU time 1.02 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:25 PM PDT 24
Peak memory 212084 kb
Host smart-badf15b0-3c27-4baf-9328-c79e334774a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438027144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1438027144
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.273364430
Short name T1366
Test name
Test status
Simulation time 65532004 ps
CPU time 1.02 seconds
Started Mar 24 01:57:25 PM PDT 24
Finished Mar 24 01:57:27 PM PDT 24
Peak memory 213264 kb
Host smart-18ec72da-605a-4d8e-9b0c-06636a6aaa80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273364430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.273364430
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1705867024
Short name T1076
Test name
Test status
Simulation time 17721601 ps
CPU time 0.94 seconds
Started Mar 24 02:37:25 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 209980 kb
Host smart-b52321ab-b2a9-48d8-be61-990754249921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705867024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1705867024
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3294169125
Short name T1312
Test name
Test status
Simulation time 67389272 ps
CPU time 0.97 seconds
Started Mar 24 01:57:27 PM PDT 24
Finished Mar 24 01:57:29 PM PDT 24
Peak memory 209968 kb
Host smart-cc40ac31-44f5-4039-a036-a5cd84338e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294169125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3294169125
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2645715046
Short name T1248
Test name
Test status
Simulation time 810475693 ps
CPU time 10.29 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:57:39 PM PDT 24
Peak memory 218556 kb
Host smart-3739a9c0-d449-4c0b-8b1c-74baaafc1bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645715046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2645715046
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2980324812
Short name T571
Test name
Test status
Simulation time 609674019 ps
CPU time 11.82 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:33 PM PDT 24
Peak memory 218572 kb
Host smart-be0a182a-7088-44d0-88ee-c1ec716228ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980324812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2980324812
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1442562811
Short name T564
Test name
Test status
Simulation time 346916352 ps
CPU time 3.11 seconds
Started Mar 24 02:37:18 PM PDT 24
Finished Mar 24 02:37:22 PM PDT 24
Peak memory 210136 kb
Host smart-1efeb6ba-79a2-4cb9-9a22-b0d8ecba17d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442562811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1442562811
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.692599880
Short name T1472
Test name
Test status
Simulation time 214169307 ps
CPU time 2.07 seconds
Started Mar 24 01:57:27 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 217368 kb
Host smart-19c7b646-79e8-440e-a8a1-6d6d68877d18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692599880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.692599880
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1035104224
Short name T1147
Test name
Test status
Simulation time 69266375 ps
CPU time 2.78 seconds
Started Mar 24 02:37:19 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 218660 kb
Host smart-d99ef657-5366-42a5-a97b-c2b43299cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035104224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1035104224
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1577898836
Short name T753
Test name
Test status
Simulation time 16719466 ps
CPU time 1.68 seconds
Started Mar 24 01:57:28 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 221812 kb
Host smart-2d3f5fb3-e96e-4e24-a4b1-07dfe8ed57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577898836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1577898836
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1628200681
Short name T1495
Test name
Test status
Simulation time 444149838 ps
CPU time 17.47 seconds
Started Mar 24 01:57:28 PM PDT 24
Finished Mar 24 01:57:46 PM PDT 24
Peak memory 219396 kb
Host smart-e968839d-1955-48ac-9d06-a3ba9aa9dbcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628200681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1628200681
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2556063420
Short name T1311
Test name
Test status
Simulation time 215951003 ps
CPU time 10.19 seconds
Started Mar 24 02:37:22 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 219520 kb
Host smart-ef8ce6fb-3d6f-4748-88f3-7c63568bba08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556063420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2556063420
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1293002439
Short name T954
Test name
Test status
Simulation time 407496885 ps
CPU time 12.37 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:57:42 PM PDT 24
Peak memory 218544 kb
Host smart-5b0d3ffa-64a4-4e26-8b79-28430d223470
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293002439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1293002439
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.287197461
Short name T1058
Test name
Test status
Simulation time 341451165 ps
CPU time 10.49 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:35 PM PDT 24
Peak memory 218664 kb
Host smart-097abe9d-4f48-45d9-9f60-dc1d5ccd4f0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287197461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.287197461
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2290762750
Short name T637
Test name
Test status
Simulation time 547164467 ps
CPU time 16.43 seconds
Started Mar 24 02:37:22 PM PDT 24
Finished Mar 24 02:37:38 PM PDT 24
Peak memory 218476 kb
Host smart-c5d6bece-f185-40c4-a998-2f4a302fd906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290762750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2290762750
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.650823372
Short name T217
Test name
Test status
Simulation time 612705767 ps
CPU time 8.49 seconds
Started Mar 24 01:57:30 PM PDT 24
Finished Mar 24 01:57:39 PM PDT 24
Peak memory 218528 kb
Host smart-89d21cf7-32ea-450b-90a9-36f2e3541be0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650823372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.650823372
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1643335719
Short name T484
Test name
Test status
Simulation time 715218547 ps
CPU time 8.05 seconds
Started Mar 24 01:57:27 PM PDT 24
Finished Mar 24 01:57:36 PM PDT 24
Peak memory 225708 kb
Host smart-3b57e761-3200-450c-9e99-837cc553aa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643335719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1643335719
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2329944312
Short name T586
Test name
Test status
Simulation time 502188596 ps
CPU time 7.06 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:29 PM PDT 24
Peak memory 225492 kb
Host smart-d4c5f67d-7e97-4af0-9c8b-04a6dec5f012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329944312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2329944312
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1752349074
Short name T870
Test name
Test status
Simulation time 53512084 ps
CPU time 3.55 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 214740 kb
Host smart-23cbcee8-0a22-4e82-9d1c-5a1e4edcf6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752349074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1752349074
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3342193135
Short name T1263
Test name
Test status
Simulation time 26920473 ps
CPU time 1.35 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:57:31 PM PDT 24
Peak memory 213752 kb
Host smart-f1bc225c-0a65-4ced-8a05-afa1d9d361de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342193135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3342193135
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3471891824
Short name T735
Test name
Test status
Simulation time 206120051 ps
CPU time 26.66 seconds
Started Mar 24 01:57:31 PM PDT 24
Finished Mar 24 01:57:58 PM PDT 24
Peak memory 251204 kb
Host smart-bee49040-8325-492f-a8a3-db21ed1781ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471891824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3471891824
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.415952945
Short name T1365
Test name
Test status
Simulation time 56137663 ps
CPU time 2.92 seconds
Started Mar 24 02:37:18 PM PDT 24
Finished Mar 24 02:37:21 PM PDT 24
Peak memory 226924 kb
Host smart-50bf730c-e92d-4d2d-adb5-b5892325d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415952945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.415952945
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.741868964
Short name T500
Test name
Test status
Simulation time 83992102 ps
CPU time 3.66 seconds
Started Mar 24 01:57:26 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 226932 kb
Host smart-a7b3bdd0-9183-4763-9ffa-497b9e550461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741868964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.741868964
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1155701713
Short name T109
Test name
Test status
Simulation time 13051461969 ps
CPU time 80.76 seconds
Started Mar 24 01:57:28 PM PDT 24
Finished Mar 24 01:58:50 PM PDT 24
Peak memory 284356 kb
Host smart-119e3e11-b5f4-4cf9-9efa-0b022a704060
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155701713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1155701713
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2093482122
Short name T1145
Test name
Test status
Simulation time 43979266707 ps
CPU time 134.58 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:39:38 PM PDT 24
Peak memory 268248 kb
Host smart-09d91e46-d355-4fd9-91d6-ad4f483c786a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093482122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2093482122
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2779401552
Short name T1441
Test name
Test status
Simulation time 12014570 ps
CPU time 1.11 seconds
Started Mar 24 02:37:21 PM PDT 24
Finished Mar 24 02:37:23 PM PDT 24
Peak memory 212112 kb
Host smart-4f0bfd3a-a8c9-4eff-bd2d-83c7c108f113
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779401552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2779401552
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3146979913
Short name T462
Test name
Test status
Simulation time 44793422 ps
CPU time 0.81 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:57:30 PM PDT 24
Peak memory 209208 kb
Host smart-9fb2ac89-7454-4d85-acc1-a0f271c40c00
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146979913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3146979913
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1761466594
Short name T653
Test name
Test status
Simulation time 54010006 ps
CPU time 1.01 seconds
Started Mar 24 01:55:00 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 209972 kb
Host smart-6a4833cb-83e5-419a-b6be-92ba51b484b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761466594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1761466594
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.51387049
Short name T855
Test name
Test status
Simulation time 382641841 ps
CPU time 1.03 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 210028 kb
Host smart-89bef380-d4c0-4c89-b0df-c38807a92991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51387049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.51387049
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1232643996
Short name T1427
Test name
Test status
Simulation time 22214407 ps
CPU time 0.97 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 210012 kb
Host smart-8688fd7e-3067-43b1-8dcf-ba2199526282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232643996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1232643996
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2740869096
Short name T1419
Test name
Test status
Simulation time 39165988 ps
CPU time 0.89 seconds
Started Mar 24 02:34:59 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 210040 kb
Host smart-c30a180c-ce01-497e-8d4c-265621b84a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740869096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2740869096
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.177995641
Short name T296
Test name
Test status
Simulation time 3505218737 ps
CPU time 12.9 seconds
Started Mar 24 01:54:56 PM PDT 24
Finished Mar 24 01:55:09 PM PDT 24
Peak memory 226720 kb
Host smart-84b7b159-19f8-4c72-9835-4df7298b8b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177995641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.177995641
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2291354715
Short name T1395
Test name
Test status
Simulation time 1464192036 ps
CPU time 13.1 seconds
Started Mar 24 02:34:57 PM PDT 24
Finished Mar 24 02:35:11 PM PDT 24
Peak memory 218592 kb
Host smart-81f259d3-5b4f-46f5-ba0e-b2c2fbb7c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291354715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2291354715
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3071400628
Short name T797
Test name
Test status
Simulation time 260647549 ps
CPU time 3.03 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 210228 kb
Host smart-64eb309a-70e4-4fbd-b995-f4358ac6b05d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071400628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3071400628
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.446812427
Short name T737
Test name
Test status
Simulation time 278683326 ps
CPU time 4.04 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 217572 kb
Host smart-d24e437c-2dd1-43a6-99bf-9c9e7b0eca0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446812427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.446812427
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2957156222
Short name T110
Test name
Test status
Simulation time 4673464836 ps
CPU time 118.99 seconds
Started Mar 24 01:54:56 PM PDT 24
Finished Mar 24 01:56:55 PM PDT 24
Peak memory 219740 kb
Host smart-2c6ba30b-0fd9-4797-bcc6-e704471b6bef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957156222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2957156222
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3160820398
Short name T912
Test name
Test status
Simulation time 1645646746 ps
CPU time 29.92 seconds
Started Mar 24 02:35:00 PM PDT 24
Finished Mar 24 02:35:31 PM PDT 24
Peak memory 218468 kb
Host smart-5e6174c1-0870-48c6-a1f5-3119f649d361
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160820398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3160820398
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1516245682
Short name T1047
Test name
Test status
Simulation time 285091978 ps
CPU time 4.09 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:55:02 PM PDT 24
Peak memory 217768 kb
Host smart-1b4eff0d-c758-4097-ac60-09a5db0d32de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516245682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
516245682
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2620675844
Short name T234
Test name
Test status
Simulation time 612410487 ps
CPU time 4.59 seconds
Started Mar 24 02:34:59 PM PDT 24
Finished Mar 24 02:35:03 PM PDT 24
Peak memory 217580 kb
Host smart-abf15a58-097e-4a3d-82c0-1ee1fdf68509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620675844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
620675844
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1240093865
Short name T15
Test name
Test status
Simulation time 1427042841 ps
CPU time 7.99 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 218536 kb
Host smart-a9b1fa10-62fc-4afc-a8f0-d917cf8cef44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240093865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1240093865
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2504581062
Short name T777
Test name
Test status
Simulation time 414025702 ps
CPU time 6.98 seconds
Started Mar 24 01:54:56 PM PDT 24
Finished Mar 24 01:55:03 PM PDT 24
Peak memory 218556 kb
Host smart-2aec1253-5157-4d9c-b0a9-3ee097a06f4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504581062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2504581062
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3926990091
Short name T1470
Test name
Test status
Simulation time 5606777771 ps
CPU time 38.69 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 214532 kb
Host smart-7c0dcb31-45fb-4479-bcdf-d87e1b837f72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926990091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3926990091
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.59692935
Short name T1557
Test name
Test status
Simulation time 4664448065 ps
CPU time 35.79 seconds
Started Mar 24 01:54:56 PM PDT 24
Finished Mar 24 01:55:32 PM PDT 24
Peak memory 214592 kb
Host smart-58124dcc-49dd-40ff-8dce-4a00e3ad19ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59692935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt
ag_regwen_during_op.59692935
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.298113927
Short name T592
Test name
Test status
Simulation time 2423769077 ps
CPU time 10.61 seconds
Started Mar 24 01:54:57 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 214740 kb
Host smart-b0f3e4e1-d894-4039-98cd-f7b9b2e85855
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298113927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.298113927
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.301879061
Short name T1627
Test name
Test status
Simulation time 121162722 ps
CPU time 4.16 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:02 PM PDT 24
Peak memory 213752 kb
Host smart-4592a23d-5ad7-4114-845e-2f62e3515a2d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301879061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.301879061
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1759411926
Short name T1587
Test name
Test status
Simulation time 1118993369 ps
CPU time 44.29 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:55:42 PM PDT 24
Peak memory 276036 kb
Host smart-457b27f6-569f-4d85-a183-54cec0926678
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759411926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1759411926
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.893848952
Short name T758
Test name
Test status
Simulation time 2527902850 ps
CPU time 61.85 seconds
Started Mar 24 02:35:00 PM PDT 24
Finished Mar 24 02:36:03 PM PDT 24
Peak memory 277752 kb
Host smart-65788c42-9b9d-495c-b199-8167dca94974
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893848952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.893848952
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1779262679
Short name T1487
Test name
Test status
Simulation time 1574475202 ps
CPU time 8.35 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:55:04 PM PDT 24
Peak memory 218460 kb
Host smart-fe391da5-4e4b-42d3-865f-26eaea3b02a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779262679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1779262679
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.298676558
Short name T17
Test name
Test status
Simulation time 5528224163 ps
CPU time 16.78 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:20 PM PDT 24
Peak memory 250712 kb
Host smart-876c934c-b7d9-4784-a49d-33f6b436ff06
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298676558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.298676558
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1607452412
Short name T1390
Test name
Test status
Simulation time 217938060 ps
CPU time 2.62 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:01 PM PDT 24
Peak memory 222616 kb
Host smart-f930075d-9357-4b84-8d75-49209b1af411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607452412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1607452412
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2322461090
Short name T1578
Test name
Test status
Simulation time 148466698 ps
CPU time 3.87 seconds
Started Mar 24 01:54:56 PM PDT 24
Finished Mar 24 01:55:01 PM PDT 24
Peak memory 222716 kb
Host smart-dccc3347-c424-4a05-90d8-cde1affcd1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322461090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2322461090
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2136732694
Short name T1256
Test name
Test status
Simulation time 350744164 ps
CPU time 13.01 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:55:11 PM PDT 24
Peak memory 215028 kb
Host smart-f5a70b63-5880-4b8d-8499-fc9d4674c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136732694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2136732694
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4163832325
Short name T1387
Test name
Test status
Simulation time 1107622183 ps
CPU time 10.18 seconds
Started Mar 24 02:34:57 PM PDT 24
Finished Mar 24 02:35:08 PM PDT 24
Peak memory 214784 kb
Host smart-6c5a0d40-0d67-4d64-a365-ca608acc7900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163832325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4163832325
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1587958534
Short name T937
Test name
Test status
Simulation time 1054079820 ps
CPU time 8.95 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:07 PM PDT 24
Peak memory 218760 kb
Host smart-ae83b646-a38f-4062-bd26-2e43a8a1208b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587958534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1587958534
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2734780527
Short name T41
Test name
Test status
Simulation time 1426403292 ps
CPU time 13.5 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:55:13 PM PDT 24
Peak memory 219552 kb
Host smart-88bf4834-81da-4237-a4ee-03489ac5fb43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734780527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2734780527
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2850419796
Short name T1517
Test name
Test status
Simulation time 253910316 ps
CPU time 8.11 seconds
Started Mar 24 02:34:58 PM PDT 24
Finished Mar 24 02:35:07 PM PDT 24
Peak memory 218808 kb
Host smart-ec1880e8-eee2-43c4-be2e-cce9df6909c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850419796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2850419796
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4252807357
Short name T545
Test name
Test status
Simulation time 518419390 ps
CPU time 9.13 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 218656 kb
Host smart-4c291f4b-d722-467c-854e-0f802a2e3c0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252807357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.4252807357
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3880495194
Short name T1211
Test name
Test status
Simulation time 1436282227 ps
CPU time 12.47 seconds
Started Mar 24 02:35:05 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 218552 kb
Host smart-794f64d6-9a51-4a90-8ca6-43197b7049ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880495194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
880495194
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3930545887
Short name T790
Test name
Test status
Simulation time 1885792565 ps
CPU time 10.24 seconds
Started Mar 24 01:55:01 PM PDT 24
Finished Mar 24 01:55:12 PM PDT 24
Peak memory 218572 kb
Host smart-a9ceeba8-3581-44c6-88bb-b14ad606de87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930545887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
930545887
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.189730993
Short name T410
Test name
Test status
Simulation time 463549267 ps
CPU time 7.57 seconds
Started Mar 24 02:34:59 PM PDT 24
Finished Mar 24 02:35:06 PM PDT 24
Peak memory 226624 kb
Host smart-cec88c90-d4d8-4ef2-8534-1b10ef6ba9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189730993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.189730993
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3423611029
Short name T981
Test name
Test status
Simulation time 1234500190 ps
CPU time 11.16 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:55:06 PM PDT 24
Peak memory 226596 kb
Host smart-e8bfde2e-3dfe-44c8-8a31-c1bff779111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423611029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3423611029
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1387202778
Short name T1694
Test name
Test status
Simulation time 60327337 ps
CPU time 2.35 seconds
Started Mar 24 01:54:57 PM PDT 24
Finished Mar 24 01:55:00 PM PDT 24
Peak memory 214612 kb
Host smart-dc6baddd-f0c2-4d61-b235-3351df686de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387202778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1387202778
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2945843251
Short name T731
Test name
Test status
Simulation time 119121443 ps
CPU time 1.5 seconds
Started Mar 24 02:34:59 PM PDT 24
Finished Mar 24 02:35:00 PM PDT 24
Peak memory 214116 kb
Host smart-e9b26acb-ebab-4986-b6ab-cd0758b6c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945843251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2945843251
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1770853635
Short name T717
Test name
Test status
Simulation time 145410900 ps
CPU time 21.15 seconds
Started Mar 24 01:54:56 PM PDT 24
Finished Mar 24 01:55:17 PM PDT 24
Peak memory 251520 kb
Host smart-58c349e0-4649-4a41-b265-74ce6f86c6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770853635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1770853635
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3445838904
Short name T202
Test name
Test status
Simulation time 321455552 ps
CPU time 30.63 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 247636 kb
Host smart-6f2b284a-5e84-4788-b24c-97f24181a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445838904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3445838904
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1495448131
Short name T1512
Test name
Test status
Simulation time 49177617 ps
CPU time 7.39 seconds
Started Mar 24 02:35:00 PM PDT 24
Finished Mar 24 02:35:08 PM PDT 24
Peak memory 251492 kb
Host smart-ac9f682c-487c-440f-bf59-96cc7a9d48d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495448131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1495448131
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3880921699
Short name T724
Test name
Test status
Simulation time 399758132 ps
CPU time 8.24 seconds
Started Mar 24 01:54:55 PM PDT 24
Finished Mar 24 01:55:03 PM PDT 24
Peak memory 251512 kb
Host smart-0fa04d01-a17f-4d76-be6b-840c88b90781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880921699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3880921699
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1296350349
Short name T1590
Test name
Test status
Simulation time 61319599633 ps
CPU time 150 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:57:29 PM PDT 24
Peak memory 220084 kb
Host smart-30fb8f38-5bac-4a43-b6bd-7d3422627f59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296350349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1296350349
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3805343540
Short name T1244
Test name
Test status
Simulation time 5875828215 ps
CPU time 113.12 seconds
Started Mar 24 02:35:01 PM PDT 24
Finished Mar 24 02:36:54 PM PDT 24
Peak memory 279648 kb
Host smart-8e143041-d733-4a73-bc4e-d34be81091bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805343540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3805343540
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.281472290
Short name T483
Test name
Test status
Simulation time 41227625 ps
CPU time 0.89 seconds
Started Mar 24 02:34:56 PM PDT 24
Finished Mar 24 02:34:58 PM PDT 24
Peak memory 212104 kb
Host smart-0ce6e605-d0e2-400d-a3af-6484bc2c4297
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281472290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.281472290
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3471617597
Short name T1535
Test name
Test status
Simulation time 46852860 ps
CPU time 0.96 seconds
Started Mar 24 01:54:57 PM PDT 24
Finished Mar 24 01:54:58 PM PDT 24
Peak memory 213024 kb
Host smart-985f7b5c-db2e-4865-bb48-d3c1dc21bafa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471617597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3471617597
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2369106006
Short name T904
Test name
Test status
Simulation time 19300876 ps
CPU time 0.91 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:10 PM PDT 24
Peak memory 208820 kb
Host smart-eff7e718-f90d-45d5-afbd-ecdd6a92f23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369106006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2369106006
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3653585376
Short name T1521
Test name
Test status
Simulation time 88278278 ps
CPU time 1 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:54:59 PM PDT 24
Peak memory 209968 kb
Host smart-5997db9a-6c4a-4cee-b7ba-76ca52f3dc28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653585376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3653585376
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.433032098
Short name T1658
Test name
Test status
Simulation time 26132059 ps
CPU time 0.79 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:14 PM PDT 24
Peak memory 209852 kb
Host smart-f159e8e0-1105-4efb-ad87-a4a320ff79c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433032098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.433032098
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1390054647
Short name T1644
Test name
Test status
Simulation time 1419507211 ps
CPU time 12.37 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:25 PM PDT 24
Peak memory 218488 kb
Host smart-2160293b-dd54-416a-a015-106db23bfa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390054647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1390054647
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3182133691
Short name T1015
Test name
Test status
Simulation time 284365993 ps
CPU time 9.65 seconds
Started Mar 24 01:55:00 PM PDT 24
Finished Mar 24 01:55:10 PM PDT 24
Peak memory 218592 kb
Host smart-5332e0f0-4a73-41c6-898c-985c39bb423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182133691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3182133691
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1511945370
Short name T899
Test name
Test status
Simulation time 476412284 ps
CPU time 7.35 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:16 PM PDT 24
Peak memory 208924 kb
Host smart-cf6cff5f-aec3-47c8-9945-24b940139484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511945370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1511945370
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.304626321
Short name T808
Test name
Test status
Simulation time 4714465570 ps
CPU time 24.91 seconds
Started Mar 24 01:55:03 PM PDT 24
Finished Mar 24 01:55:28 PM PDT 24
Peak memory 218260 kb
Host smart-5b6f81fe-910b-4144-b54d-1708d40aa3c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304626321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.304626321
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2989939629
Short name T1074
Test name
Test status
Simulation time 5375966421 ps
CPU time 23.65 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 219520 kb
Host smart-a35a12af-9c1d-43f5-b62f-c9dc84049176
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989939629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2989939629
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.86523634
Short name T1315
Test name
Test status
Simulation time 6579369034 ps
CPU time 92.1 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:56:32 PM PDT 24
Peak memory 219188 kb
Host smart-8b2cf55e-360c-42f9-be2f-73963639e6cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86523634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_l
c_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_erro
rs.86523634
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.181113730
Short name T1531
Test name
Test status
Simulation time 1683349943 ps
CPU time 10.04 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:14 PM PDT 24
Peak memory 217600 kb
Host smart-13acde65-1b6f-4baa-b2d1-977fb2cfb903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181113730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.181113730
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.3011932056
Short name T887
Test name
Test status
Simulation time 456141412 ps
CPU time 2.9 seconds
Started Mar 24 02:35:18 PM PDT 24
Finished Mar 24 02:35:21 PM PDT 24
Peak memory 217600 kb
Host smart-894abe88-ea62-4475-9c5e-a992a494ff2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011932056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.3
011932056
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.126479389
Short name T1293
Test name
Test status
Simulation time 230796569 ps
CPU time 4.85 seconds
Started Mar 24 01:55:03 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 218476 kb
Host smart-4a6bb1f2-433e-4f70-b307-dbb99f7cef2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126479389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.126479389
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4284842061
Short name T1677
Test name
Test status
Simulation time 1147533506 ps
CPU time 8.78 seconds
Started Mar 24 02:35:04 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 218540 kb
Host smart-0608e3b7-6316-4a5d-89c6-6ef1629bfa5f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284842061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4284842061
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3836791917
Short name T389
Test name
Test status
Simulation time 777007614 ps
CPU time 15.64 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 213564 kb
Host smart-eea21f5d-4e29-423f-bffe-71c6e7b371e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836791917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3836791917
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.814469615
Short name T606
Test name
Test status
Simulation time 980879313 ps
CPU time 12.02 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:16 PM PDT 24
Peak memory 213568 kb
Host smart-36faf4fb-9abd-4c39-a5cd-936821ab6eb0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814469615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.814469615
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3220912550
Short name T1533
Test name
Test status
Simulation time 425823330 ps
CPU time 7.07 seconds
Started Mar 24 01:55:00 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 213924 kb
Host smart-098d3e27-d370-42e8-9e08-d0e070e478d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220912550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3220912550
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.94195951
Short name T1406
Test name
Test status
Simulation time 757579031 ps
CPU time 5.84 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:09 PM PDT 24
Peak memory 213768 kb
Host smart-112ce109-f7c4-475f-8886-c8b9a740cd80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94195951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.94195951
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1812481660
Short name T671
Test name
Test status
Simulation time 15979390467 ps
CPU time 73.11 seconds
Started Mar 24 02:35:05 PM PDT 24
Finished Mar 24 02:36:19 PM PDT 24
Peak memory 284196 kb
Host smart-bd4f6e70-dad7-4076-9e32-072542438c5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812481660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1812481660
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2649994889
Short name T1451
Test name
Test status
Simulation time 14737597943 ps
CPU time 56.86 seconds
Started Mar 24 01:55:00 PM PDT 24
Finished Mar 24 01:55:57 PM PDT 24
Peak memory 284220 kb
Host smart-9325e59c-70f9-487a-b06a-6078d4f23d35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649994889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2649994889
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3896871076
Short name T1174
Test name
Test status
Simulation time 1862396468 ps
CPU time 14.61 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 251240 kb
Host smart-c7d37737-66f8-4404-b1dd-6e9a79b974b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896871076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3896871076
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4106784079
Short name T532
Test name
Test status
Simulation time 3692172529 ps
CPU time 16.46 seconds
Started Mar 24 01:55:01 PM PDT 24
Finished Mar 24 01:55:18 PM PDT 24
Peak memory 245592 kb
Host smart-0fc19f6f-4e14-4775-b6b2-1693511db924
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106784079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4106784079
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.239933607
Short name T1703
Test name
Test status
Simulation time 78000196 ps
CPU time 3.16 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:07 PM PDT 24
Peak memory 222440 kb
Host smart-7f197830-7adb-448e-a51b-5887c298950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239933607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.239933607
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3497455427
Short name T191
Test name
Test status
Simulation time 350642521 ps
CPU time 2.69 seconds
Started Mar 24 01:55:01 PM PDT 24
Finished Mar 24 01:55:04 PM PDT 24
Peak memory 222508 kb
Host smart-73d6b672-4647-46c1-a792-553be83c5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497455427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3497455427
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.262005415
Short name T334
Test name
Test status
Simulation time 250238526 ps
CPU time 8.34 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:21 PM PDT 24
Peak memory 214724 kb
Host smart-c96a978e-bf91-41d5-ba92-6ab340d6c709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262005415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.262005415
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4104282823
Short name T1545
Test name
Test status
Simulation time 1600798183 ps
CPU time 9.13 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 214216 kb
Host smart-85fbc14a-29e1-4659-973e-2daa972ecd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104282823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4104282823
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2129508110
Short name T613
Test name
Test status
Simulation time 412637410 ps
CPU time 11.24 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:15 PM PDT 24
Peak memory 218600 kb
Host smart-bc886902-d296-49f1-8920-89e95e37e0ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129508110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2129508110
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4164685212
Short name T773
Test name
Test status
Simulation time 479529983 ps
CPU time 12.31 seconds
Started Mar 24 02:35:04 PM PDT 24
Finished Mar 24 02:35:16 PM PDT 24
Peak memory 218696 kb
Host smart-46f5121f-be55-4569-afe6-161c78a57605
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164685212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4164685212
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1869495456
Short name T771
Test name
Test status
Simulation time 310754908 ps
CPU time 11.91 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 218564 kb
Host smart-ba9e6fdb-3c5d-4671-94eb-5a95866d7924
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869495456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1869495456
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.600963735
Short name T1367
Test name
Test status
Simulation time 615811494 ps
CPU time 12.48 seconds
Started Mar 24 01:55:00 PM PDT 24
Finished Mar 24 01:55:12 PM PDT 24
Peak memory 218464 kb
Host smart-abea9b29-a5b3-4c41-8ac4-c70c40583356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600963735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.600963735
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.4074053012
Short name T1139
Test name
Test status
Simulation time 1454072462 ps
CPU time 13.14 seconds
Started Mar 24 02:35:05 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 218588 kb
Host smart-c9de674e-b5c3-4e12-bdea-736a95b14296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074053012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.4
074053012
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.664533094
Short name T998
Test name
Test status
Simulation time 231117369 ps
CPU time 7.3 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 218644 kb
Host smart-4563af88-ba38-4f9d-b702-322c67dff528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664533094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.664533094
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1519183203
Short name T846
Test name
Test status
Simulation time 291059527 ps
CPU time 7.1 seconds
Started Mar 24 02:35:05 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 224736 kb
Host smart-0d531c5a-664f-4566-b9ff-edb95590e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519183203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1519183203
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.722261142
Short name T770
Test name
Test status
Simulation time 4120704178 ps
CPU time 9.8 seconds
Started Mar 24 01:55:01 PM PDT 24
Finished Mar 24 01:55:11 PM PDT 24
Peak memory 226676 kb
Host smart-203de9f4-7dfe-4abc-a552-85edf7bc636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722261142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.722261142
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1567584345
Short name T435
Test name
Test status
Simulation time 17590262 ps
CPU time 1.13 seconds
Started Mar 24 02:34:57 PM PDT 24
Finished Mar 24 02:34:59 PM PDT 24
Peak memory 218388 kb
Host smart-0d3f00f4-fca8-466f-b98e-49447f906968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567584345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1567584345
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3337777509
Short name T713
Test name
Test status
Simulation time 158996899 ps
CPU time 2.57 seconds
Started Mar 24 01:54:58 PM PDT 24
Finished Mar 24 01:55:01 PM PDT 24
Peak memory 214376 kb
Host smart-7c1ecf06-e610-4384-9227-3eb5f13865dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337777509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3337777509
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1554500739
Short name T980
Test name
Test status
Simulation time 235756113 ps
CPU time 26.56 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 251548 kb
Host smart-a672b173-0067-4251-88d3-4c2181e07c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554500739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1554500739
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.485397753
Short name T1104
Test name
Test status
Simulation time 1452943601 ps
CPU time 29.14 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:32 PM PDT 24
Peak memory 251508 kb
Host smart-5f942562-ac91-4cd2-9f01-26777d65388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485397753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.485397753
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2937887289
Short name T796
Test name
Test status
Simulation time 233899421 ps
CPU time 6.89 seconds
Started Mar 24 01:55:03 PM PDT 24
Finished Mar 24 01:55:10 PM PDT 24
Peak memory 247172 kb
Host smart-f286a533-af37-415f-a40f-479ec63c32c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937887289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2937887289
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3151330771
Short name T612
Test name
Test status
Simulation time 68476256 ps
CPU time 3.68 seconds
Started Mar 24 02:35:07 PM PDT 24
Finished Mar 24 02:35:11 PM PDT 24
Peak memory 226892 kb
Host smart-8bc96632-e542-44e2-a129-f6ad70de2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151330771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3151330771
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1755831449
Short name T563
Test name
Test status
Simulation time 273627700638 ps
CPU time 547.57 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:44:11 PM PDT 24
Peak memory 274060 kb
Host smart-cf433eba-0069-4909-bae1-ee6048358794
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755831449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1755831449
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.4228318848
Short name T16
Test name
Test status
Simulation time 17253253459 ps
CPU time 86.88 seconds
Started Mar 24 01:54:59 PM PDT 24
Finished Mar 24 01:56:26 PM PDT 24
Peak memory 226980 kb
Host smart-959314ab-144b-4682-8048-04d978368af7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228318848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.4228318848
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3046620854
Short name T184
Test name
Test status
Simulation time 293601439408 ps
CPU time 1525.05 seconds
Started Mar 24 02:35:04 PM PDT 24
Finished Mar 24 03:00:30 PM PDT 24
Peak memory 497464 kb
Host smart-b3f4db4a-2ab4-429e-a985-d09b3cb446a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3046620854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.3046620854
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1047245838
Short name T595
Test name
Test status
Simulation time 16951888 ps
CPU time 0.85 seconds
Started Mar 24 02:35:03 PM PDT 24
Finished Mar 24 02:35:04 PM PDT 24
Peak memory 208984 kb
Host smart-fd794d3b-b326-4c6f-8709-7ea41e8ed9ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047245838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1047245838
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2663531100
Short name T1324
Test name
Test status
Simulation time 40970384 ps
CPU time 0.9 seconds
Started Mar 24 01:55:05 PM PDT 24
Finished Mar 24 01:55:06 PM PDT 24
Peak memory 209268 kb
Host smart-1ab27b7f-23e5-431f-84e3-75dadffc5f93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663531100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2663531100
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3007204656
Short name T294
Test name
Test status
Simulation time 21831025 ps
CPU time 0.85 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 209832 kb
Host smart-a903cefd-2602-4068-9c5e-c6c87f97ed54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007204656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3007204656
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.583118848
Short name T1223
Test name
Test status
Simulation time 46176210 ps
CPU time 0.87 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 209820 kb
Host smart-eed162d0-0611-416d-aadd-d6aabb2ca32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583118848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.583118848
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2117087659
Short name T267
Test name
Test status
Simulation time 10612819 ps
CPU time 0.82 seconds
Started Mar 24 02:35:15 PM PDT 24
Finished Mar 24 02:35:16 PM PDT 24
Peak memory 209864 kb
Host smart-55c466d3-9046-40ea-b5eb-aea716a24c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117087659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2117087659
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3365586984
Short name T266
Test name
Test status
Simulation time 12089644 ps
CPU time 0.98 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:05 PM PDT 24
Peak memory 210012 kb
Host smart-2c158efd-ce1f-401c-a215-8fd66f41a966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365586984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3365586984
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.118476205
Short name T1082
Test name
Test status
Simulation time 405447558 ps
CPU time 11.29 seconds
Started Mar 24 01:55:03 PM PDT 24
Finished Mar 24 01:55:14 PM PDT 24
Peak memory 218624 kb
Host smart-5a4eba40-1f4e-4932-aec2-b288a063789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118476205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.118476205
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1292350903
Short name T1016
Test name
Test status
Simulation time 1680301976 ps
CPU time 9.74 seconds
Started Mar 24 02:35:17 PM PDT 24
Finished Mar 24 02:35:28 PM PDT 24
Peak memory 226672 kb
Host smart-517989df-e683-4004-8370-a693eb724f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292350903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1292350903
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1830213430
Short name T1307
Test name
Test status
Simulation time 212154531 ps
CPU time 3.25 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:14 PM PDT 24
Peak memory 210004 kb
Host smart-ec524cf2-e7b0-4b13-a704-78dac004570d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830213430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1830213430
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.419142455
Short name T559
Test name
Test status
Simulation time 4324965111 ps
CPU time 10.64 seconds
Started Mar 24 01:55:05 PM PDT 24
Finished Mar 24 01:55:16 PM PDT 24
Peak memory 218060 kb
Host smart-53be9c0d-f968-4721-99aa-b190e01b0b55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419142455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.419142455
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1304016418
Short name T1107
Test name
Test status
Simulation time 6634883851 ps
CPU time 24.35 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:35:36 PM PDT 24
Peak memory 218840 kb
Host smart-352abd7b-f2e7-43f3-8e04-969f51376793
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304016418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1304016418
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1327893238
Short name T977
Test name
Test status
Simulation time 7152889831 ps
CPU time 29.62 seconds
Started Mar 24 01:55:05 PM PDT 24
Finished Mar 24 01:55:35 PM PDT 24
Peak memory 218624 kb
Host smart-9ad49839-fd3a-4a59-b15a-bbf6628a7038
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327893238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1327893238
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3455533667
Short name T845
Test name
Test status
Simulation time 873402888 ps
CPU time 3.52 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:09 PM PDT 24
Peak memory 217700 kb
Host smart-c7574095-f9d0-470c-9311-b5b995b1552d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455533667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
455533667
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.462373801
Short name T686
Test name
Test status
Simulation time 15112478409 ps
CPU time 24.33 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 218404 kb
Host smart-dd63a594-9ef1-4bde-adfc-912f50638734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462373801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.462373801
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2800010709
Short name T985
Test name
Test status
Simulation time 533028892 ps
CPU time 9.15 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 218476 kb
Host smart-9d68fdf5-d616-4dbf-bafb-ff77e3c09cea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800010709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2800010709
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4059639494
Short name T1205
Test name
Test status
Simulation time 2367871082 ps
CPU time 9.95 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:16 PM PDT 24
Peak memory 218576 kb
Host smart-16ff7c3d-4b8a-4c18-8595-6c0aa4c4a6be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059639494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4059639494
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3074086078
Short name T573
Test name
Test status
Simulation time 2656279226 ps
CPU time 10.44 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 213692 kb
Host smart-8508ea48-d060-44fa-aa91-ee5defd92b35
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074086078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3074086078
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.769271479
Short name T1188
Test name
Test status
Simulation time 3949989160 ps
CPU time 14.63 seconds
Started Mar 24 01:55:07 PM PDT 24
Finished Mar 24 01:55:22 PM PDT 24
Peak memory 214348 kb
Host smart-e28c4604-82f6-46f0-84a9-70aa08abf983
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769271479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.769271479
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1219596468
Short name T572
Test name
Test status
Simulation time 530213801 ps
CPU time 13.89 seconds
Started Mar 24 02:35:15 PM PDT 24
Finished Mar 24 02:35:29 PM PDT 24
Peak memory 214160 kb
Host smart-c0abcab8-2182-4ea4-9e22-a04f412644d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219596468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1219596468
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1644815636
Short name T1443
Test name
Test status
Simulation time 231096175 ps
CPU time 7.5 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:12 PM PDT 24
Peak memory 213832 kb
Host smart-f06dab88-e7e1-4ba4-a7f4-74fa57e9803f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644815636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1644815636
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2959789606
Short name T368
Test name
Test status
Simulation time 768947426 ps
CPU time 38 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 251468 kb
Host smart-db70d3a9-1e06-4cbd-8e0b-f28d2d146e70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959789606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2959789606
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4240855395
Short name T445
Test name
Test status
Simulation time 3791007038 ps
CPU time 44.27 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:56 PM PDT 24
Peak memory 251724 kb
Host smart-c5553272-28aa-4edb-9f2d-4e820b389d53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240855395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.4240855395
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2927314667
Short name T318
Test name
Test status
Simulation time 558859304 ps
CPU time 21.53 seconds
Started Mar 24 01:55:07 PM PDT 24
Finished Mar 24 01:55:29 PM PDT 24
Peak memory 251456 kb
Host smart-a8aead55-2dd9-4dda-bfcc-aea894ccc2fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927314667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2927314667
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3807542429
Short name T930
Test name
Test status
Simulation time 2091710184 ps
CPU time 19.73 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:28 PM PDT 24
Peak memory 250984 kb
Host smart-7c331b28-6e34-411e-9dbc-3377422aaf83
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807542429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3807542429
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3056879629
Short name T1024
Test name
Test status
Simulation time 26702383 ps
CPU time 1.73 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 222092 kb
Host smart-2d544731-cc05-40ff-a3a7-1fdad8bcae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056879629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3056879629
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.78625202
Short name T324
Test name
Test status
Simulation time 81871854 ps
CPU time 2.82 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 218444 kb
Host smart-7cd9f105-3a16-4bb8-809b-14b3c1e77cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78625202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.78625202
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3511070818
Short name T1611
Test name
Test status
Simulation time 1472771389 ps
CPU time 13.97 seconds
Started Mar 24 01:55:08 PM PDT 24
Finished Mar 24 01:55:22 PM PDT 24
Peak memory 214944 kb
Host smart-7e1dde3a-dfc1-4fa4-99a7-460cd9714128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511070818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3511070818
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3678623369
Short name T1510
Test name
Test status
Simulation time 910521816 ps
CPU time 8.44 seconds
Started Mar 24 02:35:10 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 214640 kb
Host smart-bb8fd062-83b2-4372-84af-5220bb11dd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678623369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3678623369
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.211268112
Short name T1389
Test name
Test status
Simulation time 657958845 ps
CPU time 15.93 seconds
Started Mar 24 01:55:07 PM PDT 24
Finished Mar 24 01:55:23 PM PDT 24
Peak memory 218664 kb
Host smart-00a18443-e60c-445f-85d2-e2b489bc6870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211268112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.211268112
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.221538200
Short name T1051
Test name
Test status
Simulation time 5493479356 ps
CPU time 16.08 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 220016 kb
Host smart-a3367cdb-6e4d-43f6-abcb-80473384dec4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221538200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.221538200
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1947009609
Short name T1515
Test name
Test status
Simulation time 511516199 ps
CPU time 13.67 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:18 PM PDT 24
Peak memory 218544 kb
Host smart-5ba02c59-a872-4848-a0c0-ae85ce3d9aab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947009609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1947009609
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.4112119442
Short name T725
Test name
Test status
Simulation time 8835453438 ps
CPU time 14.46 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:23 PM PDT 24
Peak memory 218712 kb
Host smart-ed6ae977-dc93-427e-b447-e4d1c11849ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112119442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.4112119442
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1386000791
Short name T1133
Test name
Test status
Simulation time 678319309 ps
CPU time 12.79 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:19 PM PDT 24
Peak memory 218588 kb
Host smart-0bc22c84-dbbf-4db9-aa49-d5f6c341e10d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386000791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
386000791
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.697316320
Short name T1144
Test name
Test status
Simulation time 534169393 ps
CPU time 16.32 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:35:28 PM PDT 24
Peak memory 218568 kb
Host smart-a954ce4b-ca5a-4c32-b412-c36172ff379a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697316320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.697316320
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2331313805
Short name T276
Test name
Test status
Simulation time 1143723206 ps
CPU time 7.65 seconds
Started Mar 24 02:35:10 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 225368 kb
Host smart-0169d528-b953-4c80-a450-a9159cb3f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331313805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2331313805
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3883404692
Short name T810
Test name
Test status
Simulation time 601151901 ps
CPU time 13.34 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:19 PM PDT 24
Peak memory 226660 kb
Host smart-6cce987d-f8a7-411e-99f2-372928541c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883404692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3883404692
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2473786364
Short name T1604
Test name
Test status
Simulation time 1020801572 ps
CPU time 3.16 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:35:14 PM PDT 24
Peak memory 214960 kb
Host smart-7ff826b3-caec-41f7-877a-0b41b253d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473786364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2473786364
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2768689782
Short name T1612
Test name
Test status
Simulation time 84697938 ps
CPU time 3.11 seconds
Started Mar 24 01:55:03 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 215088 kb
Host smart-19223dbc-9534-4c1f-8678-797c16892e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768689782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2768689782
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2235473562
Short name T21
Test name
Test status
Simulation time 957131051 ps
CPU time 19.47 seconds
Started Mar 24 01:55:01 PM PDT 24
Finished Mar 24 01:55:21 PM PDT 24
Peak memory 251488 kb
Host smart-62b05e6d-edca-42ab-bfa3-d8dc7dad2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235473562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2235473562
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3794326896
Short name T1274
Test name
Test status
Simulation time 232087108 ps
CPU time 20.85 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:29 PM PDT 24
Peak memory 251544 kb
Host smart-7f0ce35a-a9b1-4fcb-a209-b40110c26646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794326896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3794326896
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1148439106
Short name T590
Test name
Test status
Simulation time 217187654 ps
CPU time 8.61 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 251356 kb
Host smart-530f1116-29bd-4f33-bfa2-a5df2c265790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148439106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1148439106
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3731877812
Short name T1492
Test name
Test status
Simulation time 59647556 ps
CPU time 8.06 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:14 PM PDT 24
Peak memory 251452 kb
Host smart-76cc0b21-bb30-4acd-9711-16b8ca1f22b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731877812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3731877812
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3930763538
Short name T1202
Test name
Test status
Simulation time 10884373468 ps
CPU time 431.99 seconds
Started Mar 24 02:35:11 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 278292 kb
Host smart-f0060c14-3b16-41d2-8840-f84bc30ba0a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930763538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3930763538
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.505555679
Short name T188
Test name
Test status
Simulation time 14431134482 ps
CPU time 251.87 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:59:16 PM PDT 24
Peak memory 248992 kb
Host smart-4a4170f1-acea-4e9d-b20e-b45fafa26932
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505555679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.505555679
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.724567932
Short name T222
Test name
Test status
Simulation time 29501605636 ps
CPU time 572.23 seconds
Started Mar 24 02:35:10 PM PDT 24
Finished Mar 24 02:44:43 PM PDT 24
Peak memory 283744 kb
Host smart-65e08d5a-2107-40d6-beca-744c1cc94ac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=724567932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.724567932
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1281330577
Short name T1288
Test name
Test status
Simulation time 149805123 ps
CPU time 0.92 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:14 PM PDT 24
Peak memory 212024 kb
Host smart-5b0c1997-302b-4f57-8fa1-e9f7c5e25683
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281330577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1281330577
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3619722760
Short name T898
Test name
Test status
Simulation time 31836809 ps
CPU time 0.85 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:05 PM PDT 24
Peak memory 209016 kb
Host smart-444eee7b-f07b-4310-8ddf-0a2c60c287ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619722760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3619722760
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1206494683
Short name T99
Test name
Test status
Simulation time 16238146 ps
CPU time 0.98 seconds
Started Mar 24 02:35:15 PM PDT 24
Finished Mar 24 02:35:16 PM PDT 24
Peak memory 209980 kb
Host smart-f11293fc-3895-4e71-9bb2-2474d23f00d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206494683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1206494683
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2174439439
Short name T1041
Test name
Test status
Simulation time 29363296 ps
CPU time 1.03 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:10 PM PDT 24
Peak memory 210056 kb
Host smart-4452f3a7-f2af-4815-877f-c257ca97022f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174439439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2174439439
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1546727166
Short name T262
Test name
Test status
Simulation time 60742405 ps
CPU time 0.86 seconds
Started Mar 24 01:55:07 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 209872 kb
Host smart-a1465335-0736-47ba-9185-954b2691d8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546727166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1546727166
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.4141168786
Short name T1368
Test name
Test status
Simulation time 11293201 ps
CPU time 0.84 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:10 PM PDT 24
Peak memory 209880 kb
Host smart-05219873-0c72-4949-ac9b-462987642080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141168786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.4141168786
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.278091894
Short name T599
Test name
Test status
Simulation time 2750070023 ps
CPU time 11.76 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:21 PM PDT 24
Peak memory 218620 kb
Host smart-7f2acaa0-5129-4ae9-bd65-27c53322d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278091894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.278091894
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.281278802
Short name T818
Test name
Test status
Simulation time 211451396 ps
CPU time 10.28 seconds
Started Mar 24 01:55:12 PM PDT 24
Finished Mar 24 01:55:22 PM PDT 24
Peak memory 218508 kb
Host smart-8816e655-4980-4126-ada7-61e520ef8586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281278802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.281278802
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1526846941
Short name T26
Test name
Test status
Simulation time 811757406 ps
CPU time 10.95 seconds
Started Mar 24 01:55:12 PM PDT 24
Finished Mar 24 01:55:23 PM PDT 24
Peak memory 217752 kb
Host smart-9542ad00-cdfe-4afb-98c3-6c39fdb30587
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526846941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1526846941
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2064606768
Short name T1005
Test name
Test status
Simulation time 1048146549 ps
CPU time 6.32 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:17 PM PDT 24
Peak memory 210004 kb
Host smart-385ad20f-ef9b-4915-b0cc-7aa72927a673
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064606768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2064606768
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1451695939
Short name T1057
Test name
Test status
Simulation time 2395860653 ps
CPU time 34.7 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:45 PM PDT 24
Peak memory 218644 kb
Host smart-3c50b51b-862f-44f5-bcfa-ed2cef2e0e44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451695939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1451695939
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2212909341
Short name T823
Test name
Test status
Simulation time 3625609488 ps
CPU time 29.1 seconds
Started Mar 24 01:55:10 PM PDT 24
Finished Mar 24 01:55:39 PM PDT 24
Peak memory 219404 kb
Host smart-63fa80bc-a507-442d-bd57-0acb9d2b5798
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212909341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2212909341
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2238597015
Short name T100
Test name
Test status
Simulation time 24116468688 ps
CPU time 39.68 seconds
Started Mar 24 02:35:10 PM PDT 24
Finished Mar 24 02:35:50 PM PDT 24
Peak memory 218340 kb
Host smart-d83a813a-f072-4539-8365-a022013d6ffe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238597015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
238597015
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.4015868891
Short name T1696
Test name
Test status
Simulation time 2948515744 ps
CPU time 18.28 seconds
Started Mar 24 01:55:08 PM PDT 24
Finished Mar 24 01:55:27 PM PDT 24
Peak memory 217924 kb
Host smart-d9609c08-bbe4-40ae-9bd6-a611a0dfe5ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015868891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.4
015868891
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1834839228
Short name T1563
Test name
Test status
Simulation time 1102349644 ps
CPU time 15.89 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:25 PM PDT 24
Peak memory 218512 kb
Host smart-a7c46aa5-9a4e-4a36-b00d-fd548b95361f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834839228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1834839228
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3079870602
Short name T542
Test name
Test status
Simulation time 446328854 ps
CPU time 7.95 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 218528 kb
Host smart-3921bd8f-2816-41f7-a655-026d8514169c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079870602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3079870602
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2661129821
Short name T675
Test name
Test status
Simulation time 2237684517 ps
CPU time 15.97 seconds
Started Mar 24 01:55:08 PM PDT 24
Finished Mar 24 01:55:24 PM PDT 24
Peak memory 213724 kb
Host smart-0dd28ec9-53d6-48f3-9e55-3888d186aa88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661129821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2661129821
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3298312045
Short name T1121
Test name
Test status
Simulation time 1324215261 ps
CPU time 21.62 seconds
Started Mar 24 02:35:15 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 213776 kb
Host smart-38ec8bc9-64ba-484f-99db-c9d7a043e397
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298312045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3298312045
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1877764353
Short name T956
Test name
Test status
Simulation time 176810341 ps
CPU time 3.68 seconds
Started Mar 24 02:35:14 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 213700 kb
Host smart-01ae454f-1913-41d5-9157-1aee6eb81b3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877764353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1877764353
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3401842839
Short name T290
Test name
Test status
Simulation time 149707571 ps
CPU time 3.29 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:13 PM PDT 24
Peak memory 213664 kb
Host smart-ba98b76c-8f1d-41fe-ab9c-6e04d87da3cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401842839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3401842839
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.196943927
Short name T1614
Test name
Test status
Simulation time 7497194218 ps
CPU time 73.48 seconds
Started Mar 24 01:55:10 PM PDT 24
Finished Mar 24 01:56:24 PM PDT 24
Peak memory 279588 kb
Host smart-7409261e-a380-443a-9cc9-8c04539bb260
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196943927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.196943927
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.853627628
Short name T893
Test name
Test status
Simulation time 1838734414 ps
CPU time 33 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:43 PM PDT 24
Peak memory 267828 kb
Host smart-812f1ab1-4b31-484a-a102-e89485defde1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853627628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.853627628
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1404656900
Short name T1028
Test name
Test status
Simulation time 7225318308 ps
CPU time 31.25 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:40 PM PDT 24
Peak memory 251456 kb
Host smart-27f89de0-acdb-4791-a0dd-582cd154584b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404656900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1404656900
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2062102874
Short name T1526
Test name
Test status
Simulation time 1776895334 ps
CPU time 16.79 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 226764 kb
Host smart-6881727b-adb5-470e-be14-f975948eac9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062102874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2062102874
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1036815039
Short name T366
Test name
Test status
Simulation time 344983524 ps
CPU time 4.11 seconds
Started Mar 24 01:55:07 PM PDT 24
Finished Mar 24 01:55:11 PM PDT 24
Peak memory 218620 kb
Host smart-4b316a97-2dd7-44de-a23d-fcb74088e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036815039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1036815039
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2538626752
Short name T477
Test name
Test status
Simulation time 300030871 ps
CPU time 3.4 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 218680 kb
Host smart-2237e401-bbc0-4016-a163-77cd450fb4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538626752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2538626752
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1953508470
Short name T360
Test name
Test status
Simulation time 784723799 ps
CPU time 12.84 seconds
Started Mar 24 01:55:08 PM PDT 24
Finished Mar 24 01:55:20 PM PDT 24
Peak memory 214844 kb
Host smart-98825c5a-aeb1-4fcb-86d8-7687bc9d72b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953508470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1953508470
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.206597276
Short name T126
Test name
Test status
Simulation time 2388600555 ps
CPU time 9.75 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 218416 kb
Host smart-bc40bb88-4556-42af-9572-9c57d525355f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206597276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.206597276
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2888482525
Short name T419
Test name
Test status
Simulation time 5331374263 ps
CPU time 22.52 seconds
Started Mar 24 02:35:16 PM PDT 24
Finished Mar 24 02:35:38 PM PDT 24
Peak memory 220236 kb
Host smart-223ed57f-c801-4a62-b79b-8d60016b44a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888482525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2888482525
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.4258337384
Short name T306
Test name
Test status
Simulation time 252264009 ps
CPU time 9.17 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:18 PM PDT 24
Peak memory 218604 kb
Host smart-ff0f5fef-681e-4586-acf6-351d423ad755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258337384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.4258337384
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3391017842
Short name T353
Test name
Test status
Simulation time 257400303 ps
CPU time 11.13 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:20 PM PDT 24
Peak memory 218540 kb
Host smart-7f27f29a-0720-47c2-b2de-2a6e81fec4a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391017842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3391017842
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.4122539861
Short name T291
Test name
Test status
Simulation time 1630189653 ps
CPU time 13.35 seconds
Started Mar 24 02:35:14 PM PDT 24
Finished Mar 24 02:35:28 PM PDT 24
Peak memory 218508 kb
Host smart-c448208c-9bbc-479b-b315-74caecb983d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122539861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.4122539861
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3207028946
Short name T774
Test name
Test status
Simulation time 1333347230 ps
CPU time 13.46 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 218480 kb
Host smart-2a390c9e-60ec-45c8-a14e-3d8ea5ae574d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207028946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
207028946
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3273495419
Short name T935
Test name
Test status
Simulation time 2085780634 ps
CPU time 12.56 seconds
Started Mar 24 01:55:06 PM PDT 24
Finished Mar 24 01:55:19 PM PDT 24
Peak memory 218584 kb
Host smart-4b13790c-c4de-4c50-9453-9ff09bfd6b3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273495419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
273495419
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.307223715
Short name T1020
Test name
Test status
Simulation time 295979579 ps
CPU time 13.55 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 226148 kb
Host smart-267bbe25-8e0d-4061-a1f3-3793af484c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307223715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.307223715
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.79283384
Short name T973
Test name
Test status
Simulation time 1143781156 ps
CPU time 10.66 seconds
Started Mar 24 01:55:10 PM PDT 24
Finished Mar 24 01:55:21 PM PDT 24
Peak memory 226104 kb
Host smart-b6b656fe-55f8-4770-9ddc-bbe0e22d1c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79283384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.79283384
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.121729420
Short name T357
Test name
Test status
Simulation time 48257138 ps
CPU time 2.5 seconds
Started Mar 24 01:55:05 PM PDT 24
Finished Mar 24 01:55:07 PM PDT 24
Peak memory 218424 kb
Host smart-2e1cc02c-7019-494b-9289-ec04ece8edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121729420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.121729420
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3165657271
Short name T79
Test name
Test status
Simulation time 172040016 ps
CPU time 2.05 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:12 PM PDT 24
Peak memory 218424 kb
Host smart-31221320-c38d-4ed9-aca5-a72e7bae9210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165657271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3165657271
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1033352276
Short name T931
Test name
Test status
Simulation time 212213669 ps
CPU time 14.74 seconds
Started Mar 24 02:35:08 PM PDT 24
Finished Mar 24 02:35:23 PM PDT 24
Peak memory 251452 kb
Host smart-238f8128-883a-41fe-9335-4313185df337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033352276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1033352276
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.4048625811
Short name T487
Test name
Test status
Simulation time 325710192 ps
CPU time 32.67 seconds
Started Mar 24 01:55:04 PM PDT 24
Finished Mar 24 01:55:37 PM PDT 24
Peak memory 248280 kb
Host smart-278fdf85-fc6d-4b26-bfac-c6e5402eb68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048625811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.4048625811
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1082924889
Short name T900
Test name
Test status
Simulation time 184672392 ps
CPU time 7.23 seconds
Started Mar 24 02:35:09 PM PDT 24
Finished Mar 24 02:35:18 PM PDT 24
Peak memory 251432 kb
Host smart-c9c8cffd-1ef5-40ab-bc6b-25329d37bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082924889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1082924889
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3640176274
Short name T1177
Test name
Test status
Simulation time 98176601 ps
CPU time 8.91 seconds
Started Mar 24 01:55:08 PM PDT 24
Finished Mar 24 01:55:17 PM PDT 24
Peak memory 251488 kb
Host smart-8bf5b617-ccfd-4ca1-ad2b-9dfc110f48d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640176274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3640176274
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3192093825
Short name T74
Test name
Test status
Simulation time 66302850723 ps
CPU time 930.23 seconds
Started Mar 24 02:35:17 PM PDT 24
Finished Mar 24 02:50:48 PM PDT 24
Peak memory 251496 kb
Host smart-1bfd6596-2e7e-4f0f-b38f-07eb3ba4edd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192093825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3192093825
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.519152709
Short name T1570
Test name
Test status
Simulation time 1847615634 ps
CPU time 38.82 seconds
Started Mar 24 01:55:11 PM PDT 24
Finished Mar 24 01:55:50 PM PDT 24
Peak memory 226892 kb
Host smart-72b4bc4e-b711-43e7-a336-3a8490183b79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519152709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.519152709
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3001303740
Short name T1329
Test name
Test status
Simulation time 48211105 ps
CPU time 1.02 seconds
Started Mar 24 02:35:14 PM PDT 24
Finished Mar 24 02:35:15 PM PDT 24
Peak memory 209088 kb
Host smart-4c92faac-671b-4368-a34a-fba9be5c24a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001303740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3001303740
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.441003599
Short name T1255
Test name
Test status
Simulation time 31924333 ps
CPU time 1.08 seconds
Started Mar 24 01:55:09 PM PDT 24
Finished Mar 24 01:55:10 PM PDT 24
Peak memory 212096 kb
Host smart-fe316017-d190-4ece-b4e3-07761d365a12
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441003599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.441003599
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2342893537
Short name T444
Test name
Test status
Simulation time 41524615 ps
CPU time 0.79 seconds
Started Mar 24 01:55:17 PM PDT 24
Finished Mar 24 01:55:17 PM PDT 24
Peak memory 209784 kb
Host smart-2a61f298-ec01-42fb-b9d3-6266960c8693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342893537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2342893537
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.870583831
Short name T1093
Test name
Test status
Simulation time 23774796 ps
CPU time 1.19 seconds
Started Mar 24 02:35:21 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 209992 kb
Host smart-dfed20c2-b85b-4379-aede-f62e8e06a4c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870583831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.870583831
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2305332617
Short name T348
Test name
Test status
Simulation time 87974428 ps
CPU time 1.02 seconds
Started Mar 24 01:55:15 PM PDT 24
Finished Mar 24 01:55:16 PM PDT 24
Peak memory 210028 kb
Host smart-fecbf5d7-9e97-4e2f-b638-a99d70725aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305332617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2305332617
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3453690706
Short name T265
Test name
Test status
Simulation time 80938666 ps
CPU time 0.79 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:13 PM PDT 24
Peak memory 209848 kb
Host smart-8de879f6-e807-4072-ba7d-251c726a4ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453690706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3453690706
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2941870411
Short name T546
Test name
Test status
Simulation time 644754143 ps
CPU time 9.23 seconds
Started Mar 24 02:35:17 PM PDT 24
Finished Mar 24 02:35:27 PM PDT 24
Peak memory 218580 kb
Host smart-7b609526-18ff-482d-9f5c-1b6048e54cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941870411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2941870411
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3539159527
Short name T497
Test name
Test status
Simulation time 320697896 ps
CPU time 12.98 seconds
Started Mar 24 01:55:13 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 226708 kb
Host smart-dfca63fa-8497-474c-894c-c02e998b9336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539159527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3539159527
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2772626258
Short name T1556
Test name
Test status
Simulation time 1866093342 ps
CPU time 12.37 seconds
Started Mar 24 01:55:34 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 217772 kb
Host smart-d1d0ed9b-a199-4e81-a124-8744d571a9ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772626258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2772626258
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.686101191
Short name T443
Test name
Test status
Simulation time 68873691 ps
CPU time 1.73 seconds
Started Mar 24 02:35:20 PM PDT 24
Finished Mar 24 02:35:22 PM PDT 24
Peak memory 217076 kb
Host smart-5b556b18-b3c3-4556-8f6b-aa14bae2a482
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686101191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.686101191
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1654997339
Short name T633
Test name
Test status
Simulation time 1530202799 ps
CPU time 30.96 seconds
Started Mar 24 01:55:16 PM PDT 24
Finished Mar 24 01:55:47 PM PDT 24
Peak memory 218544 kb
Host smart-ab235d0a-6f18-4419-8d73-4645c8b66ffe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654997339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1654997339
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.597671660
Short name T640
Test name
Test status
Simulation time 35419341626 ps
CPU time 70.75 seconds
Started Mar 24 02:35:26 PM PDT 24
Finished Mar 24 02:36:37 PM PDT 24
Peak memory 219524 kb
Host smart-f98b0cff-1635-4dbf-b4ca-e5cae3fa6010
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597671660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.597671660
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1732458028
Short name T1481
Test name
Test status
Simulation time 1131266274 ps
CPU time 10.94 seconds
Started Mar 24 01:55:17 PM PDT 24
Finished Mar 24 01:55:28 PM PDT 24
Peak memory 217532 kb
Host smart-68106231-0ab9-4c36-ae9d-327075164668
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732458028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
732458028
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.613375917
Short name T1163
Test name
Test status
Simulation time 226007897 ps
CPU time 3.55 seconds
Started Mar 24 02:35:20 PM PDT 24
Finished Mar 24 02:35:24 PM PDT 24
Peak memory 217584 kb
Host smart-f16587ca-2328-4223-9b31-23ec16ac2cbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613375917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.613375917
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3277049824
Short name T1331
Test name
Test status
Simulation time 672719601 ps
CPU time 10.2 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 218496 kb
Host smart-31178624-a7b3-4072-93a7-c61014c7f00d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277049824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3277049824
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3974863453
Short name T1372
Test name
Test status
Simulation time 541931200 ps
CPU time 2.45 seconds
Started Mar 24 02:35:19 PM PDT 24
Finished Mar 24 02:35:23 PM PDT 24
Peak memory 218568 kb
Host smart-11cf7423-be4a-4697-acff-e297fe95f236
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974863453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3974863453
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.418766621
Short name T440
Test name
Test status
Simulation time 937822787 ps
CPU time 13.49 seconds
Started Mar 24 02:35:22 PM PDT 24
Finished Mar 24 02:35:36 PM PDT 24
Peak memory 213616 kb
Host smart-f162fd28-673e-4456-9db5-abbb8636c131
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418766621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.418766621
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.773341059
Short name T1073
Test name
Test status
Simulation time 6532970279 ps
CPU time 30.19 seconds
Started Mar 24 01:55:32 PM PDT 24
Finished Mar 24 01:56:03 PM PDT 24
Peak memory 214464 kb
Host smart-be0d72a4-9d49-4586-a8c1-93821e8f3374
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773341059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.773341059
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2437748652
Short name T915
Test name
Test status
Simulation time 258012767 ps
CPU time 1.82 seconds
Started Mar 24 01:55:12 PM PDT 24
Finished Mar 24 01:55:14 PM PDT 24
Peak memory 213404 kb
Host smart-9f1a5ec1-fdd3-45fa-9c2a-77eddcac6a77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437748652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2437748652
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2795548350
Short name T1050
Test name
Test status
Simulation time 14293908170 ps
CPU time 8.19 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:20 PM PDT 24
Peak memory 214556 kb
Host smart-3c784f5a-243e-45f5-a2fb-0fd7f04b762a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795548350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2795548350
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1889259812
Short name T1018
Test name
Test status
Simulation time 6374685102 ps
CPU time 63.44 seconds
Started Mar 24 01:55:13 PM PDT 24
Finished Mar 24 01:56:16 PM PDT 24
Peak memory 268904 kb
Host smart-b55c9441-3bf0-4269-989b-170c5f75332f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889259812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1889259812
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3966448537
Short name T1194
Test name
Test status
Simulation time 5208268207 ps
CPU time 88.78 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:36:42 PM PDT 24
Peak memory 276608 kb
Host smart-f00ab31f-3e6e-43fa-b32e-ddd7bd8708f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966448537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3966448537
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4115072726
Short name T114
Test name
Test status
Simulation time 281016194 ps
CPU time 9.77 seconds
Started Mar 24 02:35:23 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 226876 kb
Host smart-3c1c39a6-aaac-40dc-93d2-f6c1044d5036
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115072726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4115072726
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.711959971
Short name T1160
Test name
Test status
Simulation time 1226664044 ps
CPU time 12.44 seconds
Started Mar 24 01:55:14 PM PDT 24
Finished Mar 24 01:55:27 PM PDT 24
Peak memory 251456 kb
Host smart-b113f4d3-35ae-4f4f-a3c9-32e524d34bbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711959971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.711959971
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1061396031
Short name T1043
Test name
Test status
Simulation time 64565218 ps
CPU time 3.38 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:15 PM PDT 24
Peak memory 218596 kb
Host smart-d254b4fd-bdf2-4dee-b1ca-304cf569911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061396031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1061396031
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.3257155345
Short name T1436
Test name
Test status
Simulation time 97156615 ps
CPU time 3.52 seconds
Started Mar 24 01:55:12 PM PDT 24
Finished Mar 24 01:55:16 PM PDT 24
Peak memory 222500 kb
Host smart-5954a294-c410-4eac-aa42-b8c9054c6a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257155345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3257155345
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2432346159
Short name T501
Test name
Test status
Simulation time 216387115 ps
CPU time 5.92 seconds
Started Mar 24 02:35:13 PM PDT 24
Finished Mar 24 02:35:20 PM PDT 24
Peak memory 214760 kb
Host smart-5bb3cc21-24df-4c69-a325-20f294d22318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432346159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2432346159
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3742996382
Short name T1491
Test name
Test status
Simulation time 955388838 ps
CPU time 13.3 seconds
Started Mar 24 01:55:13 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 214836 kb
Host smart-2ae3986d-8685-4c32-b266-a015b92b6d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742996382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3742996382
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1431735377
Short name T1673
Test name
Test status
Simulation time 360122446 ps
CPU time 15.6 seconds
Started Mar 24 01:55:17 PM PDT 24
Finished Mar 24 01:55:32 PM PDT 24
Peak memory 219524 kb
Host smart-116a2052-f900-439b-850e-e0b6a646a248
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431735377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1431735377
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.557508295
Short name T1113
Test name
Test status
Simulation time 977258688 ps
CPU time 12.53 seconds
Started Mar 24 02:35:26 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 226396 kb
Host smart-47a47b4c-a012-4014-a695-aa6f7cb9cb42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557508295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.557508295
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.134264711
Short name T1421
Test name
Test status
Simulation time 364053440 ps
CPU time 14.11 seconds
Started Mar 24 01:55:20 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 218580 kb
Host smart-a7cfbba3-e20a-43bd-8b7a-7a17a8b54bf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134264711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.134264711
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2712148372
Short name T574
Test name
Test status
Simulation time 389697875 ps
CPU time 11.47 seconds
Started Mar 24 02:35:25 PM PDT 24
Finished Mar 24 02:35:37 PM PDT 24
Peak memory 218632 kb
Host smart-a03a3e09-82a4-4e10-a069-7343f449956b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712148372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2712148372
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3632120606
Short name T1381
Test name
Test status
Simulation time 261382094 ps
CPU time 9.41 seconds
Started Mar 24 01:55:34 PM PDT 24
Finished Mar 24 01:55:44 PM PDT 24
Peak memory 218564 kb
Host smart-fe9a3993-3c34-4403-b13c-8c22a356878a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632120606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
632120606
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.697916349
Short name T1613
Test name
Test status
Simulation time 246285727 ps
CPU time 10.64 seconds
Started Mar 24 02:35:24 PM PDT 24
Finished Mar 24 02:35:34 PM PDT 24
Peak memory 218596 kb
Host smart-2879196c-88e5-437d-ba40-286a409594c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697916349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.697916349
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1438615404
Short name T920
Test name
Test status
Simulation time 664764456 ps
CPU time 8.5 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:21 PM PDT 24
Peak memory 225136 kb
Host smart-880cde51-ff4e-44c2-aca7-b16ccc142031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438615404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1438615404
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4228164769
Short name T56
Test name
Test status
Simulation time 361755742 ps
CPU time 13.52 seconds
Started Mar 24 01:55:12 PM PDT 24
Finished Mar 24 01:55:25 PM PDT 24
Peak memory 226636 kb
Host smart-46e9f203-af57-480e-ad6a-2d6849cdaccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228164769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4228164769
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.2269848382
Short name T1033
Test name
Test status
Simulation time 374491827 ps
CPU time 2.69 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:15 PM PDT 24
Peak memory 215100 kb
Host smart-66c8ddab-ead1-4cf8-a546-49e2c6d21479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269848382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.2269848382
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.4207416254
Short name T476
Test name
Test status
Simulation time 168046943 ps
CPU time 2.15 seconds
Started Mar 24 01:55:11 PM PDT 24
Finished Mar 24 01:55:13 PM PDT 24
Peak memory 214588 kb
Host smart-ab97afde-657d-4879-bf45-23a65d119ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207416254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4207416254
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2563286035
Short name T634
Test name
Test status
Simulation time 361355267 ps
CPU time 25.69 seconds
Started Mar 24 02:35:15 PM PDT 24
Finished Mar 24 02:35:41 PM PDT 24
Peak memory 251312 kb
Host smart-55b6d6b9-7eef-4705-a4dd-0822f144e112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563286035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2563286035
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.795990833
Short name T1626
Test name
Test status
Simulation time 415201721 ps
CPU time 26.97 seconds
Started Mar 24 01:55:15 PM PDT 24
Finished Mar 24 01:55:43 PM PDT 24
Peak memory 251392 kb
Host smart-71bab327-010f-427e-92b1-186b9e15356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795990833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.795990833
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1373505013
Short name T650
Test name
Test status
Simulation time 73313541 ps
CPU time 4.26 seconds
Started Mar 24 01:55:12 PM PDT 24
Finished Mar 24 01:55:17 PM PDT 24
Peak memory 226824 kb
Host smart-99f5910d-057f-4c0a-b9d0-3b985b66d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373505013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1373505013
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3218502950
Short name T215
Test name
Test status
Simulation time 301282120 ps
CPU time 3.57 seconds
Started Mar 24 02:35:12 PM PDT 24
Finished Mar 24 02:35:16 PM PDT 24
Peak memory 223020 kb
Host smart-4f762f1b-82bc-4a76-999e-64edab38538d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218502950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3218502950
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1855687075
Short name T784
Test name
Test status
Simulation time 61268499494 ps
CPU time 417.86 seconds
Started Mar 24 02:35:18 PM PDT 24
Finished Mar 24 02:42:16 PM PDT 24
Peak memory 389424 kb
Host smart-68970ee3-99f9-4edf-94ba-1c14bee647c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855687075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1855687075
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4155501629
Short name T1594
Test name
Test status
Simulation time 23172130437 ps
CPU time 203.36 seconds
Started Mar 24 01:55:17 PM PDT 24
Finished Mar 24 01:58:41 PM PDT 24
Peak memory 284264 kb
Host smart-312549bb-1161-4f49-8a38-5ed6c000d101
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155501629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4155501629
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2553488967
Short name T518
Test name
Test status
Simulation time 13499754 ps
CPU time 0.94 seconds
Started Mar 24 01:55:11 PM PDT 24
Finished Mar 24 01:55:12 PM PDT 24
Peak memory 209328 kb
Host smart-36d73dad-606a-4a0c-a0d9-5fc7aea7b85a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553488967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2553488967
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.967225499
Short name T414
Test name
Test status
Simulation time 20037213 ps
CPU time 0.8 seconds
Started Mar 24 02:35:17 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 209244 kb
Host smart-7da1f7d8-90c0-44c9-9932-d992a134d3d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967225499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.967225499
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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