Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3975423	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4422267

1

T1

821

T2

8630

T3

284

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7702657	1			T1	659		T2	15564		T3	394
values[0x0]	346691	1			T1	323		T2	557		T3	63
values[0x1]	348342	1			T1	317		T2	610		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3160653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5237037

1

T1

950

T2

10264

T3

335

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28906	1			T1	1		T9	11		T5	919
valid_sources[0x01]	43061	1			T1	14		T9	8		T4	2
valid_sources[0x02]	28147	1			T1	8		T9	12		T4	4
valid_sources[0x03]	28049	1			T1	8		T9	3		T11	2
valid_sources[0x04]	29724	1			T1	4		T9	9		T11	9
valid_sources[0x05]	31238	1			T1	4		T2	17		T9	12
valid_sources[0x06]	30369	1			T1	1		T9	19		T4	4
valid_sources[0x07]	28256	1			T9	6		T11	4		T5	894
valid_sources[0x08]	28561	1			T1	2		T9	10		T11	4
valid_sources[0x09]	28540	1			T1	4		T9	14		T11	11
valid_sources[0x0a]	29290	1			T1	9		T9	11		T11	5
valid_sources[0x0b]	32927	1			T1	7		T9	10		T4	9
valid_sources[0x0c]	28248	1			T9	11		T4	1		T11	6
valid_sources[0x0d]	28111	1			T1	2		T9	7		T5	901
valid_sources[0x0e]	28725	1			T1	10		T9	13		T4	1
valid_sources[0x0f]	28453	1			T1	2		T9	12		T4	1
valid_sources[0x10]	28314	1			T1	11		T9	7		T4	2
valid_sources[0x11]	29305	1			T1	3		T9	13		T4	2
valid_sources[0x12]	28319	1			T1	2		T9	8		T11	8
valid_sources[0x13]	34272	1			T1	11		T9	10		T11	1
valid_sources[0x14]	29459	1			T1	4		T9	15		T4	2
valid_sources[0x15]	29481	1			T1	1		T9	8		T11	5
valid_sources[0x16]	29434	1			T1	13		T9	14		T4	1
valid_sources[0x17]	27765	1			T1	7		T9	6		T11	2
valid_sources[0x18]	29387	1			T1	4		T9	9		T11	3
valid_sources[0x19]	33253	1			T1	14		T9	9		T11	3
valid_sources[0x1a]	28138	1			T1	1		T9	4		T11	3
valid_sources[0x1b]	30518	1			T1	6		T9	9		T11	7
valid_sources[0x1c]	28385	1			T1	4		T9	7		T11	2
valid_sources[0x1d]	34382	1			T1	5		T9	6		T4	1
valid_sources[0x1e]	28970	1			T1	2		T9	12		T10	1
valid_sources[0x1f]	27912	1			T1	6		T9	13		T11	7
valid_sources[0x20]	38907	1			T1	1		T9	11		T4	2
valid_sources[0x21]	29233	1			T1	5		T9	9		T4	5
valid_sources[0x22]	28470	1			T1	3		T9	9		T4	3
valid_sources[0x23]	27934	1			T1	9		T9	9		T4	6
valid_sources[0x24]	27567	1			T1	7		T9	20		T11	2
valid_sources[0x25]	29412	1			T1	1		T9	8		T4	5
valid_sources[0x26]	30894	1			T1	9		T3	514		T9	6
valid_sources[0x27]	33940	1			T1	3		T9	10		T10	1
valid_sources[0x28]	34737	1			T1	10		T9	12		T11	3
valid_sources[0x29]	28068	1			T1	7		T9	11		T11	3
valid_sources[0x2a]	29014	1			T1	2		T9	13		T11	7
valid_sources[0x2b]	28100	1			T1	10		T9	4		T11	3
valid_sources[0x2c]	28179	1			T1	8		T9	4		T11	4
valid_sources[0x2d]	30331	1			T1	2		T9	17		T11	2
valid_sources[0x2e]	29878	1			T1	8		T9	5		T11	2
valid_sources[0x2f]	40141	1			T1	6		T9	15		T11	5
valid_sources[0x30]	27768	1			T1	5		T9	7		T11	4
valid_sources[0x31]	28249	1			T1	3		T9	3		T10	2
valid_sources[0x32]	28443	1			T1	3		T9	10		T11	5
valid_sources[0x33]	37099	1			T1	3		T9	12		T11	1
valid_sources[0x34]	29237	1			T1	12		T9	8		T10	1
valid_sources[0x35]	29376	1			T1	7		T9	7		T11	4
valid_sources[0x36]	28826	1			T1	4		T9	12		T4	5
valid_sources[0x37]	56777	1			T1	3		T9	8		T11	6
valid_sources[0x38]	31349	1			T1	9		T9	10		T4	1
valid_sources[0x39]	30043	1			T1	8		T9	18		T11	8
valid_sources[0x3a]	54801	1			T1	1		T9	7		T4	7
valid_sources[0x3b]	28828	1			T1	7		T9	18		T4	2
valid_sources[0x3c]	30376	1			T1	7		T9	12		T10	1
valid_sources[0x3d]	29450	1			T1	4		T9	7		T11	5
valid_sources[0x3e]	28318	1			T1	4		T9	6		T4	3
valid_sources[0x3f]	36175	1			T1	15		T9	10		T11	14
valid_sources[0x40]	27930	1			T1	4		T9	11		T10	2
valid_sources[0x41]	36433	1			T1	9		T9	13		T4	1
valid_sources[0x42]	31463	1			T1	5		T9	12		T11	3
valid_sources[0x43]	29770	1			T9	11		T11	8		T5	937
valid_sources[0x44]	29524	1			T1	9		T9	5		T4	2
valid_sources[0x45]	29743	1			T1	11		T9	12		T11	7
valid_sources[0x46]	27918	1			T1	5		T9	7		T11	4
valid_sources[0x47]	30375	1			T1	1		T9	8		T11	1
valid_sources[0x48]	29935	1			T1	8		T9	7		T11	6
valid_sources[0x49]	28352	1			T1	1		T9	9		T4	5
valid_sources[0x4a]	31591	1			T1	1		T9	12		T4	1
valid_sources[0x4b]	30224	1			T1	11		T9	9		T4	3
valid_sources[0x4c]	28413	1			T1	3		T9	12		T11	2
valid_sources[0x4d]	28253	1			T1	3		T9	9		T11	4
valid_sources[0x4e]	74157	1			T1	5		T9	20		T4	1
valid_sources[0x4f]	30545	1			T1	6		T9	14		T11	3
valid_sources[0x50]	28618	1			T1	3		T9	5		T4	1
valid_sources[0x51]	30368	1			T1	5		T9	18		T4	1
valid_sources[0x52]	32116	1			T1	1		T9	8		T11	7
valid_sources[0x53]	47352	1			T1	8		T2	17		T9	13
valid_sources[0x54]	29195	1			T1	4		T9	13		T11	2
valid_sources[0x55]	28619	1			T1	11		T9	7		T11	1
valid_sources[0x56]	28659	1			T1	5		T9	12		T4	2
valid_sources[0x57]	34445	1			T1	8		T9	10		T11	6
valid_sources[0x58]	35893	1			T1	5		T9	11		T10	1
valid_sources[0x59]	29323	1			T1	2		T9	6		T4	1
valid_sources[0x5a]	31149	1			T1	6		T9	16		T4	1
valid_sources[0x5b]	28450	1			T1	2		T9	9		T4	3
valid_sources[0x5c]	32259	1			T1	2		T9	2		T4	3
valid_sources[0x5d]	30222	1			T1	5		T9	17		T4	2
valid_sources[0x5e]	45585	1			T1	3		T9	8		T11	4
valid_sources[0x5f]	39941	1			T1	3		T9	10		T4	3
valid_sources[0x60]	29355	1			T1	4		T9	8		T11	3
valid_sources[0x61]	29675	1			T1	5		T9	10		T4	3
valid_sources[0x62]	31116	1			T1	4		T9	10		T10	1
valid_sources[0x63]	29878	1			T1	3		T9	12		T4	1
valid_sources[0x64]	28682	1			T1	4		T9	12		T4	1
valid_sources[0x65]	31343	1			T1	5		T9	12		T10	1
valid_sources[0x66]	31128	1			T1	5		T9	7		T10	1
valid_sources[0x67]	31250	1			T1	12		T9	8		T4	2
valid_sources[0x68]	30271	1			T1	5		T9	11		T10	1
valid_sources[0x69]	28968	1			T1	2		T9	9		T10	1
valid_sources[0x6a]	28601	1			T1	10		T9	6		T10	1
valid_sources[0x6b]	28780	1			T1	2		T9	13		T11	5
valid_sources[0x6c]	28977	1			T1	5		T9	17		T10	1
valid_sources[0x6d]	29096	1			T1	4		T9	9		T4	2
valid_sources[0x6e]	27787	1			T1	8		T9	11		T4	1
valid_sources[0x6f]	30107	1			T1	6		T9	13		T4	5
valid_sources[0x70]	28062	1			T1	11		T9	13		T11	5
valid_sources[0x71]	30248	1			T1	10		T9	8		T10	1
valid_sources[0x72]	28735	1			T1	6		T9	19		T10	1
valid_sources[0x73]	30889	1			T1	1		T9	5		T11	4
valid_sources[0x74]	69747	1			T1	7		T9	6		T4	2
valid_sources[0x75]	47356	1			T1	3		T9	13		T4	1
valid_sources[0x76]	29255	1			T1	7		T9	9		T10	1
valid_sources[0x77]	71925	1			T1	11		T9	10		T11	7
valid_sources[0x78]	28204	1			T1	6		T9	16		T11	7
valid_sources[0x79]	29322	1			T1	4		T9	6		T4	1
valid_sources[0x7a]	75074	1			T1	5		T9	11		T11	1
valid_sources[0x7b]	28404	1			T1	1		T9	14		T11	1
valid_sources[0x7c]	104846	1			T1	9		T9	10		T5	918
valid_sources[0x7d]	29263	1			T1	1		T9	9		T4	2
valid_sources[0x7e]	28853	1			T1	6		T9	13		T11	1
valid_sources[0x7f]	30883	1			T1	2		T9	12		T10	1
valid_sources[0x80]	32985	1			T1	8		T9	1		T11	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3823449

1

T1

253

T2

7630

T3

186

values[0x0]

all_enables

biggest_size

300466

1

T1

284

T2

480

T3

55

values[0x1]

all_enables

biggest_size

298352

1

T1

284

T2

520

T3

43