Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	220529874	28845	0	0
claim_transition_if_regwen_rd_A	220529874	2616	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220529874	28845	0	0
T5	485860	13	0	0
T6	25430	0	0	0
T12	51332	0	0	0
T13	37975	0	0	0
T14	2702	0	0	0
T15	28021	0	0	0
T16	406493	0	0	0
T26	25069	0	0	0
T27	34495	0	0	0
T43	0	2	0	0
T57	0	6	0	0
T65	30648	0	0	0
T66	0	18	0	0
T103	0	3	0	0
T107	0	7	0	0
T132	0	15	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	15	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220529874	2616	0	0
T39	32466	0	0	0
T43	659679	4	0	0
T52	20515	0	0	0
T55	22751	0	0	0
T92	1424	0	0	0
T94	0	8	0	0
T103	0	23	0	0
T104	0	9	0	0
T178	0	6	0	0
T180	0	13	0	0
T181	0	5	0	0
T182	0	8	0	0
T183	0	9	0	0
T184	0	19	0	0
T185	2337	0	0	0
T186	1098	0	0	0
T187	21060	0	0	0
T188	6205	0	0	0
T189	338162	0	0	0