Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1201662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1428457

1

T1

253

T8

39

T9

211

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2289189	1			T1	278		T8	156		T9	268
values[0x0]	169487	1			T1	77		T9	50		T4	978
values[0x1]	171443	1			T1	67		T9	45		T4	893

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	952268	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1677851

1

T1

289

T8

75

T9

240

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9381	1			T50	12		T42	28		T44	11
valid_sources[0x01]	7733	1			T8	1		T9	4		T4	40
valid_sources[0x02]	11888	1			T8	1		T4	32		T11	21
valid_sources[0x03]	13623	1			T4	30		T11	14		T14	1
valid_sources[0x04]	7842	1			T1	1		T9	2		T4	16
valid_sources[0x05]	8212	1			T4	61		T50	3		T42	24
valid_sources[0x06]	7297	1			T1	4		T50	7		T42	47
valid_sources[0x07]	9770	1			T1	7		T4	7		T11	1
valid_sources[0x08]	7708	1			T1	1		T8	2		T4	102
valid_sources[0x09]	14194	1			T8	1		T14	5		T50	2
valid_sources[0x0a]	10738	1			T8	1		T4	39		T11	22
valid_sources[0x0b]	7702	1			T8	1		T4	177		T11	2
valid_sources[0x0c]	7571	1			T9	5		T4	27		T14	9
valid_sources[0x0d]	7943	1			T14	1		T50	3		T42	23
valid_sources[0x0e]	9206	1			T8	1		T4	41		T11	4
valid_sources[0x0f]	9596	1			T1	2		T8	2		T4	10
valid_sources[0x10]	7852	1			T1	4		T4	7		T11	11
valid_sources[0x11]	8861	1			T11	8		T14	1		T50	1
valid_sources[0x12]	7688	1			T11	1		T14	5		T50	3
valid_sources[0x13]	11869	1			T8	1		T9	1		T4	166
valid_sources[0x14]	8981	1			T4	60		T11	5		T14	2
valid_sources[0x15]	7816	1			T1	6		T8	1		T4	87
valid_sources[0x16]	8206	1			T1	1		T4	125		T11	7
valid_sources[0x17]	8128	1			T4	184		T14	5		T50	3
valid_sources[0x18]	7242	1			T8	1		T4	13		T11	17
valid_sources[0x19]	10531	1			T8	1		T4	89		T50	2
valid_sources[0x1a]	8459	1			T1	4		T8	1		T4	150
valid_sources[0x1b]	9421	1			T1	5		T8	1		T9	2
valid_sources[0x1c]	8809	1			T1	1		T8	1		T14	2
valid_sources[0x1d]	9586	1			T1	3		T8	1		T4	208
valid_sources[0x1e]	7338	1			T4	21		T11	2		T14	4
valid_sources[0x1f]	38088	1			T1	6		T4	30		T50	5
valid_sources[0x20]	8374	1			T8	1		T9	3		T11	3
valid_sources[0x21]	7710	1			T1	5		T8	2		T11	1
valid_sources[0x22]	8623	1			T8	2		T4	13		T50	6
valid_sources[0x23]	8331	1			T1	1		T50	13		T42	30
valid_sources[0x24]	9043	1			T1	2		T50	2		T42	32
valid_sources[0x25]	7645	1			T8	2		T9	4		T10	1
valid_sources[0x26]	9041	1			T11	4		T14	1		T50	7
valid_sources[0x27]	10652	1			T1	1		T4	149		T11	17
valid_sources[0x28]	7630	1			T1	1		T4	38		T64	1
valid_sources[0x29]	7372	1			T1	2		T4	47		T50	1
valid_sources[0x2a]	11180	1			T1	2		T4	25		T11	2
valid_sources[0x2b]	9312	1			T1	5		T9	2		T50	4
valid_sources[0x2c]	24109	1			T8	1		T4	6		T11	18
valid_sources[0x2d]	10640	1			T1	2		T8	1		T4	12
valid_sources[0x2e]	7555	1			T4	10		T14	1		T42	28
valid_sources[0x2f]	7809	1			T8	1		T11	5		T14	4
valid_sources[0x30]	11652	1			T8	1		T11	1		T14	3
valid_sources[0x31]	7703	1			T1	3		T8	1		T9	1
valid_sources[0x32]	7678	1			T1	4		T4	42		T11	5
valid_sources[0x33]	7484	1			T8	1		T4	55		T14	3
valid_sources[0x34]	8084	1			T1	5		T4	49		T11	8
valid_sources[0x35]	7795	1			T8	1		T42	49		T44	4
valid_sources[0x36]	8695	1			T1	1		T8	1		T4	124
valid_sources[0x37]	7889	1			T1	2		T8	2		T9	5
valid_sources[0x38]	64677	1			T4	15		T14	9		T42	28
valid_sources[0x39]	8180	1			T1	1		T8	1		T11	5
valid_sources[0x3a]	10013	1			T1	3		T50	3		T42	24
valid_sources[0x3b]	8121	1			T1	7		T8	1		T9	16
valid_sources[0x3c]	45089	1			T1	6		T8	1		T9	1
valid_sources[0x3d]	7699	1			T1	3		T8	2		T4	41
valid_sources[0x3e]	37713	1			T8	2		T50	9		T42	26
valid_sources[0x3f]	7219	1			T11	3		T50	5		T42	38
valid_sources[0x40]	8600	1			T4	37		T14	1		T50	3
valid_sources[0x41]	8077	1			T50	4		T42	34		T44	7
valid_sources[0x42]	7569	1			T1	6		T8	1		T9	3
valid_sources[0x43]	8251	1			T1	3		T8	1		T4	28
valid_sources[0x44]	8192	1			T8	2		T4	142		T11	11
valid_sources[0x45]	10554	1			T1	1		T4	123		T14	4
valid_sources[0x46]	10178	1			T8	1		T11	10		T50	4
valid_sources[0x47]	7349	1			T1	3		T4	16		T14	2
valid_sources[0x48]	7358	1			T50	5		T42	41		T44	2
valid_sources[0x49]	8589	1			T1	3		T8	1		T11	8
valid_sources[0x4a]	7438	1			T14	7		T50	10		T42	22
valid_sources[0x4b]	55511	1			T1	1		T4	82		T11	13
valid_sources[0x4c]	7505	1			T4	60		T50	5		T42	31
valid_sources[0x4d]	7753	1			T4	1		T11	1		T50	1
valid_sources[0x4e]	7725	1			T1	1		T8	1		T4	5
valid_sources[0x4f]	9986	1			T1	5		T8	1		T4	13
valid_sources[0x50]	7729	1			T1	2		T8	4		T4	2
valid_sources[0x51]	7561	1			T1	2		T8	2		T4	66
valid_sources[0x52]	10460	1			T1	4		T8	1		T14	1
valid_sources[0x53]	8481	1			T1	2		T8	1		T4	15
valid_sources[0x54]	8599	1			T4	22		T11	7		T64	1
valid_sources[0x55]	8690	1			T8	1		T14	3		T50	7
valid_sources[0x56]	20423	1			T4	88		T11	8		T64	2
valid_sources[0x57]	18322	1			T1	2		T8	1		T4	124
valid_sources[0x58]	8641	1			T1	1		T8	1		T11	17
valid_sources[0x59]	7869	1			T1	3		T9	5		T4	19
valid_sources[0x5a]	7648	1			T42	23		T44	5		T61	4
valid_sources[0x5b]	8908	1			T1	4		T8	1		T11	4
valid_sources[0x5c]	8221	1			T4	90		T50	2		T42	31
valid_sources[0x5d]	7852	1			T8	1		T4	61		T50	4
valid_sources[0x5e]	8754	1			T1	1		T4	66		T11	6
valid_sources[0x5f]	7607	1			T1	2		T8	1		T9	1
valid_sources[0x60]	9682	1			T8	1		T9	5		T11	21
valid_sources[0x61]	9700	1			T1	2		T8	1		T4	119
valid_sources[0x62]	21789	1			T1	3		T8	1		T4	72
valid_sources[0x63]	7401	1			T1	1		T8	1		T4	3
valid_sources[0x64]	7999	1			T11	1		T14	1		T50	4
valid_sources[0x65]	9621	1			T8	1		T4	3		T11	15
valid_sources[0x66]	7702	1			T1	1		T8	1		T4	29
valid_sources[0x67]	7956	1			T1	3		T9	25		T4	15
valid_sources[0x68]	13811	1			T1	1		T8	1		T4	33
valid_sources[0x69]	7781	1			T8	1		T9	1		T4	90
valid_sources[0x6a]	8584	1			T4	186		T11	4		T14	8
valid_sources[0x6b]	8910	1			T1	3		T9	3		T4	2
valid_sources[0x6c]	8230	1			T4	37		T50	1		T42	25
valid_sources[0x6d]	9035	1			T1	4		T9	3		T4	147
valid_sources[0x6e]	7496	1			T8	3		T9	1		T4	32
valid_sources[0x6f]	7202	1			T1	7		T9	8		T4	86
valid_sources[0x70]	13206	1			T14	1		T50	4		T42	32
valid_sources[0x71]	7819	1			T1	2		T4	36		T11	4
valid_sources[0x72]	7541	1			T1	4		T11	3		T50	5
valid_sources[0x73]	7853	1			T1	5		T8	1		T4	151
valid_sources[0x74]	7997	1			T4	88		T11	7		T14	2
valid_sources[0x75]	8685	1			T1	3		T8	1		T4	57
valid_sources[0x76]	8556	1			T1	1		T8	1		T4	38
valid_sources[0x77]	7742	1			T8	1		T50	3		T42	41
valid_sources[0x78]	77392	1			T4	56		T11	13		T64	1
valid_sources[0x79]	7412	1			T9	3		T4	4		T50	3
valid_sources[0x7a]	7620	1			T1	2		T4	32		T11	12
valid_sources[0x7b]	10206	1			T4	17		T11	2		T14	2
valid_sources[0x7c]	8369	1			T1	4		T9	3		T4	19
valid_sources[0x7d]	24793	1			T1	3		T4	36		T11	25
valid_sources[0x7e]	7910	1			T50	1		T42	20		T44	4
valid_sources[0x7f]	7272	1			T1	1		T14	2		T50	6
valid_sources[0x80]	7792	1			T8	3		T9	1		T11	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1134016

1

T1

123

T8

39

T9

127

values[0x0]

all_enables

biggest_size

147601

1

T1

69

T9

43

T4

842

values[0x1]

all_enables

biggest_size

146840

1

T1

61

T9

41

T4

800