Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	86057092	26193	0	0
claim_transition_if_regwen_rd_A	86057092	2690	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86057092	26193	0	0
T4	158766	1	0	0
T10	1486	0	0	0
T11	32417	0	0	0
T12	39821	0	0	0
T13	26262	0	0	0
T14	2396	0	0	0
T15	194559	0	0	0
T16	163250	0	0	0
T49	0	1	0	0
T50	26532	0	0	0
T64	1652	0	0	0
T74	0	6	0	0
T88	0	9	0	0
T89	0	7	0	0
T144	0	4	0	0
T145	0	8	0	0
T146	0	3	0	0
T147	0	1	0	0
T148	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86057092	2690	0	0
T49	245029	22	0	0
T72	53605	0	0	0
T80	5715	0	0	0
T97	0	55	0	0
T102	0	18	0	0
T103	0	3	0	0
T110	0	12	0	0
T120	0	16	0	0
T146	0	12	0	0
T148	0	5	0	0
T149	0	7	0	0
T150	0	9	0	0
T151	32669	0	0	0
T152	10889	0	0	0
T153	4810	0	0	0
T154	19891	0	0	0
T155	20188	0	0	0
T156	43732	0	0	0
T157	5888	0	0	0