Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3316751	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3761909

1

T1

838

T2

256

T3

727

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6383718	1			T1	689		T2	188		T3	736
values[0x0]	346745	1			T1	304		T2	119		T3	223
values[0x1]	348197	1			T1	360		T2	89		T3	217

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2634102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4444558

1

T1

987

T2

290

T3

832

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21453	1			T1	6		T10	38		T19	5
valid_sources[0x01]	21036	1			T10	9		T19	25		T68	8
valid_sources[0x02]	21420	1			T1	9		T10	17		T12	8
valid_sources[0x03]	21100	1			T1	14		T10	17		T19	3
valid_sources[0x04]	20950	1			T1	11		T10	10		T12	1
valid_sources[0x05]	20960	1			T1	4		T10	7		T68	12
valid_sources[0x06]	28741	1			T1	3		T10	18		T14	1
valid_sources[0x07]	26064	1			T1	8		T10	7		T12	5
valid_sources[0x08]	21323	1			T1	7		T10	1		T19	15
valid_sources[0x09]	24549	1			T1	5		T66	6		T68	5
valid_sources[0x0a]	21907	1			T1	9		T10	2		T12	5
valid_sources[0x0b]	21346	1			T1	7		T10	8		T66	2
valid_sources[0x0c]	21992	1			T1	8		T10	1		T19	12
valid_sources[0x0d]	21710	1			T1	1		T10	6		T19	21
valid_sources[0x0e]	22522	1			T1	6		T10	8		T19	1
valid_sources[0x0f]	20579	1			T1	3		T10	16		T12	6
valid_sources[0x10]	22907	1			T1	8		T10	16		T19	9
valid_sources[0x11]	34208	1			T1	6		T10	1		T12	2
valid_sources[0x12]	40568	1			T1	6		T10	3		T12	3
valid_sources[0x13]	36954	1			T1	6		T65	1		T66	1
valid_sources[0x14]	21467	1			T1	5		T10	6		T65	3
valid_sources[0x15]	22305	1			T1	3		T10	33		T12	4
valid_sources[0x16]	22251	1			T1	4		T10	11		T19	25
valid_sources[0x17]	20692	1			T1	6		T10	8		T68	10
valid_sources[0x18]	20463	1			T1	6		T10	5		T12	1
valid_sources[0x19]	20890	1			T1	5		T66	2		T68	7
valid_sources[0x1a]	21663	1			T1	6		T10	5		T66	4
valid_sources[0x1b]	21941	1			T1	8		T10	4		T11	962
valid_sources[0x1c]	21667	1			T1	11		T10	4		T68	11
valid_sources[0x1d]	21292	1			T1	4		T10	2		T66	2
valid_sources[0x1e]	20890	1			T1	7		T10	2		T66	2
valid_sources[0x1f]	22414	1			T1	1		T66	6		T68	7
valid_sources[0x20]	22419	1			T1	4		T10	10		T19	15
valid_sources[0x21]	21470	1			T1	3		T10	1		T68	5
valid_sources[0x22]	21242	1			T1	3		T10	5		T14	1
valid_sources[0x23]	20810	1			T1	9		T68	12		T93	1
valid_sources[0x24]	20759	1			T1	4		T10	6		T66	1
valid_sources[0x25]	21442	1			T1	4		T10	16		T14	2
valid_sources[0x26]	21501	1			T1	3		T14	1		T66	1
valid_sources[0x27]	37620	1			T1	5		T10	12		T19	12
valid_sources[0x28]	22947	1			T1	6		T10	3		T12	6
valid_sources[0x29]	24811	1			T1	12		T10	3		T19	20
valid_sources[0x2a]	22543	1			T1	5		T10	6		T12	6
valid_sources[0x2b]	25773	1			T1	6		T10	11		T65	10
valid_sources[0x2c]	20379	1			T1	4		T19	6		T66	1
valid_sources[0x2d]	28178	1			T1	11		T10	16		T19	8
valid_sources[0x2e]	26314	1			T1	2		T10	7		T14	1
valid_sources[0x2f]	21455	1			T1	9		T10	2		T65	1
valid_sources[0x30]	33480	1			T1	4		T68	5		T48	7
valid_sources[0x31]	20446	1			T1	8		T10	8		T12	2
valid_sources[0x32]	22146	1			T1	5		T10	3		T66	1
valid_sources[0x33]	22070	1			T1	6		T10	2		T19	18
valid_sources[0x34]	24668	1			T10	11		T12	1		T68	5
valid_sources[0x35]	22951	1			T1	10		T10	9		T65	1
valid_sources[0x36]	26549	1			T1	3		T10	3		T12	4
valid_sources[0x37]	21430	1			T1	7		T10	7		T68	4
valid_sources[0x38]	28707	1			T1	4		T10	3		T12	6
valid_sources[0x39]	21246	1			T1	5		T10	8		T12	2
valid_sources[0x3a]	35957	1			T1	4		T10	8		T68	7
valid_sources[0x3b]	31303	1			T1	8		T10	4		T19	2
valid_sources[0x3c]	32578	1			T1	4		T10	25		T12	2
valid_sources[0x3d]	20874	1			T1	6		T10	2		T66	3
valid_sources[0x3e]	22927	1			T1	6		T10	5		T12	5
valid_sources[0x3f]	21393	1			T1	8		T10	7		T14	1
valid_sources[0x40]	75826	1			T1	4		T10	3		T12	2
valid_sources[0x41]	21080	1			T1	8		T10	8		T68	8
valid_sources[0x42]	21251	1			T1	1		T10	23		T19	12
valid_sources[0x43]	20253	1			T1	5		T10	4		T12	6
valid_sources[0x44]	20886	1			T1	11		T10	10		T68	4
valid_sources[0x45]	107749	1			T1	4		T10	1		T19	6
valid_sources[0x46]	21381	1			T1	3		T10	9		T12	2
valid_sources[0x47]	24922	1			T1	2		T10	4		T14	1
valid_sources[0x48]	22465	1			T1	2		T10	9		T14	1
valid_sources[0x49]	22325	1			T1	5		T10	2		T19	11
valid_sources[0x4a]	21194	1			T1	4		T10	3		T19	4
valid_sources[0x4b]	21413	1			T1	1		T10	24		T13	1
valid_sources[0x4c]	21082	1			T1	6		T10	10		T66	11
valid_sources[0x4d]	21401	1			T1	2		T10	2		T68	5
valid_sources[0x4e]	23779	1			T1	4		T19	4		T65	3
valid_sources[0x4f]	23280	1			T1	1		T10	4		T68	3
valid_sources[0x50]	32423	1			T1	8		T10	4		T12	5
valid_sources[0x51]	66146	1			T1	9		T66	1		T68	5
valid_sources[0x52]	50813	1			T1	6		T10	31		T12	2
valid_sources[0x53]	21095	1			T1	1		T10	4		T65	2
valid_sources[0x54]	72238	1			T1	3		T10	2		T12	1
valid_sources[0x55]	20979	1			T1	4		T10	6		T19	3
valid_sources[0x56]	57373	1			T1	4		T10	1		T5	36556
valid_sources[0x57]	23072	1			T1	6		T10	18		T66	1
valid_sources[0x58]	27643	1			T1	9		T19	27		T68	14
valid_sources[0x59]	32162	1			T1	5		T10	17		T12	2
valid_sources[0x5a]	24228	1			T1	3		T10	29		T19	8
valid_sources[0x5b]	21545	1			T1	5		T65	2		T66	1
valid_sources[0x5c]	20719	1			T1	3		T12	6		T19	9
valid_sources[0x5d]	20899	1			T1	7		T10	8		T68	3
valid_sources[0x5e]	30610	1			T1	6		T12	2		T14	1
valid_sources[0x5f]	21196	1			T1	9		T10	9		T19	41
valid_sources[0x60]	22458	1			T1	6		T10	11		T68	4
valid_sources[0x61]	21595	1			T1	5		T19	29		T68	8
valid_sources[0x62]	22963	1			T1	5		T10	2		T66	2
valid_sources[0x63]	21156	1			T1	3		T10	3		T66	1
valid_sources[0x64]	22459	1			T1	6		T10	2		T68	5
valid_sources[0x65]	23185	1			T1	4		T10	5		T19	20
valid_sources[0x66]	39355	1			T1	9		T10	10		T66	3
valid_sources[0x67]	32791	1			T1	7		T10	10		T68	4
valid_sources[0x68]	21608	1			T1	14		T10	22		T68	5
valid_sources[0x69]	62991	1			T1	6		T10	2		T12	6
valid_sources[0x6a]	22012	1			T1	3		T10	22		T66	2
valid_sources[0x6b]	40408	1			T1	15		T2	396		T10	5
valid_sources[0x6c]	21091	1			T1	1		T10	2		T66	3
valid_sources[0x6d]	21862	1			T1	6		T10	1		T66	5
valid_sources[0x6e]	21037	1			T1	3		T10	21		T12	1
valid_sources[0x6f]	21120	1			T1	7		T10	22		T12	8
valid_sources[0x70]	20598	1			T1	5		T10	11		T12	1
valid_sources[0x71]	23952	1			T1	7		T10	12		T12	5
valid_sources[0x72]	20924	1			T1	7		T10	5		T19	2
valid_sources[0x73]	27416	1			T1	10		T10	8		T12	8
valid_sources[0x74]	21486	1			T1	4		T10	12		T66	2
valid_sources[0x75]	21453	1			T1	8		T10	5		T12	3
valid_sources[0x76]	20765	1			T1	7		T10	7		T12	8
valid_sources[0x77]	110089	1			T1	8		T10	3		T12	3
valid_sources[0x78]	123548	1			T1	7		T10	6		T19	5
valid_sources[0x79]	22870	1			T1	3		T10	17		T12	2
valid_sources[0x7a]	22806	1			T1	7		T10	8		T12	2
valid_sources[0x7b]	21860	1			T1	4		T10	5		T68	10
valid_sources[0x7c]	42445	1			T1	4		T10	8		T12	2
valid_sources[0x7d]	21888	1			T1	4		T10	1		T19	11
valid_sources[0x7e]	42581	1			T1	3		T19	5		T66	2
valid_sources[0x7f]	128022	1			T1	4		T10	2		T12	2
valid_sources[0x80]	23530	1			T1	3		T10	18		T12	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3163439

1

T1

261

T2

84

T3

344

values[0x0]

all_enables

biggest_size

300163

1

T1

267

T2

96

T3

195

values[0x1]

all_enables

biggest_size

298307

1

T1

310

T2

76

T3

188