Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	218822363	29094	0	0
claim_transition_if_regwen_rd_A	218822363	2572	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218822363	29094	0	0
T5	150971	3	0	0
T6	21516	0	0	0
T14	1096	0	0	0
T18	0	5	0	0
T19	30051	0	0	0
T21	6474	0	0	0
T37	0	1	0	0
T42	0	2	0	0
T61	0	7	0	0
T64	0	1	0	0
T65	3378	0	0	0
T66	8959	0	0	0
T67	1264	0	0	0
T68	27645	0	0	0
T74	2040	0	0	0
T124	0	2	0	0
T181	0	2	0	0
T182	0	3	0	0
T183	0	7	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218822363	2572	0	0
T8	24823	0	0	0
T9	29836	0	0	0
T18	252268	9	0	0
T24	68012	0	0	0
T33	92623	0	0	0
T34	27450	0	0	0
T35	18165	0	0	0
T42	0	5	0	0
T46	0	7	0	0
T59	136496	0	0	0
T124	0	7	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	5	0	0
T188	0	11	0	0
T189	0	9	0	0
T190	4884	0	0	0
T191	1105	0	0	0