Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1821955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2075236

1

T1

20643

T3

839

T8

568

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3513765	1			T1	40577		T3	721		T8	423
values[0x0]	191124	1			T1	145		T3	249		T8	205
values[0x1]	192302	1			T1	157		T3	287		T8	195

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1447507	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2449684

1

T1

24714

T3

932

T8

623

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14063	1			T1	178		T3	3		T9	2
valid_sources[0x01]	13855	1			T1	167		T3	10		T10	8
valid_sources[0x02]	11550	1			T1	137		T3	3		T10	4
valid_sources[0x03]	12762	1			T1	146		T3	6		T8	3
valid_sources[0x04]	13714	1			T1	155		T3	5		T8	1
valid_sources[0x05]	15092	1			T1	175		T3	4		T8	1
valid_sources[0x06]	13499	1			T1	174		T3	2		T10	7
valid_sources[0x07]	14147	1			T1	179		T3	4		T8	10
valid_sources[0x08]	12075	1			T1	154		T3	10		T8	13
valid_sources[0x09]	11919	1			T1	163		T3	3		T9	1
valid_sources[0x0a]	40470	1			T1	213		T3	1		T8	5
valid_sources[0x0b]	11177	1			T1	156		T3	6		T8	6
valid_sources[0x0c]	12407	1			T1	180		T3	10		T9	2
valid_sources[0x0d]	12100	1			T1	154		T3	2		T8	13
valid_sources[0x0e]	12086	1			T1	176		T3	5		T9	1
valid_sources[0x0f]	11976	1			T1	168		T3	5		T8	8
valid_sources[0x10]	12458	1			T1	143		T3	8		T9	1
valid_sources[0x11]	11576	1			T1	170		T3	3		T9	2
valid_sources[0x12]	11869	1			T1	206		T3	6		T8	5
valid_sources[0x13]	11475	1			T1	163		T3	6		T8	2
valid_sources[0x14]	11496	1			T1	195		T3	6		T9	1
valid_sources[0x15]	12833	1			T1	170		T3	6		T8	3
valid_sources[0x16]	11430	1			T1	153		T3	7		T8	1
valid_sources[0x17]	12300	1			T1	194		T3	7		T9	1
valid_sources[0x18]	13114	1			T1	149		T3	6		T8	12
valid_sources[0x19]	12022	1			T1	160		T3	8		T9	4
valid_sources[0x1a]	13648	1			T1	179		T3	6		T9	3
valid_sources[0x1b]	16335	1			T1	137		T3	7		T9	1
valid_sources[0x1c]	11549	1			T1	180		T3	8		T8	4
valid_sources[0x1d]	11678	1			T1	126		T3	2		T9	3
valid_sources[0x1e]	11972	1			T1	168		T3	3		T9	1
valid_sources[0x1f]	13963	1			T1	145		T3	2		T8	1
valid_sources[0x20]	13438	1			T1	133		T3	6		T9	2
valid_sources[0x21]	11836	1			T1	162		T3	3		T8	14
valid_sources[0x22]	13251	1			T1	182		T3	3		T9	2
valid_sources[0x23]	11378	1			T1	184		T8	4		T9	2
valid_sources[0x24]	11142	1			T1	178		T3	6		T8	2
valid_sources[0x25]	15871	1			T1	173		T3	10		T8	1
valid_sources[0x26]	13802	1			T1	155		T3	5		T8	4
valid_sources[0x27]	11285	1			T1	153		T3	4		T9	2
valid_sources[0x28]	14378	1			T1	186		T9	4		T10	8
valid_sources[0x29]	30070	1			T1	121		T3	6		T9	1
valid_sources[0x2a]	13782	1			T1	171		T3	7		T8	1
valid_sources[0x2b]	11562	1			T1	124		T8	4		T9	1
valid_sources[0x2c]	11791	1			T1	161		T3	3		T8	27
valid_sources[0x2d]	11717	1			T1	159		T3	7		T10	5
valid_sources[0x2e]	14147	1			T1	141		T3	11		T9	2
valid_sources[0x2f]	37057	1			T1	136		T3	6		T8	1
valid_sources[0x30]	12401	1			T1	149		T3	6		T9	1
valid_sources[0x31]	72567	1			T1	149		T3	3		T8	20
valid_sources[0x32]	12058	1			T1	119		T3	4		T8	8
valid_sources[0x33]	16895	1			T1	175		T3	6		T9	1
valid_sources[0x34]	11837	1			T1	128		T3	4		T8	19
valid_sources[0x35]	11411	1			T1	132		T3	8		T9	2
valid_sources[0x36]	112953	1			T1	172		T3	8		T8	4
valid_sources[0x37]	12113	1			T1	178		T3	3		T9	1
valid_sources[0x38]	11697	1			T1	152		T3	5		T9	1
valid_sources[0x39]	12536	1			T1	156		T3	4		T8	1
valid_sources[0x3a]	12355	1			T1	132		T3	8		T8	7
valid_sources[0x3b]	13313	1			T1	164		T3	5		T9	1
valid_sources[0x3c]	14118	1			T1	119		T3	5		T8	6
valid_sources[0x3d]	11345	1			T1	156		T3	3		T10	3
valid_sources[0x3e]	12007	1			T1	192		T3	1		T8	3
valid_sources[0x3f]	14481	1			T1	137		T3	8		T8	1
valid_sources[0x40]	13449	1			T1	148		T3	3		T8	7
valid_sources[0x41]	78541	1			T1	140		T3	6		T8	1
valid_sources[0x42]	34486	1			T1	158		T3	1		T9	2
valid_sources[0x43]	11933	1			T1	136		T3	5		T9	1
valid_sources[0x44]	12091	1			T1	128		T3	9		T8	5
valid_sources[0x45]	12028	1			T1	198		T8	4		T9	1
valid_sources[0x46]	11495	1			T1	151		T3	5		T8	17
valid_sources[0x47]	12139	1			T1	182		T3	5		T10	6
valid_sources[0x48]	19259	1			T1	210		T3	4		T9	3
valid_sources[0x49]	11545	1			T1	152		T3	7		T9	1
valid_sources[0x4a]	19901	1			T1	184		T3	6		T9	3
valid_sources[0x4b]	11532	1			T1	112		T3	6		T8	10
valid_sources[0x4c]	19187	1			T1	182		T3	4		T8	9
valid_sources[0x4d]	42415	1			T1	162		T3	7		T8	10
valid_sources[0x4e]	24134	1			T1	184		T3	3		T8	3
valid_sources[0x4f]	12167	1			T1	182		T3	12		T8	3
valid_sources[0x50]	11570	1			T1	152		T3	6		T8	16
valid_sources[0x51]	11543	1			T1	180		T3	5		T9	2
valid_sources[0x52]	11964	1			T1	170		T3	8		T8	8
valid_sources[0x53]	11632	1			T1	172		T3	7		T8	1
valid_sources[0x54]	12022	1			T1	139		T3	6		T8	5
valid_sources[0x55]	12946	1			T1	165		T3	5		T8	5
valid_sources[0x56]	11779	1			T1	185		T3	5		T9	2
valid_sources[0x57]	12174	1			T1	143		T3	8		T9	6
valid_sources[0x58]	12144	1			T1	154		T3	5		T8	2
valid_sources[0x59]	11753	1			T1	161		T3	3		T8	3
valid_sources[0x5a]	15256	1			T1	187		T3	9		T9	1
valid_sources[0x5b]	12165	1			T1	188		T3	3		T8	6
valid_sources[0x5c]	26452	1			T1	118		T3	3		T8	2
valid_sources[0x5d]	12296	1			T1	170		T3	5		T8	6
valid_sources[0x5e]	46764	1			T1	140		T3	1		T8	3
valid_sources[0x5f]	12903	1			T1	197		T3	1		T10	4
valid_sources[0x60]	14207	1			T1	160		T3	2		T8	3
valid_sources[0x61]	11796	1			T1	160		T3	2		T9	3
valid_sources[0x62]	14326	1			T1	122		T3	9		T8	4
valid_sources[0x63]	11391	1			T1	181		T3	6		T9	1
valid_sources[0x64]	11458	1			T1	151		T3	6		T8	5
valid_sources[0x65]	12307	1			T1	145		T3	12		T8	4
valid_sources[0x66]	11912	1			T1	202		T3	5		T8	16
valid_sources[0x67]	12368	1			T1	156		T8	2		T10	3
valid_sources[0x68]	11751	1			T1	169		T3	7		T9	1
valid_sources[0x69]	11840	1			T1	169		T3	1		T8	6
valid_sources[0x6a]	154364	1			T1	152		T3	12		T8	11
valid_sources[0x6b]	17813	1			T1	205		T3	5		T8	4
valid_sources[0x6c]	11957	1			T1	164		T3	3		T8	2
valid_sources[0x6d]	11733	1			T1	140		T3	2		T9	1
valid_sources[0x6e]	12270	1			T1	151		T3	6		T10	2
valid_sources[0x6f]	11887	1			T1	166		T3	7		T8	5
valid_sources[0x70]	11914	1			T1	183		T3	3		T9	1
valid_sources[0x71]	11416	1			T1	193		T3	11		T8	1
valid_sources[0x72]	11754	1			T1	130		T3	4		T9	1
valid_sources[0x73]	11750	1			T1	135		T3	6		T8	9
valid_sources[0x74]	11448	1			T1	164		T3	3		T9	1
valid_sources[0x75]	12120	1			T1	145		T3	6		T8	2
valid_sources[0x76]	11989	1			T1	148		T3	5		T9	2
valid_sources[0x77]	11623	1			T1	153		T3	2		T9	1
valid_sources[0x78]	11799	1			T1	153		T3	3		T9	1
valid_sources[0x79]	14072	1			T1	153		T3	3		T8	16
valid_sources[0x7a]	12141	1			T1	137		T3	3		T9	3
valid_sources[0x7b]	11585	1			T1	152		T3	4		T9	2
valid_sources[0x7c]	11683	1			T1	176		T3	2		T8	5
valid_sources[0x7d]	11225	1			T1	145		T3	7		T9	5
valid_sources[0x7e]	11709	1			T1	162		T3	4		T9	3
valid_sources[0x7f]	11442	1			T1	136		T3	7		T9	2
valid_sources[0x80]	18544	1			T1	154		T3	5		T8	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1743677

1

T1

20386

T3

377

T8

222

values[0x0]

all_enables

biggest_size

166721

1

T1

122

T3

216

T8

179

values[0x1]

all_enables

biggest_size

164838

1

T1

135

T3

246

T8

167