Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117185741	29746	0	0
claim_transition_if_regwen_rd_A	117185741	2985	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117185741	29746	0	0
T34	1351	0	0	0
T39	300202	10	0	0
T44	0	3	0	0
T46	0	13	0	0
T70	1453	0	0	0
T90	349726	2	0	0
T163	0	7	0	0
T164	0	1	0	0
T165	0	9	0	0
T166	0	4	0	0
T167	0	1	0	0
T168	0	6	0	0
T169	39861	0	0	0
T170	65928	0	0	0
T171	697430	0	0	0
T172	35346	0	0	0
T173	8060	0	0	0
T174	7773	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117185741	2985	0	0
T49	369142	17	0	0
T74	5121	0	0	0
T105	0	3	0	0
T109	0	84	0	0
T113	0	22	0	0
T116	0	2	0	0
T138	0	1	0	0
T175	0	5	0	0
T176	0	4	0	0
T177	0	13	0	0
T178	0	2	0	0
T179	27226	0	0	0
T180	3552	0	0	0
T181	28719	0	0	0
T182	29812	0	0	0
T183	1090	0	0	0
T184	105417	0	0	0
T185	871	0	0	0
T186	1743	0	0	0