Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3185827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3616724

1

T3

551

T10

198

T11

262

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6131337	1			T3	413		T10	171		T11	262
values[0x0]	333932	1			T3	212		T10	75		T11	77
values[0x1]	337282	1			T3	188		T10	69		T11	77

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2528691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4273860

1

T3

600

T10

218

T11

305

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18914	1			T3	8		T4	2		T13	8
valid_sources[0x01]	20398	1			T3	1		T12	1		T15	1
valid_sources[0x02]	75835	1			T12	1		T13	2		T45	2
valid_sources[0x03]	20955	1			T3	6		T11	3		T4	1
valid_sources[0x04]	20752	1			T3	11		T11	5		T12	3
valid_sources[0x05]	18343	1			T3	12		T12	1		T17	1
valid_sources[0x06]	20802	1			T3	3		T11	1		T12	4
valid_sources[0x07]	19732	1			T3	1		T12	2		T4	6
valid_sources[0x08]	19383	1			T3	1		T12	2		T45	1
valid_sources[0x09]	22041	1			T12	1		T17	3		T48	6
valid_sources[0x0a]	28698	1			T3	3		T12	2		T4	5
valid_sources[0x0b]	18834	1			T3	3		T11	3		T12	2
valid_sources[0x0c]	18540	1			T11	1		T12	1		T17	1
valid_sources[0x0d]	21683	1			T17	3		T48	8		T42	16
valid_sources[0x0e]	22409	1			T3	5		T12	1		T17	3
valid_sources[0x0f]	20463	1			T3	3		T12	1		T4	5
valid_sources[0x10]	26155	1			T3	3		T4	2		T48	9
valid_sources[0x11]	20979	1			T3	2		T11	1		T12	3
valid_sources[0x12]	93222	1			T3	7		T12	4		T4	3
valid_sources[0x13]	18898	1			T3	1		T12	4		T4	2
valid_sources[0x14]	19139	1			T3	1		T12	1		T48	6
valid_sources[0x15]	22780	1			T3	2		T12	2		T4	2
valid_sources[0x16]	18962	1			T3	4		T11	2		T12	4
valid_sources[0x17]	18855	1			T3	4		T11	8		T12	1
valid_sources[0x18]	19992	1			T11	5		T48	7		T50	4
valid_sources[0x19]	25906	1			T3	4		T12	3		T48	12
valid_sources[0x1a]	18556	1			T3	6		T12	3		T48	7
valid_sources[0x1b]	20580	1			T3	1		T11	3		T12	4
valid_sources[0x1c]	18594	1			T3	7		T11	1		T17	3
valid_sources[0x1d]	36379	1			T3	2		T11	23		T12	2
valid_sources[0x1e]	25025	1			T11	6		T12	1		T4	4
valid_sources[0x1f]	26211	1			T3	1		T12	3		T4	1
valid_sources[0x20]	18932	1			T3	4		T11	3		T12	1
valid_sources[0x21]	18929	1			T3	1		T12	2		T4	1
valid_sources[0x22]	19260	1			T12	2		T4	1		T17	1
valid_sources[0x23]	31397	1			T12	1		T4	3		T48	3
valid_sources[0x24]	18693	1			T3	9		T12	4		T4	3
valid_sources[0x25]	19332	1			T3	4		T45	3		T48	7
valid_sources[0x26]	19290	1			T3	1		T12	1		T4	1
valid_sources[0x27]	20931	1			T3	9		T12	3		T48	5
valid_sources[0x28]	21442	1			T3	3		T11	2		T17	2
valid_sources[0x29]	49943	1			T3	1		T11	4		T12	2
valid_sources[0x2a]	18826	1			T3	2		T12	1		T4	1
valid_sources[0x2b]	20541	1			T3	1		T12	3		T48	2
valid_sources[0x2c]	36531	1			T3	2		T12	2		T17	4
valid_sources[0x2d]	18980	1			T3	4		T12	1		T17	2
valid_sources[0x2e]	18619	1			T3	2		T11	6		T12	2
valid_sources[0x2f]	22722	1			T3	4		T12	2		T4	1
valid_sources[0x30]	19504	1			T3	3		T12	5		T4	2
valid_sources[0x31]	20856	1			T3	6		T12	1		T4	1
valid_sources[0x32]	20584	1			T12	3		T48	9		T50	1
valid_sources[0x33]	25346	1			T12	1		T17	1		T48	8
valid_sources[0x34]	20924	1			T3	11		T12	6		T4	2
valid_sources[0x35]	21470	1			T11	5		T12	6		T48	13
valid_sources[0x36]	18406	1			T12	2		T17	3		T48	4
valid_sources[0x37]	22612	1			T3	8		T11	3		T12	1
valid_sources[0x38]	29569	1			T3	10		T17	2		T48	6
valid_sources[0x39]	20744	1			T3	7		T12	1		T17	3
valid_sources[0x3a]	19220	1			T3	8		T12	3		T15	1
valid_sources[0x3b]	67610	1			T3	1		T11	1		T12	1
valid_sources[0x3c]	18835	1			T3	7		T12	1		T47	2
valid_sources[0x3d]	19635	1			T3	5		T12	2		T4	2
valid_sources[0x3e]	38773	1			T17	1		T48	8		T50	4
valid_sources[0x3f]	18624	1			T3	11		T4	1		T17	1
valid_sources[0x40]	28333	1			T3	3		T12	1		T4	5
valid_sources[0x41]	39037	1			T11	8		T48	4		T50	6
valid_sources[0x42]	19725	1			T11	8		T12	1		T4	1
valid_sources[0x43]	18856	1			T12	1		T17	1		T48	6
valid_sources[0x44]	46615	1			T3	7		T12	2		T4	1
valid_sources[0x45]	22064	1			T3	4		T12	1		T17	3
valid_sources[0x46]	18656	1			T12	3		T4	2		T17	4
valid_sources[0x47]	19613	1			T3	5		T12	2		T45	1
valid_sources[0x48]	19394	1			T3	9		T11	11		T12	4
valid_sources[0x49]	19717	1			T3	1		T12	4		T4	1
valid_sources[0x4a]	19157	1			T3	1		T11	6		T12	4
valid_sources[0x4b]	20152	1			T3	6		T11	2		T12	2
valid_sources[0x4c]	19879	1			T3	3		T12	2		T48	6
valid_sources[0x4d]	19026	1			T3	5		T11	2		T12	1
valid_sources[0x4e]	35500	1			T11	2		T12	2		T4	3
valid_sources[0x4f]	60162	1			T11	6		T12	1		T48	7
valid_sources[0x50]	21208	1			T3	12		T12	1		T4	2
valid_sources[0x51]	63415	1			T3	1		T12	1		T4	1
valid_sources[0x52]	19679	1			T3	5		T11	4		T12	2
valid_sources[0x53]	21491	1			T12	1		T13	4		T45	4
valid_sources[0x54]	20034	1			T3	2		T12	1		T48	6
valid_sources[0x55]	19184	1			T3	2		T12	2		T17	4
valid_sources[0x56]	18888	1			T3	3		T12	2		T48	14
valid_sources[0x57]	23548	1			T10	315		T12	1		T17	1
valid_sources[0x58]	19629	1			T3	6		T12	1		T4	1
valid_sources[0x59]	19710	1			T3	3		T11	6		T12	1
valid_sources[0x5a]	19840	1			T3	1		T11	2		T12	3
valid_sources[0x5b]	18993	1			T12	2		T4	1		T17	2
valid_sources[0x5c]	20747	1			T3	3		T11	4		T4	5
valid_sources[0x5d]	21101	1			T3	9		T12	2		T4	4
valid_sources[0x5e]	29433	1			T3	3		T12	3		T17	1
valid_sources[0x5f]	20471	1			T3	4		T17	2		T48	6
valid_sources[0x60]	20630	1			T3	3		T12	1		T4	1
valid_sources[0x61]	21403	1			T3	3		T4	1		T17	4
valid_sources[0x62]	18149	1			T3	5		T48	6		T50	6
valid_sources[0x63]	18494	1			T3	6		T12	2		T4	2
valid_sources[0x64]	118100	1			T3	3		T12	4		T4	2
valid_sources[0x65]	20961	1			T11	2		T45	1		T48	6
valid_sources[0x66]	21129	1			T3	1		T11	1		T13	1
valid_sources[0x67]	18704	1			T3	2		T4	1		T45	4
valid_sources[0x68]	21659	1			T3	9		T11	9		T45	3
valid_sources[0x69]	19480	1			T3	2		T17	2		T45	3
valid_sources[0x6a]	29830	1			T3	7		T12	2		T17	5
valid_sources[0x6b]	18918	1			T3	2		T11	7		T48	8
valid_sources[0x6c]	18908	1			T12	2		T4	2		T48	9
valid_sources[0x6d]	18778	1			T3	5		T11	1		T12	1
valid_sources[0x6e]	22807	1			T3	2		T11	10		T12	1
valid_sources[0x6f]	20634	1			T3	10		T12	5		T17	2
valid_sources[0x70]	27923	1			T3	4		T12	3		T17	2
valid_sources[0x71]	21368	1			T45	2		T48	10		T50	4
valid_sources[0x72]	31470	1			T3	3		T48	6		T50	3
valid_sources[0x73]	24520	1			T3	5		T12	1		T4	1
valid_sources[0x74]	19750	1			T3	1		T11	2		T12	3
valid_sources[0x75]	45115	1			T11	4		T12	1		T4	3
valid_sources[0x76]	19938	1			T3	6		T12	1		T17	1
valid_sources[0x77]	57729	1			T3	1		T12	1		T4	3
valid_sources[0x78]	22910	1			T3	8		T12	2		T4	6
valid_sources[0x79]	18511	1			T3	3		T4	2		T48	5
valid_sources[0x7a]	19063	1			T3	7		T11	8		T4	2
valid_sources[0x7b]	28950	1			T12	5		T15	1		T17	2
valid_sources[0x7c]	22122	1			T12	2		T4	3		T17	1
valid_sources[0x7d]	21845	1			T3	8		T48	6		T50	5
valid_sources[0x7e]	20457	1			T11	2		T12	3		T48	5
valid_sources[0x7f]	33617	1			T3	4		T15	1		T48	5
valid_sources[0x80]	21428	1			T12	1		T17	1		T48	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3038568

1

T3

196

T10

74

T11

132

values[0x0]

all_enables

biggest_size

289423

1

T3

194

T10

68

T11

66

values[0x1]

all_enables

biggest_size

288733

1

T3

161

T10

56

T11

64