Unified Coverage Report :: Module :: prim_alert_sender

Module Definition

dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tb.dut.gen_alert_tx[2].u_prim_alert_sender	100.00			100.00

Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T15,T100,T80	Yes	T15,T100,T80	INPUT
alert_req_i	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
alert_ack_o	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T15,T100,T80	Yes	T15,T100,T80	INPUT
alert_req_i	Yes	Yes	T10,T13,T17	Yes	T10,T13,T17	INPUT
alert_ack_o	Yes	Yes	T10,T13,T17	Yes	T10,T13,T17	OUTPUT
alert_state_o	Yes	Yes	T10,T13,T17	Yes	T10,T13,T17	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T10,T13,T15	Yes	T10,T13,T15	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T10,T13,T15	Yes	T10,T13,T15	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[1].u_prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T15,T100,T80	Yes	T15,T100,T80	INPUT
alert_req_i	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	INPUT
alert_ack_o	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
alert_state_o	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_tx[2].u_prim_alert_sender

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	20	20	100.00
Total Bits 0->1	10	10	100.00
Total Bits 1->0	10	10	100.00


Ports	10	10	100.00
Port Bits	20	20	100.00
Port Bits 0->1	10	10	100.00
Port Bits 1->0	10	10	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T15,T100,T80	Yes	T15,T100,T80	INPUT
alert_req_i	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
alert_ack_o	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
alert_state_o	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T15,T100,T80	Yes	T15,T100,T80	INPUT
alert_rx_i.ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i.ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T15,T100,T80	Yes	T15,T100,T80	OUTPUT

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%