Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	203981615	26702	0	0
claim_transition_if_regwen_rd_A	203981615	3473	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203981615	26702	0	0
T19	268018	12	0	0
T20	110814	4	0	0
T21	243994	0	0	0
T54	0	7	0	0
T76	32672	0	0	0
T78	1967	0	0	0
T79	2983	0	0	0
T97	0	7	0	0
T191	0	6	0	0
T195	0	1	0	0
T196	0	3	0	0
T197	0	9	0	0
T198	0	5	0	0
T199	0	2	0	0
T200	17863	0	0	0
T201	94985	0	0	0
T202	22435	0	0	0
T203	7363	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	203981615	3473	0	0
T141	0	35	0	0
T146	0	9	0	0
T155	0	14	0	0
T204	224702	2	0	0
T205	0	7	0	0
T206	0	7	0	0
T207	0	7	0	0
T208	0	6	0	0
T209	0	7	0	0
T210	0	8	0	0
T211	25303	0	0	0
T212	93099	0	0	0
T213	280226	0	0	0
T214	35122	0	0	0
T215	28141	0	0	0
T216	1335	0	0	0
T217	31885	0	0	0
T218	1528	0	0	0
T219	170463	0	0	0