Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2477792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2895114

1

T2

2140

T3

951

T9

874

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4724577	1			T2	2401		T3	792		T9	755
values[0x0]	323277	1			T2	619		T3	330		T9	284
values[0x1]	325052	1			T2	603		T3	326		T9	300

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1965132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3407774

1

T2

2504

T3

1079

T9

975

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17154	1			T2	7		T3	4		T9	7
valid_sources[0x01]	16307	1			T2	54		T3	4		T9	5
valid_sources[0x02]	16277	1			T2	30		T3	1		T9	8
valid_sources[0x03]	21391	1			T2	17		T3	7		T9	6
valid_sources[0x04]	16765	1			T2	9		T3	4		T9	11
valid_sources[0x05]	16045	1			T2	13		T3	7		T9	6
valid_sources[0x06]	16455	1			T3	6		T9	4		T12	9
valid_sources[0x07]	16900	1			T2	23		T3	8		T9	5
valid_sources[0x08]	16139	1			T3	6		T9	8		T12	16
valid_sources[0x09]	34107	1			T2	26		T3	5		T9	6
valid_sources[0x0a]	17644	1			T2	38		T3	5		T9	6
valid_sources[0x0b]	20385	1			T2	2		T3	5		T9	5
valid_sources[0x0c]	17191	1			T2	14		T3	1		T9	5
valid_sources[0x0d]	16629	1			T2	4		T3	9		T9	2
valid_sources[0x0e]	16742	1			T3	2		T9	4		T12	11
valid_sources[0x0f]	24931	1			T2	14		T3	9		T9	9
valid_sources[0x10]	17087	1			T3	8		T9	4		T12	22
valid_sources[0x11]	22612	1			T3	7		T9	3		T12	6
valid_sources[0x12]	17440	1			T3	10		T9	11		T12	10
valid_sources[0x13]	15281	1			T3	6		T9	3		T13	4
valid_sources[0x14]	17152	1			T3	1		T9	4		T12	5
valid_sources[0x15]	18618	1			T3	2		T9	8		T12	6
valid_sources[0x16]	17029	1			T2	2		T3	4		T9	6
valid_sources[0x17]	17482	1			T2	3		T3	4		T9	5
valid_sources[0x18]	18426	1			T2	16		T3	4		T9	10
valid_sources[0x19]	16496	1			T2	3		T3	5		T9	6
valid_sources[0x1a]	24278	1			T2	5		T9	3		T13	7
valid_sources[0x1b]	17564	1			T2	4		T9	11		T12	19
valid_sources[0x1c]	18980	1			T2	1		T3	4		T9	5
valid_sources[0x1d]	16160	1			T2	24		T3	3		T9	3
valid_sources[0x1e]	15805	1			T3	4		T9	9		T12	13
valid_sources[0x1f]	16153	1			T3	4		T9	9		T12	8
valid_sources[0x20]	22909	1			T2	7		T3	8		T9	6
valid_sources[0x21]	30921	1			T2	7		T3	7		T9	10
valid_sources[0x22]	19147	1			T3	5		T9	4		T12	14
valid_sources[0x23]	18386	1			T2	16		T3	10		T9	3
valid_sources[0x24]	18661	1			T2	28		T3	7		T9	3
valid_sources[0x25]	36916	1			T2	13		T3	3		T9	6
valid_sources[0x26]	17056	1			T2	6		T3	3		T9	5
valid_sources[0x27]	16039	1			T2	30		T3	7		T9	6
valid_sources[0x28]	17201	1			T2	13		T3	3		T9	4
valid_sources[0x29]	18558	1			T2	21		T3	10		T9	8
valid_sources[0x2a]	16040	1			T2	47		T3	3		T9	3
valid_sources[0x2b]	85844	1			T2	10		T3	4		T9	6
valid_sources[0x2c]	15994	1			T2	3		T3	9		T9	3
valid_sources[0x2d]	18350	1			T2	21		T3	3		T9	3
valid_sources[0x2e]	17590	1			T2	11		T3	4		T9	6
valid_sources[0x2f]	16036	1			T3	7		T9	5		T12	2
valid_sources[0x30]	15789	1			T2	33		T3	11		T9	3
valid_sources[0x31]	16496	1			T2	6		T3	8		T9	3
valid_sources[0x32]	16509	1			T2	35		T3	4		T9	4
valid_sources[0x33]	16649	1			T2	1		T3	5		T9	1
valid_sources[0x34]	16332	1			T2	26		T3	5		T9	3
valid_sources[0x35]	16255	1			T2	3		T3	5		T9	10
valid_sources[0x36]	16690	1			T3	2		T9	4		T12	16
valid_sources[0x37]	19607	1			T2	8		T3	3		T9	3
valid_sources[0x38]	16929	1			T2	29		T3	6		T9	4
valid_sources[0x39]	16033	1			T2	16		T3	6		T9	5
valid_sources[0x3a]	16601	1			T2	7		T3	2		T9	10
valid_sources[0x3b]	20618	1			T2	11		T3	8		T9	7
valid_sources[0x3c]	16257	1			T3	4		T9	3		T12	8
valid_sources[0x3d]	18934	1			T2	8		T3	8		T9	2
valid_sources[0x3e]	27152	1			T3	6		T9	5		T13	4
valid_sources[0x3f]	17164	1			T3	4		T9	11		T12	18
valid_sources[0x40]	17957	1			T2	19		T3	6		T9	8
valid_sources[0x41]	23597	1			T2	27		T3	4		T9	5
valid_sources[0x42]	17098	1			T2	7		T3	2		T9	4
valid_sources[0x43]	18312	1			T2	20		T3	1		T9	5
valid_sources[0x44]	17945	1			T2	11		T3	7		T9	7
valid_sources[0x45]	18095	1			T2	24		T3	3		T9	4
valid_sources[0x46]	18998	1			T2	6		T3	6		T9	3
valid_sources[0x47]	16324	1			T2	1		T3	7		T9	2
valid_sources[0x48]	16881	1			T2	14		T3	1		T9	7
valid_sources[0x49]	17628	1			T2	4		T3	4		T9	5
valid_sources[0x4a]	23525	1			T2	1		T3	9		T9	4
valid_sources[0x4b]	58935	1			T2	16		T3	7		T9	5
valid_sources[0x4c]	18683	1			T2	9		T3	7		T9	3
valid_sources[0x4d]	17894	1			T2	74		T3	4		T9	5
valid_sources[0x4e]	18596	1			T2	41		T3	5		T9	5
valid_sources[0x4f]	16442	1			T2	16		T3	6		T9	6
valid_sources[0x50]	21591	1			T2	10		T3	11		T9	7
valid_sources[0x51]	17776	1			T2	10		T9	4		T12	8
valid_sources[0x52]	18168	1			T2	11		T3	10		T9	6
valid_sources[0x53]	18360	1			T2	53		T3	1		T9	3
valid_sources[0x54]	23531	1			T2	2		T3	8		T9	10
valid_sources[0x55]	22316	1			T2	13		T3	6		T9	6
valid_sources[0x56]	16922	1			T2	14		T3	4		T9	3
valid_sources[0x57]	15895	1			T2	8		T3	6		T9	9
valid_sources[0x58]	18329	1			T3	9		T9	1		T12	14
valid_sources[0x59]	26829	1			T2	14		T3	7		T9	3
valid_sources[0x5a]	18838	1			T3	5		T9	6		T12	5
valid_sources[0x5b]	18133	1			T2	50		T3	8		T9	6
valid_sources[0x5c]	16055	1			T2	40		T3	6		T9	10
valid_sources[0x5d]	17143	1			T3	7		T9	5		T12	25
valid_sources[0x5e]	16712	1			T2	15		T3	5		T9	5
valid_sources[0x5f]	19016	1			T2	33		T3	9		T9	2
valid_sources[0x60]	16643	1			T2	3		T3	5		T9	6
valid_sources[0x61]	17519	1			T2	26		T3	2		T9	10
valid_sources[0x62]	16840	1			T2	27		T3	16		T9	2
valid_sources[0x63]	16709	1			T2	16		T3	6		T9	4
valid_sources[0x64]	18541	1			T2	23		T3	10		T9	2
valid_sources[0x65]	15976	1			T2	6		T3	4		T9	8
valid_sources[0x66]	15966	1			T2	4		T3	8		T9	11
valid_sources[0x67]	18322	1			T2	20		T3	7		T9	8
valid_sources[0x68]	18879	1			T2	14		T3	1		T9	9
valid_sources[0x69]	52963	1			T2	10		T3	7		T9	2
valid_sources[0x6a]	20673	1			T2	12		T3	4		T9	6
valid_sources[0x6b]	17588	1			T2	5		T3	6		T9	5
valid_sources[0x6c]	22067	1			T2	33		T3	6		T9	6
valid_sources[0x6d]	17189	1			T2	10		T3	7		T9	6
valid_sources[0x6e]	21121	1			T2	79		T3	3		T9	4
valid_sources[0x6f]	18124	1			T3	2		T9	3		T12	22
valid_sources[0x70]	17603	1			T2	23		T3	7		T9	3
valid_sources[0x71]	20932	1			T2	39		T3	5		T9	2
valid_sources[0x72]	18423	1			T2	25		T3	7		T9	4
valid_sources[0x73]	39445	1			T2	17		T3	3		T9	5
valid_sources[0x74]	17521	1			T2	16		T3	7		T9	4
valid_sources[0x75]	18041	1			T3	3		T9	5		T12	4
valid_sources[0x76]	17267	1			T2	9		T3	2		T9	2
valid_sources[0x77]	18046	1			T2	17		T3	5		T9	3
valid_sources[0x78]	22149	1			T2	11		T3	3		T9	10
valid_sources[0x79]	16546	1			T2	24		T3	5		T9	7
valid_sources[0x7a]	17439	1			T2	40		T3	3		T9	5
valid_sources[0x7b]	17962	1			T2	2		T3	6		T9	6
valid_sources[0x7c]	20437	1			T2	19		T3	2		T9	2
valid_sources[0x7d]	16462	1			T2	19		T3	7		T9	4
valid_sources[0x7e]	16329	1			T2	9		T3	4		T9	2
valid_sources[0x7f]	15979	1			T2	10		T3	4		T9	3
valid_sources[0x80]	108087	1			T2	28		T3	6		T9	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2336127

1

T2

1075

T3

380

T9

359

values[0x0]

all_enables

biggest_size

280527

1

T2

543

T3

289

T9

249

values[0x1]

all_enables

biggest_size

278460

1

T2

522

T3

282

T9

266