Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.88		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	183622455	29053	0	0
claim_transition_if_regwen_rd_A	183622455	3219	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183622455	29053	0	0
T14	235803	7	0	0
T15	39971	0	0	0
T16	114377	0	0	0
T31	0	10	0	0
T35	957	0	0	0
T42	22634	0	0	0
T60	16523	0	0	0
T72	3846	0	0	0
T73	0	4	0	0
T74	1180	0	0	0
T98	2101	0	0	0
T99	1834	0	0	0
T111	0	6	0	0
T201	0	8	0	0
T202	0	8	0	0
T203	0	3	0	0
T204	0	5	0	0
T205	0	5	0	0
T206	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183622455	3219	0	0
T53	329178	12	0	0
T54	0	2	0	0
T93	3708	0	0	0
T205	0	6	0	0
T207	0	16	0	0
T208	0	9	0	0
T209	0	11	0	0
T210	0	7	0	0
T211	0	9	0	0
T212	0	5	0	0
T213	0	3	0	0
T214	4294	0	0	0
T215	1120	0	0	0
T216	69663	0	0	0
T217	19618	0	0	0
T218	1180	0	0	0
T219	117770	0	0	0
T220	3800	0	0	0
T221	25404	0	0	0