Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4047954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4505057

1

T1

662

T3

791

T9

810

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7837326	1			T1	539		T3	581		T9	663
values[0x0]	356761	1			T1	233		T3	280		T9	293
values[0x1]	358924	1			T1	247		T3	304		T9	291

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3217273	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5335738

1

T1

742

T3

868

T9

908

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24200	1			T1	3		T3	1		T9	3
valid_sources[0x01]	28548	1			T1	3		T3	4		T9	8
valid_sources[0x02]	25469	1			T1	1		T3	3		T9	1
valid_sources[0x03]	26191	1			T1	8		T3	6		T9	6
valid_sources[0x04]	24987	1			T1	7		T3	7		T9	5
valid_sources[0x05]	24526	1			T1	4		T3	11		T9	3
valid_sources[0x06]	24568	1			T1	2		T9	9		T10	6
valid_sources[0x07]	26803	1			T1	5		T3	3		T9	3
valid_sources[0x08]	24883	1			T1	4		T3	2		T9	1
valid_sources[0x09]	24460	1			T1	5		T3	5		T9	4
valid_sources[0x0a]	26159	1			T1	3		T3	7		T9	3
valid_sources[0x0b]	53350	1			T1	6		T3	3		T9	4
valid_sources[0x0c]	24201	1			T1	6		T3	3		T9	5
valid_sources[0x0d]	24251	1			T1	3		T3	6		T9	4
valid_sources[0x0e]	25514	1			T1	4		T3	5		T9	7
valid_sources[0x0f]	43583	1			T1	6		T3	5		T9	2
valid_sources[0x10]	26597	1			T1	2		T3	3		T9	6
valid_sources[0x11]	36864	1			T1	3		T3	4		T9	6
valid_sources[0x12]	28964	1			T1	3		T3	5		T9	5
valid_sources[0x13]	25102	1			T1	3		T3	9		T9	5
valid_sources[0x14]	35473	1			T1	3		T3	3		T9	3
valid_sources[0x15]	25932	1			T1	4		T3	4		T9	5
valid_sources[0x16]	26736	1			T1	2		T3	4		T9	5
valid_sources[0x17]	24807	1			T1	5		T3	2		T9	10
valid_sources[0x18]	26061	1			T1	8		T3	5		T9	4
valid_sources[0x19]	55840	1			T1	1		T3	12		T9	4
valid_sources[0x1a]	29003	1			T3	1		T9	1		T10	3
valid_sources[0x1b]	24247	1			T1	6		T3	4		T9	5
valid_sources[0x1c]	24357	1			T1	4		T3	5		T9	7
valid_sources[0x1d]	24831	1			T1	6		T3	4		T9	9
valid_sources[0x1e]	28012	1			T1	5		T3	1		T9	5
valid_sources[0x1f]	25876	1			T1	2		T3	2		T9	7
valid_sources[0x20]	24675	1			T1	1		T3	1		T9	5
valid_sources[0x21]	34478	1			T1	1		T3	7		T9	5
valid_sources[0x22]	25411	1			T1	4		T3	3		T9	8
valid_sources[0x23]	24344	1			T1	5		T3	10		T9	1
valid_sources[0x24]	29147	1			T1	6		T3	4		T9	7
valid_sources[0x25]	25166	1			T1	2		T3	10		T9	7
valid_sources[0x26]	27184	1			T1	4		T3	4		T9	7
valid_sources[0x27]	24682	1			T1	8		T3	7		T9	2
valid_sources[0x28]	24808	1			T1	1		T3	1		T9	5
valid_sources[0x29]	24975	1			T1	4		T3	2		T9	3
valid_sources[0x2a]	24058	1			T1	3		T3	3		T9	4
valid_sources[0x2b]	24612	1			T1	2		T3	9		T9	3
valid_sources[0x2c]	54786	1			T1	4		T3	5		T9	3
valid_sources[0x2d]	49798	1			T1	4		T3	5		T9	3
valid_sources[0x2e]	25959	1			T1	7		T3	3		T9	2
valid_sources[0x2f]	24713	1			T1	4		T3	4		T9	6
valid_sources[0x30]	57161	1			T1	4		T3	3		T9	2
valid_sources[0x31]	24806	1			T1	4		T3	6		T9	5
valid_sources[0x32]	34944	1			T1	3		T3	9		T9	5
valid_sources[0x33]	25035	1			T1	6		T3	4		T9	8
valid_sources[0x34]	88243	1			T1	4		T3	4		T9	1
valid_sources[0x35]	24336	1			T1	4		T3	8		T9	5
valid_sources[0x36]	50944	1			T1	4		T3	6		T9	3
valid_sources[0x37]	95011	1			T1	3		T3	5		T9	5
valid_sources[0x38]	41920	1			T1	2		T3	3		T9	3
valid_sources[0x39]	25078	1			T1	5		T3	3		T9	5
valid_sources[0x3a]	24298	1			T1	3		T3	2		T9	6
valid_sources[0x3b]	24650	1			T1	4		T3	4		T9	4
valid_sources[0x3c]	131177	1			T1	3		T3	5		T9	6
valid_sources[0x3d]	25812	1			T1	3		T3	1		T9	3
valid_sources[0x3e]	26497	1			T1	5		T3	5		T9	6
valid_sources[0x3f]	25573	1			T1	2		T3	6		T9	11
valid_sources[0x40]	26606	1			T1	7		T3	3		T9	2
valid_sources[0x41]	24846	1			T1	3		T3	8		T9	3
valid_sources[0x42]	24765	1			T1	3		T3	2		T9	2
valid_sources[0x43]	25184	1			T1	8		T3	6		T9	2
valid_sources[0x44]	24421	1			T1	1		T3	5		T9	4
valid_sources[0x45]	26737	1			T1	3		T3	2		T9	4
valid_sources[0x46]	33399	1			T1	5		T3	5		T9	3
valid_sources[0x47]	28635	1			T1	3		T3	6		T9	4
valid_sources[0x48]	25759	1			T1	3		T3	5		T9	3
valid_sources[0x49]	24885	1			T1	6		T3	5		T9	5
valid_sources[0x4a]	24688	1			T1	2		T3	8		T9	4
valid_sources[0x4b]	25386	1			T1	3		T3	6		T9	5
valid_sources[0x4c]	24657	1			T1	3		T3	2		T9	7
valid_sources[0x4d]	25359	1			T1	1		T9	4		T10	4
valid_sources[0x4e]	105508	1			T1	4		T3	11		T9	9
valid_sources[0x4f]	25504	1			T1	7		T3	11		T9	6
valid_sources[0x50]	24447	1			T1	2		T3	2		T9	2
valid_sources[0x51]	53251	1			T1	1		T3	1		T9	5
valid_sources[0x52]	24921	1			T1	9		T3	5		T9	1
valid_sources[0x53]	188239	1			T1	3		T3	7		T9	3
valid_sources[0x54]	77742	1			T3	7		T9	3		T10	1
valid_sources[0x55]	24595	1			T1	5		T3	3		T9	2
valid_sources[0x56]	25123	1			T1	3		T3	5		T9	12
valid_sources[0x57]	24467	1			T1	2		T3	1		T9	4
valid_sources[0x58]	24275	1			T1	4		T9	6		T10	7
valid_sources[0x59]	24301	1			T1	7		T3	5		T9	4
valid_sources[0x5a]	24921	1			T1	4		T3	3		T9	3
valid_sources[0x5b]	24509	1			T1	2		T3	1		T9	9
valid_sources[0x5c]	58578	1			T1	1		T3	5		T9	6
valid_sources[0x5d]	26838	1			T1	5		T3	6		T9	1
valid_sources[0x5e]	24313	1			T1	4		T9	3		T10	6
valid_sources[0x5f]	44163	1			T1	5		T3	1		T9	4
valid_sources[0x60]	24187	1			T1	7		T3	5		T9	5
valid_sources[0x61]	63067	1			T1	3		T3	8		T9	3
valid_sources[0x62]	28077	1			T1	2		T3	1		T9	5
valid_sources[0x63]	40262	1			T1	5		T3	5		T9	8
valid_sources[0x64]	28092	1			T1	6		T3	3		T9	4
valid_sources[0x65]	24954	1			T1	6		T3	3		T9	7
valid_sources[0x66]	29027	1			T1	6		T3	2		T9	9
valid_sources[0x67]	26035	1			T1	4		T3	2		T9	6
valid_sources[0x68]	24175	1			T1	2		T3	7		T9	4
valid_sources[0x69]	27135	1			T1	4		T3	1		T9	8
valid_sources[0x6a]	92952	1			T1	3		T3	10		T9	8
valid_sources[0x6b]	24089	1			T1	6		T3	4		T9	4
valid_sources[0x6c]	25858	1			T1	6		T3	3		T9	5
valid_sources[0x6d]	24770	1			T1	4		T3	4		T9	6
valid_sources[0x6e]	27001	1			T1	5		T3	2		T9	5
valid_sources[0x6f]	94984	1			T3	5		T9	3		T10	3
valid_sources[0x70]	56071	1			T1	4		T3	5		T9	11
valid_sources[0x71]	24264	1			T1	5		T3	3		T9	4
valid_sources[0x72]	26386	1			T1	5		T3	4		T9	2
valid_sources[0x73]	25888	1			T1	4		T3	5		T9	8
valid_sources[0x74]	24664	1			T1	2		T3	8		T9	7
valid_sources[0x75]	24835	1			T3	10		T9	3		T10	6
valid_sources[0x76]	25012	1			T1	4		T3	4		T10	7
valid_sources[0x77]	26624	1			T1	6		T3	2		T9	6
valid_sources[0x78]	24708	1			T1	3		T3	2		T9	5
valid_sources[0x79]	24864	1			T1	8		T3	10		T9	4
valid_sources[0x7a]	26305	1			T1	1		T9	3		T4	13
valid_sources[0x7b]	36335	1			T1	5		T3	6		T9	8
valid_sources[0x7c]	27216	1			T1	4		T3	5		T9	3
valid_sources[0x7d]	24547	1			T1	7		T3	5		T9	9
valid_sources[0x7e]	28470	1			T1	3		T3	2		T9	3
valid_sources[0x7f]	40346	1			T1	3		T3	5		T9	7
valid_sources[0x80]	27163	1			T1	2		T3	4		T9	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3887482

1

T1

240

T3

287

T9

306

values[0x0]

all_enables

biggest_size

309738

1

T1

207

T3

246

T9

255

values[0x1]

all_enables

biggest_size

307837

1

T1

215

T3

258

T9

249