Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.88		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	228419859	29583	0	0
claim_transition_if_regwen_rd_A	228419859	2849	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228419859	29583	0	0
T17	215236	2	0	0
T18	101196	0	0	0
T19	65274	0	0	0
T20	372738	0	0	0
T31	31223	0	0	0
T32	4060	0	0	0
T45	0	4	0	0
T47	0	4	0	0
T61	203493	11	0	0
T64	0	12	0	0
T66	28096	0	0	0
T93	26050	0	0	0
T104	0	2	0	0
T156	0	3	0	0
T157	0	10	0	0
T158	0	8	0	0
T159	0	2	0	0
T160	21386	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228419859	2849	0	0
T24	33634	0	0	0
T45	266485	10	0	0
T46	27073	0	0	0
T54	39007	0	0	0
T104	0	4	0	0
T114	0	270	0	0
T159	0	21	0	0
T161	0	12	0	0
T162	0	7	0	0
T163	0	2	0	0
T164	0	6	0	0
T165	0	1	0	0
T166	0	6	0	0
T167	12136	0	0	0
T168	24802	0	0	0
T169	42614	0	0	0
T170	5491	0	0	0
T171	12324	0	0	0
T172	988	0	0	0