Unified Coverage Report :: Module

Module : lc_ctrl_fsm_cov_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.51	97.77	89.13		100.00	97.30	93.33	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_fsm_cov_if

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	77	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv' or '../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
77	1	1
78	1	1
79	1	1
81	1	1
82	1	1
85	1	1
86	1	1
			MISSING_ELSE
89	1	1
90	1	1
			MISSING_ELSE

Cond Coverage for Module : lc_ctrl_fsm_cov_if

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION (trans_invalid_error_o & ((~trans_invalid_error)))
             ----------1----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T36
1	1	Covered	T3,T9,T10

 LINE       77
 EXPRESSION (rst_ni == 1'b0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       85
 EXPRESSION (((~token_mux_idx_error_prev)) & token_mux_idx_error)
             --------------1--------------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

 LINE       89
 EXPRESSION (((~token_invalid_error_o_prev)) & token_invalid_error_o)
             ---------------1---------------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

Branch Coverage for Module : lc_ctrl_fsm_cov_if

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	77	2	2	100.00
IF	85	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv' or '../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	77	if ((rst_ni == 1'b0))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	85	if (((~token_mux_idx_error_prev) & token_mux_idx_error))

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	if (((~token_invalid_error_o_prev) & token_invalid_error_o))

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3