Unified Coverage Report :: Module :: lc_ctrl_state_transition

Module : lc_ctrl_state_transition

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.07	97.01	66.67			91.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition	88.95	98.48	72.00			96.36

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.95	98.48	72.00			96.36

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.95	98.48	72.00			96.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.51	97.77	89.13		100.00	97.30	93.33	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
TOTAL		67	65	97.01
ALWAYS	52	67	65	97.01

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
53	1	1
54	1	1
55	1	1
63	1	1
66	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
73	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
106	1	1
107	1	1
108	1	1
109	1	1
118	1	1
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
			MISSING_ELSE
125	1	1
133	1	1
140	1	1
147	1	1
148	0	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
172	1	1
175	0	1
180	1	1
201	1	1
			MISSING_ELSE

---

Cond Coverage for Module : lc_ctrl_state_transition

	Total	Covered	Percent
Conditions	27	18	66.67
Logical	27	18	66.67
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && (fsm_state_i == IdleSt))
             -----------1----------    ----------2----------    -----3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Covered	T1,T2,T3
-	1	0	1	Covered	T33,T6,T30
-	1	1	0	Not Covered
-	1	1	1	Covered	T33,T30,T34

 LINE       63
 SUB-EXPRESSION (fsm_state_i == IdleSt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || 
      2  (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))

-1-	-2-	Status	Tests
0	0	Covered	T33,T30,T34
0	1	Not Covered
1	0	Not Covered

 LINE       66
 SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T33,T30,T34
1	Covered	T30,T34,T35

 LINE       66
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T33,T30,T34
1	Covered	T30,T34,T35

 LINE       118
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i[0] <= DecLcStScrap) && 
      2  (trans_target_i[0] <= DecLcStScrap) && 
      3  (dec_lc_state_i[1] <= DecLcStScrap) && 
      4  (trans_target_i[1] <= DecLcStScrap))

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION 
 Number  Term
      1  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || 
      2  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T36
0	1	Not Covered
1	0	Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T4,T13,T36
1	Covered	T1,T2,T3

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T4,T13,T36
1	Covered	T1,T2,T3

---

Branch Coverage for Module : lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
Branches		59	54	91.53
IF	63	3	3	100.00
IF	73	29	28	96.55
IF	125	27	23	85.19

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if ((((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i) && (fsm_state_i == IdleSt)))
-2-:	66	if (((dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T30,T34,T35
1	0	Covered	T33,T30,T34
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((fsm_state_i inside {CntIncrSt, CntProgSt, TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	84	case (lc_cnt_i)
-3-:	118	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}))

Branches:

-1-	-2-	-3-	Status	Tests
1	LcCnt0	-	Covered	T3,T4,T17
1	LcCnt1	-	Covered	T1,T2,T3
1	LcCnt2	-	Covered	T1,T3,T9
1	LcCnt3	-	Covered	T3,T9,T10
1	LcCnt4	-	Covered	T1,T3,T9
1	LcCnt5	-	Covered	T1,T3,T9
1	LcCnt6	-	Covered	T1,T2,T3
1	LcCnt7	-	Covered	T1,T2,T3
1	LcCnt8	-	Covered	T1,T3,T9
1	LcCnt9	-	Covered	T1,T2,T3
1	LcCnt10	-	Covered	T1,T3,T9
1	LcCnt11	-	Covered	T3,T9,T10
1	LcCnt12	-	Covered	T1,T3,T9
1	LcCnt13	-	Covered	T1,T3,T9
1	LcCnt14	-	Covered	T1,T2,T3
1	LcCnt15	-	Covered	T1,T3,T9
1	LcCnt16	-	Covered	T1,T3,T9
1	LcCnt17	-	Covered	T1,T3,T9
1	LcCnt18	-	Covered	T1,T3,T9
1	LcCnt19	-	Covered	T1,T3,T9
1	LcCnt20	-	Covered	T1,T3,T9
1	LcCnt21	-	Covered	T1,T3,T9
1	LcCnt22	-	Covered	T1,T3,T9
1	LcCnt23	-	Covered	T3,T9,T10
1	LcCnt24	-	Covered	T4,T13,T36
1	default	-	Not Covered
1	-	1	Covered	T1,T2,T3
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	if ((fsm_state_i inside {TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	133	if (((((dec_lc_state_i[0] <= DecLcStScrap) && (trans_target_i[0] <= DecLcStScrap)) && (dec_lc_state_i[1] <= DecLcStScrap)) && (trans_target_i[1] <= DecLcStScrap)))
-3-:	140	if (((lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)))
-4-:	147	case (trans_target_i)
-5-:	180	case (dec_lc_state_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}	-	Covered	T1,T3,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}}	-	Covered	T1,T4,T11
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}}	-	Covered	T9,T10,T11
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}}	-	Covered	T1,T2,T3
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}}	-	Covered	T3,T9,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}}	-	Covered	T3,T9,T4
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}}	-	Covered	T3,T10,T4
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}}	-	Covered	T1,T9,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}}	-	Covered	T3,T10,T4
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}}	-	Covered	T1,T3,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}}	-	Covered	T1,T2,T3
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	-	Covered	T1,T2,T3
1	1	1	default	-	Not Covered
1	1	0	-	-	Covered	T4,T13,T36
1	0	-	-	-	Not Covered
1	-	-	-	CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	Covered	T1,T2,T3
1	-	-	-	default	Not Covered
0	-	-	-	-	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
TOTAL		66	65	98.48
ALWAYS	52	66	65	98.48

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
53	1	1
54	1	1
55	1	1
63	1	1
66	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
73	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
99	1	1
100	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
106	1	1
107	1	1
108	1	1
109	1	1
			Exclude Annotation: VC_COV_UNR
118	1	1
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
			MISSING_ELSE
125	1	1
133	1	1
140	1	1
147	1	1
148		excluded
			Exclude Annotation: VC_COV_UNR
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
172	1	1
175	0	1
180	1	1
201	1	1
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

	Total	Covered	Percent
Conditions	25	18	72.00
Logical	25	18	72.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && (fsm_state_i == IdleSt))
             -----------1----------    ----------2----------    -----3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Covered	T1,T2,T3
-	1	0	1	Covered	T33,T6,T30
-	1	1	0	Not Covered
-	1	1	1	Covered	T33,T30,T34

 LINE       63
 SUB-EXPRESSION (fsm_state_i == IdleSt)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || 
      2  (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))

-1-	-2-	Status	Tests
0	0	Covered	T33,T30,T34
0	1	Not Covered
1	0	Not Covered

 LINE       66
 SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T33,T30,T34
1	Covered	T30,T34,T35

 LINE       66
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T33,T30,T34
1	Covered	T30,T34,T35

 LINE       118
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i[0] <= DecLcStScrap) && 
      2  (trans_target_i[0] <= DecLcStScrap) && 
      3  (dec_lc_state_i[1] <= DecLcStScrap) && 
      4  (trans_target_i[1] <= DecLcStScrap))

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION 
 Number  Term
      1  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || 
      2  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T36
0	1	Not Covered
1	0	Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T4,T13,T36
1	Covered	T1,T2,T3

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T4,T13,T36
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
IF	63	2	2	100.00
IF	73	28	28	100.00
IF	125	25	23	92.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if ((((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i) && (fsm_state_i == IdleSt)))
-2-:	66	if (((dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})))

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Covered	T30,T34,T35
1	0	Excluded	T33,T30,T34	VC_COV_UNR
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((fsm_state_i inside {CntIncrSt, CntProgSt, TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	84	case (lc_cnt_i)
-3-:	118	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	LcCnt0	-	Covered	T3,T4,T17
1	LcCnt1	-	Covered	T1,T2,T3
1	LcCnt2	-	Covered	T1,T3,T9
1	LcCnt3	-	Covered	T3,T9,T10
1	LcCnt4	-	Covered	T1,T3,T9
1	LcCnt5	-	Covered	T1,T3,T9
1	LcCnt6	-	Covered	T1,T2,T3
1	LcCnt7	-	Covered	T1,T2,T3
1	LcCnt8	-	Covered	T1,T3,T9
1	LcCnt9	-	Covered	T1,T2,T3
1	LcCnt10	-	Covered	T1,T3,T9
1	LcCnt11	-	Covered	T3,T9,T10
1	LcCnt12	-	Covered	T1,T3,T9
1	LcCnt13	-	Covered	T1,T3,T9
1	LcCnt14	-	Covered	T1,T2,T3
1	LcCnt15	-	Covered	T1,T3,T9
1	LcCnt16	-	Covered	T1,T3,T9
1	LcCnt17	-	Covered	T1,T3,T9
1	LcCnt18	-	Covered	T1,T3,T9
1	LcCnt19	-	Covered	T1,T3,T9
1	LcCnt20	-	Covered	T1,T3,T9
1	LcCnt21	-	Covered	T1,T3,T9
1	LcCnt22	-	Covered	T1,T3,T9
1	LcCnt23	-	Covered	T3,T9,T10
1	LcCnt24	-	Covered	T4,T13,T36
1	default	-	Excluded		VC_COV_UNR
1	-	1	Covered	T1,T2,T3
1	-	0	Covered	T1,T2,T3
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	if ((fsm_state_i inside {TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	133	if (((((dec_lc_state_i[0] <= DecLcStScrap) && (trans_target_i[0] <= DecLcStScrap)) && (dec_lc_state_i[1] <= DecLcStScrap)) && (trans_target_i[1] <= DecLcStScrap)))
-3-:	140	if (((lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)))
-4-:	147	case (trans_target_i)
-5-:	180	case (dec_lc_state_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}	-	Excluded		VC_COV_UNR
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}	-	Covered	T1,T3,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}}	-	Covered	T1,T4,T11
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}}	-	Covered	T9,T10,T11
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}}	-	Covered	T1,T2,T3
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}}	-	Covered	T3,T9,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}}	-	Covered	T3,T9,T4
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}}	-	Covered	T3,T10,T4
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}}	-	Covered	T1,T9,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}}	-	Covered	T3,T10,T4
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}}	-	Covered	T1,T3,T10
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}}	-	Covered	T1,T2,T3
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}	-	Covered	T1,T3,T9
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	-	Covered	T1,T2,T3
1	1	1	default	-	Not Covered
1	1	0	-	-	Covered	T4,T13,T36
1	0	-	-	-	Not Covered
1	-	-	-	CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	Covered	T1,T2,T3
1	-	-	-	default	Excluded		VC_COV_UNR
0	-	-	-	-	Covered	T1,T2,T3