Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1933693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2153311

1

T2

4

T3

16

T10

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3746238	1			T10	2		T4	170		T5	164
values[0x0]	169701	1			T2	6		T3	26		T10	3
values[0x1]	171065	1			T2	5		T3	14		T10	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1538212	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2548792

1

T2

5

T3

21

T10

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13333	1			T5	4		T12	8		T17	3
valid_sources[0x01]	14140	1			T6	2		T12	10		T13	3
valid_sources[0x02]	14121	1			T6	6		T12	3		T17	2
valid_sources[0x03]	13330	1			T6	4		T12	1		T17	5
valid_sources[0x04]	14369	1			T4	4		T6	3		T12	7
valid_sources[0x05]	13631	1			T5	6		T6	2		T12	5
valid_sources[0x06]	14574	1			T6	7		T12	4		T13	6
valid_sources[0x07]	14320	1			T4	4		T5	2		T6	8
valid_sources[0x08]	13478	1			T4	5		T6	4		T12	13
valid_sources[0x09]	14220	1			T5	6		T6	4		T12	1
valid_sources[0x0a]	14640	1			T4	5		T5	2		T6	3
valid_sources[0x0b]	13620	1			T6	3		T12	16		T17	4
valid_sources[0x0c]	13356	1			T4	2		T5	3		T6	1
valid_sources[0x0d]	14563	1			T2	1		T4	1		T6	2
valid_sources[0x0e]	14135	1			T12	3		T17	3		T88	3
valid_sources[0x0f]	13645	1			T6	5		T12	2		T17	4
valid_sources[0x10]	13786	1			T4	1		T6	1		T17	7
valid_sources[0x11]	13785	1			T6	4		T12	2		T23	5
valid_sources[0x12]	13525	1			T4	7		T6	2		T12	2
valid_sources[0x13]	15167	1			T11	4		T6	2		T17	6
valid_sources[0x14]	15599	1			T11	1		T6	2		T12	6
valid_sources[0x15]	14063	1			T4	2		T5	1		T13	1
valid_sources[0x16]	13960	1			T2	1		T6	2		T12	1
valid_sources[0x17]	14452	1			T4	1		T6	2		T12	10
valid_sources[0x18]	14305	1			T4	14		T5	10		T6	2
valid_sources[0x19]	15223	1			T6	5		T12	11		T17	4
valid_sources[0x1a]	14482	1			T6	5		T12	4		T13	3
valid_sources[0x1b]	27374	1			T11	2		T6	5		T17	4
valid_sources[0x1c]	14598	1			T6	4		T17	7		T23	5
valid_sources[0x1d]	13264	1			T6	1		T12	12		T23	2
valid_sources[0x1e]	14918	1			T11	5		T12	1		T17	4
valid_sources[0x1f]	13789	1			T4	12		T6	3		T12	1
valid_sources[0x20]	13643	1			T6	2		T12	26		T13	2
valid_sources[0x21]	13082	1			T4	2		T6	1		T13	1
valid_sources[0x22]	13683	1			T6	1		T12	4		T23	6
valid_sources[0x23]	14788	1			T6	3		T12	2		T17	1
valid_sources[0x24]	13218	1			T4	2		T6	3		T12	12
valid_sources[0x25]	15354	1			T4	4		T5	2		T6	1
valid_sources[0x26]	15974	1			T6	5		T12	21		T17	2
valid_sources[0x27]	16432	1			T6	2		T12	1		T17	5
valid_sources[0x28]	14974	1			T6	2		T12	6		T13	17
valid_sources[0x29]	15484	1			T4	2		T6	3		T12	8
valid_sources[0x2a]	13561	1			T11	1		T12	6		T13	1
valid_sources[0x2b]	15486	1			T5	2		T6	1		T12	16
valid_sources[0x2c]	13391	1			T6	2		T12	14		T17	2
valid_sources[0x2d]	15180	1			T5	8		T6	1		T12	10
valid_sources[0x2e]	12890	1			T5	10		T6	1		T12	3
valid_sources[0x2f]	15249	1			T11	3		T6	4		T12	7
valid_sources[0x30]	14042	1			T6	4		T12	5		T13	2
valid_sources[0x31]	13528	1			T12	4		T17	1		T23	1
valid_sources[0x32]	15213	1			T2	1		T6	1		T12	4
valid_sources[0x33]	14015	1			T4	5		T6	7		T12	3
valid_sources[0x34]	14696	1			T2	1		T6	1		T12	1
valid_sources[0x35]	14820	1			T11	2		T6	5		T12	2
valid_sources[0x36]	13288	1			T6	1		T12	19		T17	5
valid_sources[0x37]	13188	1			T6	2		T12	1		T23	7
valid_sources[0x38]	14029	1			T3	2		T4	23		T11	2
valid_sources[0x39]	14346	1			T5	1		T6	2		T12	4
valid_sources[0x3a]	12845	1			T4	1		T6	1		T12	3
valid_sources[0x3b]	13201	1			T5	3		T6	1		T12	14
valid_sources[0x3c]	14739	1			T5	8		T6	5		T12	7
valid_sources[0x3d]	14295	1			T5	17		T6	3		T12	11
valid_sources[0x3e]	14832	1			T11	3		T5	7		T6	5
valid_sources[0x3f]	13055	1			T2	1		T5	1		T6	1
valid_sources[0x40]	13175	1			T6	2		T12	1		T17	1
valid_sources[0x41]	13772	1			T4	20		T23	1		T88	4
valid_sources[0x42]	13728	1			T6	2		T12	9		T23	2
valid_sources[0x43]	15720	1			T4	7		T6	3		T12	2
valid_sources[0x44]	13742	1			T4	2		T6	4		T12	1
valid_sources[0x45]	13482	1			T4	13		T6	1		T17	1
valid_sources[0x46]	14759	1			T6	1		T12	4		T17	8
valid_sources[0x47]	13862	1			T2	1		T6	4		T12	9
valid_sources[0x48]	13556	1			T4	2		T6	13		T12	2
valid_sources[0x49]	14529	1			T6	1		T12	3		T17	2
valid_sources[0x4a]	13769	1			T11	2		T6	6		T12	4
valid_sources[0x4b]	15018	1			T4	5		T12	5		T17	4
valid_sources[0x4c]	12715	1			T5	2		T6	3		T12	9
valid_sources[0x4d]	13167	1			T11	7		T6	3		T12	11
valid_sources[0x4e]	13424	1			T6	2		T12	6		T13	1
valid_sources[0x4f]	13704	1			T6	2		T12	2		T13	4
valid_sources[0x50]	16401	1			T5	4		T6	4		T12	3
valid_sources[0x51]	13727	1			T4	4		T6	1		T12	4
valid_sources[0x52]	14300	1			T4	3		T6	2		T12	6
valid_sources[0x53]	13584	1			T6	4		T12	9		T17	4
valid_sources[0x54]	13877	1			T5	6		T6	3		T12	2
valid_sources[0x55]	13395	1			T4	3		T6	7		T12	6
valid_sources[0x56]	13727	1			T11	1		T5	5		T6	4
valid_sources[0x57]	13949	1			T6	4		T12	5		T13	1
valid_sources[0x58]	13394	1			T11	2		T6	1		T12	12
valid_sources[0x59]	13387	1			T4	2		T6	8		T12	12
valid_sources[0x5a]	15465	1			T4	2		T6	2		T17	6
valid_sources[0x5b]	13688	1			T5	1		T6	2		T12	1
valid_sources[0x5c]	16592	1			T6	3		T12	4		T23	5
valid_sources[0x5d]	13500	1			T6	2		T12	8		T17	12
valid_sources[0x5e]	14859	1			T11	1		T6	1		T12	16
valid_sources[0x5f]	14918	1			T6	3		T17	2		T23	3
valid_sources[0x60]	15556	1			T6	4		T17	6		T88	3
valid_sources[0x61]	15213	1			T6	2		T17	7		T23	11
valid_sources[0x62]	13298	1			T11	2		T5	12		T6	1
valid_sources[0x63]	13632	1			T6	1		T12	12		T23	3
valid_sources[0x64]	13239	1			T5	3		T6	2		T12	12
valid_sources[0x65]	14113	1			T4	3		T11	2		T6	1
valid_sources[0x66]	18566	1			T4	2		T11	3		T6	3
valid_sources[0x67]	14114	1			T4	13		T6	3		T13	1
valid_sources[0x68]	14110	1			T6	1		T12	3		T17	3
valid_sources[0x69]	15189	1			T6	1		T12	2		T13	1
valid_sources[0x6a]	13444	1			T6	4		T12	3		T17	17
valid_sources[0x6b]	13245	1			T6	4		T12	12		T23	4
valid_sources[0x6c]	13229	1			T5	17		T6	1		T12	1
valid_sources[0x6d]	15916	1			T6	3		T12	6		T88	5
valid_sources[0x6e]	16537	1			T6	3		T12	2		T17	6
valid_sources[0x6f]	24166	1			T4	4		T19	4		T24	10
valid_sources[0x70]	13696	1			T6	11		T12	12		T13	3
valid_sources[0x71]	13720	1			T11	2		T6	2		T12	5
valid_sources[0x72]	14167	1			T4	1		T6	2		T12	5
valid_sources[0x73]	13750	1			T4	6		T11	2		T6	1
valid_sources[0x74]	13212	1			T6	3		T13	2		T17	4
valid_sources[0x75]	14319	1			T17	2		T23	2		T19	3
valid_sources[0x76]	13030	1			T5	12		T6	6		T12	10
valid_sources[0x77]	13881	1			T23	2		T19	4		T88	3
valid_sources[0x78]	14046	1			T4	2		T5	3		T6	1
valid_sources[0x79]	14603	1			T6	3		T12	3		T17	5
valid_sources[0x7a]	20487	1			T5	3		T6	4		T12	8
valid_sources[0x7b]	14645	1			T5	10		T6	1		T12	5
valid_sources[0x7c]	13381	1			T6	2		T12	3		T17	5
valid_sources[0x7d]	13569	1			T6	2		T12	1		T18	335
valid_sources[0x7e]	13192	1			T2	1		T6	3		T12	25
valid_sources[0x7f]	13027	1			T4	1		T6	2		T12	18
valid_sources[0x80]	13726	1			T4	1		T6	1		T12	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1858950

1

T4

80

T5

90

T6

159

values[0x0]

all_enables

biggest_size

147479

1

T2

3

T3

13

T10

1

values[0x1]

all_enables

biggest_size

146882

1

T2

1

T3

3

T10

5