Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108143875	13175	0	0
claim_transition_if_regwen_rd_A	108143875	1803	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108143875	13175	0	0
T8	27483	0	0	0
T9	37037	0	0	0
T14	490627	12	0	0
T15	1233	0	0	0
T20	28065	0	0	0
T40	0	3	0	0
T43	0	1	0	0
T53	0	8	0	0
T59	20996	0	0	0
T90	25505	0	0	0
T96	0	12	0	0
T117	0	1	0	0
T118	0	7	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	14	0	0
T158	1870	0	0	0
T159	1372	0	0	0
T160	22417	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108143875	1803	0	0
T40	138501	3	0	0
T43	0	1	0	0
T50	33413	0	0	0
T85	117774	0	0	0
T86	113473	11	0	0
T92	10389	0	0	0
T121	0	8	0	0
T128	0	69	0	0
T156	0	7	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	12	0	0
T164	0	136	0	0
T165	182448	0	0	0
T166	1019	0	0	0
T167	29526	0	0	0
T168	1468	0	0	0
T169	21234	0	0	0