LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	12.100s	208.940us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.110s	14.624us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.150s	15.491us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.590s	778.929us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.440s	28.158us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.790s	23.222us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.150s	15.491us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	28.158us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.910s	89.553us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	26.730s	7.509ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	12.086us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.530s	373.337us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.680s	3.431ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_prog_failure	6.530s	373.337us	50	50	100.00
		lc_ctrl_errors	24.680s	3.431ms	50	50	100.00
		lc_ctrl_security_escalation	19.900s	948.843us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.067m	16.729ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.190s	3.964ms	20	20	100.00
		lc_ctrl_jtag_errors	1.505m	6.551ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.040s	1.068ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	20.530s	4.362ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.190s	3.964ms	20	20	100.00
		lc_ctrl_jtag_errors	1.505m	6.551ms	20	20	100.00
		lc_ctrl_jtag_access	22.370s	1.893ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.130s	5.822ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.950s	320.277us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.510s	83.260us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	32.940s	5.747ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.230s	2.579ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.540s	22.977us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.550s	104.283us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.050s	251.767us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.060s	1.857ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.320s	127.931us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.697m	20.330ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.320s	27.900us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.810s	142.435us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.810s	142.435us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.110s	14.624us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	15.491us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	28.158us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.120s	46.806us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.110s	14.624us	5	5	100.00
		lc_ctrl_csr_rw	1.150s	15.491us	20	20	100.00
		lc_ctrl_csr_aliasing	1.440s	28.158us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.120s	46.806us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
		lc_ctrl_tl_intg_err	4.820s	137.573us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.820s	137.573us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	26.730s	7.509ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	34.220s	616.504us	50	50	100.00
		lc_ctrl_sec_cm	26.120s	213.785us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.900s	948.843us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.910s	89.553us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	20.530s	4.362ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.740s	670.289us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.740s	670.289us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	27.570s	852.552us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	18.050s	507.027us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	18.050s	507.027us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.992h	249.352ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1005	1030	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	97.82	96.21	93.31	97.62	98.52	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 18 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.72081789426185755929600073473587040439406441257493962746429354672566601498003
      Line 18962, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19661595249 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19661595249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.55675252243258516534854350294071256156698084313259812955526023539650055449826
      Line 17831, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21590396025 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21590396025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 25.lc_ctrl_stress_all_with_rand_reset.86998154716137930888060506387205053537270965937947808992371325604614516769777
      Line 67449, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 30.lc_ctrl_stress_all_with_rand_reset.19244284514760109954867179596067680018494844816804311555774527247454661606234
      Line 34364, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.102172644246709375236408906335142529845102489381277296716162972030241867802015
      Line 30672, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18371007474 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 18371007474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 38.lc_ctrl_stress_all_with_rand_reset.20364088821892429523594804045576254844070817230037065361823857793580213987560
      Line 10976, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2600798754 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2600798754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.95560491872049715550684445081040158601315899163077342567090302274769217388949
      Line 20598, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14870382335 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 14870382335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl_volatile_unlock_disabled-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.83214222616052872577597497915443735241970936739784417780308819572563872305562
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:4b986f47-e677-46ac-b508-e17188e3b03a
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.41667353461865079142706964181334304262764619140000750375465562522480391347987
      Line 4077, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21410537460 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 21410537460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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