LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.040s	1.627ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.680s	15.906us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.660s	31.593us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.820s	66.029us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.990s	114.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.570s	49.955us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.660s	31.593us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	114.939us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	18.370s	89.959us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.780s	773.771us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.470s	14.371us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.570s	105.977us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	35.800s	2.518ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_prog_failure	6.570s	105.977us	50	50	100.00
		lc_ctrl_errors	35.800s	2.518ms	50	50	100.00
		lc_ctrl_security_escalation	24.810s	1.245ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.099m	15.624ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.570s	3.228ms	20	20	100.00
		lc_ctrl_jtag_errors	1.448m	2.371ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.060s	1.427ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.940s	4.255ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.570s	3.228ms	20	20	100.00
		lc_ctrl_jtag_errors	1.448m	2.371ms	20	20	100.00
		lc_ctrl_jtag_access	32.720s	5.301ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.560s	1.136ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.680s	354.189us	10	10	100.00
		lc_ctrl_jtag_csr_rw	5.440s	292.216us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	29.640s	968.451us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.280s	2.722ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.830s	51.600us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	7.800s	967.833us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.940s	359.663us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.870s	3.672ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.650s	13.098us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.650m	16.319ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.930s	415.479us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.860s	263.841us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.860s	263.841us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.680s	15.906us	5	5	100.00
		lc_ctrl_csr_rw	1.660s	31.593us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	114.939us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.510s	268.873us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.680s	15.906us	5	5	100.00
		lc_ctrl_csr_rw	1.660s	31.593us	20	20	100.00
		lc_ctrl_csr_aliasing	1.990s	114.939us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.510s	268.873us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
		lc_ctrl_tl_intg_err	6.970s	625.977us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	6.970s	625.977us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.780s	773.771us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.108m	334.456us	50	50	100.00
		lc_ctrl_sec_cm	1.071m	415.475us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	24.810s	1.245ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	18.370s	89.959us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.940s	4.255ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	40.050s	963.694us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	40.050s	963.694us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	30.070s	1.221ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	26.650s	813.685us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	26.650s	813.685us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	57.238m	77.298ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.16	97.92	95.84	93.40	100.00	98.52	98.51	95.94

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 18 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.55114910258955033068481038200947157470654612859054184475739011093956716112966
      Line 8258, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10730366496 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10730366496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.lc_ctrl_stress_all_with_rand_reset.59532223890531927861067282397166423872701469446373811172761397500874177234143
      Line 31343, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31558374639 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 31558374639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 4 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.13798719116794735172926985051881489316470926880759714330825749921019614171077
      Line 22552, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20987867561 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 20987867561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.34273817967925506703916608764695309489387632302533001666515866017018769814438
      Line 6085, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4598086162 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 4598086162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

  • Test lc_ctrl_stress_all has 1 failures.

    • 16.lc_ctrl_stress_all.38418103817880620737830881470085476831146319234185559141505551814552746208782
      Line 938, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 5527213252 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 5527213252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.27299879531429483806110536128288295460166696819668578067958998693195241018749
      Line 63887, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 77298004649 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 77298004649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:238) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.9762446087574442244584716832317648064532995215868006300606455661038037941521
      Line 27910, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66996930553 ps: (lc_ctrl_scoreboard.sv:238) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 100, LC_St DecLcStTestUnlocked2
        UVM_INFO @ 66996930553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 23.lc_ctrl_stress_all_with_rand_reset.63275162950800316617814521175036968597293965776924646486180174076883400173533
      Line 77600, in log /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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