LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	11.980s	237.549us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.670s	30.015us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.640s	17.645us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.900s	92.242us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	2.300s	118.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.660s	156.113us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.640s	17.645us	20	20	100.00
		lc_ctrl_csr_aliasing	2.300s	118.976us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	14.090s	156.711us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	22.820s	332.088us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.430s	13.460us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	6.310s	681.962us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	30.920s	1.259ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_prog_failure	6.310s	681.962us	50	50	100.00
		lc_ctrl_errors	30.920s	1.259ms	50	50	100.00
		lc_ctrl_security_escalation	21.680s	5.255ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.273m	15.306ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.020s	3.565ms	20	20	100.00
		lc_ctrl_jtag_errors	1.661m	14.245ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.400s	632.959us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	41.640s	4.204ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.020s	3.565ms	20	20	100.00
		lc_ctrl_jtag_errors	1.661m	14.245ms	20	20	100.00
		lc_ctrl_jtag_access	26.160s	1.173ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.000s	2.464ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.410s	327.963us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.640s	351.111us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	48.900s	22.721ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.070s	621.550us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.360s	33.555us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.520s	192.842us	10	10	100.00
		lc_ctrl_jtag_alert_test	4.490s	636.570us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.990s	901.754us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.640s	14.046us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	13.712m	122.705ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	2.610s	336.642us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	6.770s	903.061us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	6.770s	903.061us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.670s	30.015us	5	5	100.00
		lc_ctrl_csr_rw	1.640s	17.645us	20	20	100.00
		lc_ctrl_csr_aliasing	2.300s	118.976us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.340s	42.089us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.670s	30.015us	5	5	100.00
		lc_ctrl_csr_rw	1.640s	17.645us	20	20	100.00
		lc_ctrl_csr_aliasing	2.300s	118.976us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.340s	42.089us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
		lc_ctrl_tl_intg_err	5.210s	144.412us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.210s	144.412us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	22.820s	332.088us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.150s	490.695us	50	50	100.00
		lc_ctrl_sec_cm	44.560s	249.228us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	21.680s	5.255ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	14.090s	156.711us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	41.640s	4.204ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	32.110s	1.478ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	32.110s	1.478ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	31.660s	3.859ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.730s	786.560us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.730s	786.560us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	3.019m	5.832ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.50	97.90	95.56	93.40	95.24	98.28	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 28 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.6916609005084145196431014666922313620387003213091033820459690861441409543400
      Line 3884, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9786143472 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9786143472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.23097758635495885724862636078267006218436852950758817923804844746208598078120
      Line 4118, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1861193695 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1861193695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 2 failures.

    • 26.lc_ctrl_stress_all.66535083744679736452972419733011610402362436414082600426174452055149601192133
      Line 10345, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 24847510380 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 24847510380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.lc_ctrl_stress_all.111861946082294024113011631205403452810948514655457153068611044664684493835612
      Line 5792, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2760010603 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 2760010603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.35194003929164357667488993124821691651547322809105634670351823750126748583009
      Line 1662, in log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 587703936 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 587703936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.88688828970580196933640839313155270825432720223253904342658504940950047031663
      Log /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

Past Results

• Latest
• 2024.10.13_03.39.03
• 2024.10.10_10.15.18
• 2024.10.04_00.42.11
• 2024.09.25_11.01.11
• 2024.09.19_09.04.56
• 2024.09.12_10.16.35
• 2024.09.10_08.11.26