Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1606188	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1824481

1

T1

58433

T2

759

T3

3228

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3092894	1			T1	114936		T2	652		T3	5261
values[0x0]	168360	1			T1	524		T2	293		T3	322
values[0x1]	169415	1			T1	510		T2	307		T3	372

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1275880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2154789

1

T1

70028

T2

881

T3

3787

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10483	1			T1	453		T2	7		T10	1
valid_sources[0x01]	10170	1			T1	430		T2	2		T8	1
valid_sources[0x02]	10325	1			T1	430		T2	8		T10	2
valid_sources[0x03]	9566	1			T1	492		T2	6		T14	60
valid_sources[0x04]	10371	1			T1	441		T2	5		T10	2
valid_sources[0x05]	10742	1			T1	447		T2	7		T14	87
valid_sources[0x06]	11126	1			T1	461		T2	5		T10	1
valid_sources[0x07]	9964	1			T1	478		T2	1		T14	52
valid_sources[0x08]	10767	1			T1	464		T2	6		T10	1
valid_sources[0x09]	10101	1			T1	479		T2	10		T10	1
valid_sources[0x0a]	18787	1			T1	474		T2	2		T14	54
valid_sources[0x0b]	9816	1			T1	449		T2	9		T10	2
valid_sources[0x0c]	9810	1			T1	428		T2	7		T10	4
valid_sources[0x0d]	11951	1			T1	478		T2	5		T14	58
valid_sources[0x0e]	11710	1			T1	480		T2	2		T8	2
valid_sources[0x0f]	10656	1			T1	442		T2	5		T14	58
valid_sources[0x10]	14229	1			T1	467		T2	3		T8	3
valid_sources[0x11]	10166	1			T1	413		T2	5		T10	1
valid_sources[0x12]	10079	1			T1	429		T2	2		T10	1
valid_sources[0x13]	101228	1			T1	431		T2	3		T8	1
valid_sources[0x14]	10469	1			T1	527		T2	3		T8	1
valid_sources[0x15]	69823	1			T1	426		T2	2		T14	77
valid_sources[0x16]	10272	1			T1	442		T2	6		T10	1
valid_sources[0x17]	10102	1			T1	500		T2	4		T3	17
valid_sources[0x18]	10289	1			T1	445		T2	8		T8	1
valid_sources[0x19]	10102	1			T1	481		T2	2		T8	1
valid_sources[0x1a]	10636	1			T1	455		T2	2		T14	59
valid_sources[0x1b]	10347	1			T1	441		T2	4		T14	59
valid_sources[0x1c]	10239	1			T1	474		T2	8		T8	1
valid_sources[0x1d]	10340	1			T1	483		T2	5		T10	1
valid_sources[0x1e]	12055	1			T1	468		T2	5		T10	3
valid_sources[0x1f]	9843	1			T1	436		T2	4		T8	1
valid_sources[0x20]	9972	1			T1	451		T2	5		T10	1
valid_sources[0x21]	10711	1			T1	427		T2	4		T8	6
valid_sources[0x22]	15153	1			T1	419		T2	5		T14	64
valid_sources[0x23]	10017	1			T1	460		T2	6		T8	3
valid_sources[0x24]	9946	1			T1	457		T2	3		T10	7
valid_sources[0x25]	10646	1			T1	444		T2	4		T10	1
valid_sources[0x26]	10092	1			T1	415		T2	5		T14	72
valid_sources[0x27]	12993	1			T1	432		T2	10		T10	1
valid_sources[0x28]	10750	1			T1	442		T2	7		T14	68
valid_sources[0x29]	9944	1			T1	428		T2	3		T10	1
valid_sources[0x2a]	20670	1			T1	452		T2	4		T3	17
valid_sources[0x2b]	10318	1			T1	469		T2	6		T14	61
valid_sources[0x2c]	11330	1			T1	466		T2	2		T14	45
valid_sources[0x2d]	10162	1			T1	480		T2	6		T14	56
valid_sources[0x2e]	10281	1			T1	462		T2	4		T14	48
valid_sources[0x2f]	21538	1			T1	442		T2	5		T8	2
valid_sources[0x30]	10748	1			T1	445		T2	5		T8	1
valid_sources[0x31]	10311	1			T1	466		T2	7		T10	3
valid_sources[0x32]	22793	1			T1	462		T2	3		T14	53
valid_sources[0x33]	9747	1			T1	498		T2	4		T8	4
valid_sources[0x34]	11218	1			T1	464		T2	2		T14	78
valid_sources[0x35]	10745	1			T1	438		T2	4		T14	64
valid_sources[0x36]	10398	1			T1	432		T2	1		T10	2
valid_sources[0x37]	10761	1			T1	415		T2	4		T10	1
valid_sources[0x38]	11802	1			T1	476		T2	3		T10	2
valid_sources[0x39]	10212	1			T1	446		T2	5		T14	49
valid_sources[0x3a]	10109	1			T1	451		T2	4		T8	1
valid_sources[0x3b]	10009	1			T1	439		T2	9		T14	61
valid_sources[0x3c]	10360	1			T1	433		T2	5		T14	65
valid_sources[0x3d]	38827	1			T1	434		T2	5		T10	1
valid_sources[0x3e]	10648	1			T1	470		T2	6		T10	2
valid_sources[0x3f]	10486	1			T1	440		T2	3		T14	67
valid_sources[0x40]	11510	1			T1	470		T2	4		T14	62
valid_sources[0x41]	12311	1			T1	418		T2	5		T14	59
valid_sources[0x42]	60716	1			T1	474		T2	9		T3	17
valid_sources[0x43]	11919	1			T1	460		T2	6		T10	1
valid_sources[0x44]	10049	1			T1	450		T2	1		T14	70
valid_sources[0x45]	10521	1			T1	436		T2	4		T8	1
valid_sources[0x46]	15936	1			T1	463		T2	5		T3	5802
valid_sources[0x47]	10000	1			T1	452		T2	5		T14	63
valid_sources[0x48]	11005	1			T1	424		T2	3		T8	2
valid_sources[0x49]	10350	1			T1	481		T2	6		T14	49
valid_sources[0x4a]	10691	1			T1	481		T2	7		T14	68
valid_sources[0x4b]	12084	1			T1	445		T2	3		T10	2
valid_sources[0x4c]	12180	1			T1	469		T2	12		T8	2
valid_sources[0x4d]	10497	1			T1	417		T2	6		T8	1
valid_sources[0x4e]	10099	1			T1	436		T2	2		T10	1
valid_sources[0x4f]	107226	1			T1	420		T2	2		T10	1
valid_sources[0x50]	10284	1			T1	443		T2	3		T10	1
valid_sources[0x51]	39067	1			T1	466		T2	11		T10	1
valid_sources[0x52]	10346	1			T1	407		T2	5		T8	2
valid_sources[0x53]	11840	1			T1	491		T2	6		T10	3
valid_sources[0x54]	10189	1			T1	468		T2	2		T10	1
valid_sources[0x55]	12156	1			T1	461		T2	8		T14	61
valid_sources[0x56]	10202	1			T1	456		T2	7		T14	69
valid_sources[0x57]	10264	1			T1	473		T2	3		T10	1
valid_sources[0x58]	25570	1			T1	468		T2	4		T10	1
valid_sources[0x59]	11496	1			T1	471		T2	7		T14	51
valid_sources[0x5a]	12346	1			T1	486		T2	6		T14	60
valid_sources[0x5b]	10587	1			T1	431		T2	2		T10	1
valid_sources[0x5c]	10148	1			T1	453		T2	5		T10	1
valid_sources[0x5d]	10470	1			T1	454		T2	7		T14	51
valid_sources[0x5e]	12180	1			T1	448		T2	5		T14	64
valid_sources[0x5f]	48988	1			T1	449		T2	4		T8	1
valid_sources[0x60]	10225	1			T1	466		T2	4		T14	68
valid_sources[0x61]	20794	1			T1	448		T2	5		T10	1
valid_sources[0x62]	11859	1			T1	463		T2	6		T14	46
valid_sources[0x63]	13727	1			T1	441		T2	7		T4	13
valid_sources[0x64]	10218	1			T1	428		T2	4		T14	70
valid_sources[0x65]	27266	1			T1	488		T2	4		T9	154
valid_sources[0x66]	9644	1			T1	468		T2	8		T14	73
valid_sources[0x67]	10390	1			T1	475		T2	7		T14	70
valid_sources[0x68]	10814	1			T1	471		T2	7		T8	1
valid_sources[0x69]	11190	1			T1	474		T2	1		T8	1
valid_sources[0x6a]	10399	1			T1	414		T2	3		T8	1
valid_sources[0x6b]	12504	1			T1	424		T2	5		T8	1
valid_sources[0x6c]	14359	1			T1	447		T2	4		T14	67
valid_sources[0x6d]	10202	1			T1	452		T2	5		T10	1
valid_sources[0x6e]	13888	1			T1	431		T2	5		T14	75
valid_sources[0x6f]	10297	1			T1	498		T2	3		T10	1
valid_sources[0x70]	26657	1			T1	451		T2	2		T14	76
valid_sources[0x71]	10022	1			T1	443		T2	8		T8	1
valid_sources[0x72]	10369	1			T1	446		T2	6		T14	61
valid_sources[0x73]	10154	1			T1	460		T2	3		T4	2
valid_sources[0x74]	10271	1			T1	444		T2	5		T14	61
valid_sources[0x75]	10406	1			T1	425		T2	3		T14	66
valid_sources[0x76]	11364	1			T1	454		T2	7		T14	55
valid_sources[0x77]	10199	1			T1	496		T2	2		T14	73
valid_sources[0x78]	11919	1			T1	486		T2	6		T14	50
valid_sources[0x79]	10086	1			T1	484		T2	3		T10	1
valid_sources[0x7a]	10283	1			T1	430		T2	2		T14	68
valid_sources[0x7b]	10581	1			T1	432		T2	5		T14	63
valid_sources[0x7c]	11298	1			T1	486		T2	3		T10	1
valid_sources[0x7d]	10867	1			T1	442		T2	5		T8	3
valid_sources[0x7e]	10519	1			T1	447		T2	9		T8	2
valid_sources[0x7f]	12496	1			T1	466		T2	6		T14	54
valid_sources[0x80]	10073	1			T1	468		T2	8		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1533371

1

T1

57543

T2

243

T3

2621

values[0x0]

all_enables

biggest_size

146126

1

T1

442

T2

254

T3

286

values[0x1]

all_enables

biggest_size

144984

1

T1

448

T2

262

T3

321